diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/quick/fs/10.linux-boot | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
13 files changed, 13365 insertions, 13514 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 7159169af..4c75131c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962843 # Number of seconds simulated -sim_ticks 1962842856000 # Number of ticks simulated -final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962613 # Number of seconds simulated +sim_ticks 1962612686500 # Number of ticks simulated +final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1228880 # Simulator instruction rate (inst/s) -host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39594262798 # Simulator tick rate (ticks/s) -host_mem_usage 373652 # Number of bytes of host memory used -host_seconds 49.57 # Real time elapsed on the host -sim_insts 60920382 # Number of instructions simulated -sim_ops 60920382 # Number of ops (including micro ops) simulated +host_inst_rate 1121045 # Simulator instruction rate (inst/s) +host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36128483856 # Simulator tick rate (ticks/s) +host_mem_usage 373592 # Number of bytes of host memory used +host_seconds 54.32 # Real time elapsed on the host +sim_insts 60898638 # Number of instructions simulated +sim_ops 60898638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory -system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408371 # Number of read requests accepted -system.physmem.writeReqs 162787 # Number of write requests accepted -system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25705 # Per bank write bursts -system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25737 # Per bank write bursts -system.physmem.perBankRdBursts::3 25534 # Per bank write bursts -system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24754 # Per bank write bursts -system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25489 # Per bank write bursts -system.physmem.perBankRdBursts::8 25150 # Per bank write bursts -system.physmem.perBankRdBursts::9 25518 # Per bank write bursts -system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25296 # Per bank write bursts -system.physmem.perBankRdBursts::12 25577 # Per bank write bursts -system.physmem.perBankRdBursts::13 25454 # Per bank write bursts -system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25977 # Per bank write bursts -system.physmem.perBankWrBursts::0 10598 # Per bank write bursts -system.physmem.perBankWrBursts::1 10761 # Per bank write bursts -system.physmem.perBankWrBursts::2 9727 # Per bank write bursts -system.physmem.perBankWrBursts::3 9433 # Per bank write bursts -system.physmem.perBankWrBursts::4 8910 # Per bank write bursts -system.physmem.perBankWrBursts::5 9140 # Per bank write bursts -system.physmem.perBankWrBursts::6 9908 # Per bank write bursts -system.physmem.perBankWrBursts::7 9771 # Per bank write bursts -system.physmem.perBankWrBursts::8 9710 # Per bank write bursts -system.physmem.perBankWrBursts::9 9867 # Per bank write bursts -system.physmem.perBankWrBursts::10 9923 # Per bank write bursts -system.physmem.perBankWrBursts::11 10306 # Per bank write bursts -system.physmem.perBankWrBursts::12 10733 # Per bank write bursts -system.physmem.perBankWrBursts::13 10678 # Per bank write bursts -system.physmem.perBankWrBursts::14 10553 # Per bank write bursts -system.physmem.perBankWrBursts::15 10567 # Per bank write bursts +system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406851 # Number of read requests accepted +system.physmem.writeReqs 161902 # Number of write requests accepted +system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25141 # Per bank write bursts +system.physmem.perBankRdBursts::1 25398 # Per bank write bursts +system.physmem.perBankRdBursts::2 25524 # Per bank write bursts +system.physmem.perBankRdBursts::3 24918 # Per bank write bursts +system.physmem.perBankRdBursts::4 25169 # Per bank write bursts +system.physmem.perBankRdBursts::5 25258 # Per bank write bursts +system.physmem.perBankRdBursts::6 25808 # Per bank write bursts +system.physmem.perBankRdBursts::7 25541 # Per bank write bursts +system.physmem.perBankRdBursts::8 25675 # Per bank write bursts +system.physmem.perBankRdBursts::9 25330 # Per bank write bursts +system.physmem.perBankRdBursts::10 25284 # Per bank write bursts +system.physmem.perBankRdBursts::11 25615 # Per bank write bursts +system.physmem.perBankRdBursts::12 25647 # Per bank write bursts +system.physmem.perBankRdBursts::13 25653 # Per bank write bursts +system.physmem.perBankRdBursts::14 25754 # Per bank write bursts +system.physmem.perBankRdBursts::15 25033 # Per bank write bursts +system.physmem.perBankWrBursts::0 8965 # Per bank write bursts +system.physmem.perBankWrBursts::1 8625 # Per bank write bursts +system.physmem.perBankWrBursts::2 8456 # Per bank write bursts +system.physmem.perBankWrBursts::3 7799 # Per bank write bursts +system.physmem.perBankWrBursts::4 8065 # Per bank write bursts +system.physmem.perBankWrBursts::5 8041 # Per bank write bursts +system.physmem.perBankWrBursts::6 8610 # Per bank write bursts +system.physmem.perBankWrBursts::7 8172 # Per bank write bursts +system.physmem.perBankWrBursts::8 8465 # Per bank write bursts +system.physmem.perBankWrBursts::9 8053 # Per bank write bursts +system.physmem.perBankWrBursts::10 8222 # Per bank write bursts +system.physmem.perBankWrBursts::11 8481 # Per bank write bursts +system.physmem.perBankWrBursts::12 8850 # Per bank write bursts +system.physmem.perBankWrBursts::13 9510 # Per bank write bursts +system.physmem.perBankWrBursts::14 9309 # Per bank write bursts +system.physmem.perBankWrBursts::15 8651 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962837817500 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 1962566141500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408371 # Read request sizes (log2) +system.physmem.readPktSize::6 406851 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162787 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 161902 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,185 +158,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads -system.physmem.totQLat 2189518000 # Total ticks spent queuing -system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads +system.physmem.totQLat 2137453500 # Total ticks spent queuing +system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 365775 # Number of row buffer hits during reads -system.physmem.writeRowHits 133752 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes -system.physmem.avgGap 3436593.41 # Average gap between requests -system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.687203 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing +system.physmem.readRowHits 364433 # Number of row buffer hits during reads +system.physmem.writeRowHits 110956 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes +system.physmem.avgGap 3450647.54 # Average gap between requests +system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.688732 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states +system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.737211 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states -system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.721130 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states +system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7535038 # DTB read hits -system.cpu0.dtb.read_misses 7765 # DTB read misses +system.cpu0.dtb.read_hits 7492205 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5127057 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12662095 # DTB hits -system.cpu0.dtb.data_misses 8675 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3654300 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5067323 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12559528 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_acv 344 # DTB access violations +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3501951 # ITB hits +system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3658284 # ITB accesses +system.cpu0.itb.fetch_accesses 3505822 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -349,241 +354,240 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925685712 # number of cpu cycles simulated +system.cpu0.numCycles 3923838766 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47981838 # Number of instructions committed -system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202945 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44508329 # number of integer instructions -system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12703139 # number of memory refs -system.cpu0.num_load_insts 7562835 # Number of load instructions -system.cpu0.num_store_insts 5140304 # Number of store instructions -system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7224625 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction -system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47743384 # Number of instructions committed +system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses +system.cpu0.num_func_calls 1202353 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44279734 # number of integer instructions +system.cpu0.num_fp_insts 210698 # number of float instructions +system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599731 # number of memory refs +system.cpu0.num_load_insts 7519361 # Number of load instructions +system.cpu0.num_store_insts 5080370 # Number of store instructions +system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles +system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles +system.cpu0.Branches 7198745 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction +system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47990856 # Class of executed instruction +system.cpu0.op_class::total 47751984 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed -system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149871 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149812 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190069 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits -system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses -system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.kern.swap_context 3068 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1180939 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses +system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,62 +596,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks -system.cpu0.dcache.writebacks::total 685914 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13709 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13709 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5579 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5579 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199907 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1199907 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199907 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1199907 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25214933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25214933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9773693814 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9773693814 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122568000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122568000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31544105 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31544105 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34988626814 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34988626814 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34988626814 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34988626814 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461501000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461501000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267119000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267119000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728620000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728620000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127450 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127450 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088742 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088742 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036243 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036243 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097053 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097053 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26759.661203 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26759.661203 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37936.498096 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37936.498096 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.695893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.695893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5654.078688 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5654.078688 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks +system.cpu0.dcache.writebacks::total 679102 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476948315 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476948315 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768311500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.195596 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.195596 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -655,59 +659,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 699791 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.391652 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47290432 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700302 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.528626 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391652 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits -system.cpu0.icache.overall_hits::total 47290432 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700425 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700425 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700425 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700425 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700425 # number of overall misses -system.cpu0.icache.overall_misses::total 700425 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9965953746 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9965953746 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9965953746 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9965953746 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9965953746 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9965953746 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.tags.replacements 698758 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits +system.cpu0.icache.overall_hits::total 47052596 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses +system.cpu0.icache.overall_misses::total 699388 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,51 +718,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2381610 # DTB read hits -system.cpu1.dtb.read_misses 2620 # DTB read misses +system.cpu1.dtb.read_hits 2419579 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1701782 # DTB write hits -system.cpu1.dtb.write_misses 235 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4083392 # DTB hits -system.cpu1.dtb.data_misses 2855 # DTB misses -system.cpu1.dtb.data_acv 24 # DTB access violations -system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808769 # ITB hits -system.cpu1.itb.fetch_misses 1064 # ITB misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1757217 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4176796 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.data_acv 29 # DTB access violations +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1964101 # ITB hits +system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809833 # ITB accesses +system.cpu1.itb.fetch_accesses 1965317 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -773,219 +775,220 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834021 # number of cpu cycles simulated +system.cpu1.numCycles 3925225373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12938544 # Number of instructions committed -system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411382 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11924615 # number of integer instructions -system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4106042 # number of memory refs -system.cpu1.num_load_insts 2395192 # Number of load instructions -system.cpu1.num_store_insts 1710850 # Number of store instructions -system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles -system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles -system.cpu1.Branches 1847277 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction -system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13155254 # Number of instructions committed +system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses +system.cpu1.num_func_calls 411301 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12132982 # number of integer instructions +system.cpu1.num_fp_insts 173111 # number of float instructions +system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written +system.cpu1.num_mem_refs 4200357 # number of memory refs +system.cpu1.num_load_insts 2433886 # Number of load instructions +system.cpu1.num_store_insts 1766471 # Number of store instructions +system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles +system.cpu1.Branches 1871330 # Number of branches fetched +system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction +system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12941423 # Class of executed instruction +system.cpu1.op_class::total 13158616 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed -system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71468 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 804 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71473 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 890 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 427 +system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157282 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits -system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses -system.cpu1.dcache.overall_misses::total 172235 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2467674301 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2467674301 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1998 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 166165 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits +system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses +system.cpu1.dcache.overall_misses::total 180698 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,62 +997,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks -system.cpu1.dcache.writebacks::total 107942 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172235 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172235 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks +system.cpu1.dcache.writebacks::total 114146 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1057,58 +1060,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318148 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 315648 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits -system.cpu1.icache.overall_hits::total 12622723 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses -system.cpu1.icache.overall_misses::total 318700 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits +system.cpu1.icache.overall_hits::total 12842415 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses +system.cpu1.icache.overall_misses::total 316202 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1117,30 +1121,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1156,11 +1160,11 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55631 # Transaction distribution -system.iobus.trans_dist::WriteResp 14079 # Transaction distribution +system.iobus.trans_dist::WriteReq 55604 # Transaction distribution +system.iobus.trans_dist::WriteResp 14052 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1171,12 +1175,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1187,13 +1191,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1213,52 +1217,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses -system.iocache.demand_misses::total 176 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 176 # number of overall misses -system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1267,40 +1271,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1309,189 +1313,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342765 # number of replacements -system.l2c.tags.tagsinuse 65220.427494 # Cycle average of tags in use -system.l2c.tags.total_refs 2449404 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407938 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.004354 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55273.007246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4809.132503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4932.058830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 161.965185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.263730 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073382 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 767 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7222 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25999302 # Number of tag accesses -system.l2c.tags.data_accesses 25999302 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 687538 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668153 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 318040 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 105234 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1778965 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 793856 # number of Writeback hits -system.l2c.Writeback_hits::total 793856 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 179 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 542 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 721 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129887 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42518 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172405 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 687538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 798040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 318040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 147752 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951370 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 687538 # number of overall hits -system.l2c.overall_hits::cpu0.data 798040 # number of overall hits -system.l2c.overall_hits::cpu1.inst 318040 # number of overall hits -system.l2c.overall_hits::cpu1.data 147752 # number of overall hits -system.l2c.overall_hits::total 1951370 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12866 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271551 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 659 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 293 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285369 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2958 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1782 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4740 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 895 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 917 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1812 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117982 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5781 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123763 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12866 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389533 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 659 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6074 # number of demand (read+write) misses -system.l2c.demand_misses::total 409132 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12866 # number of overall misses -system.l2c.overall_misses::cpu0.data 389533 # number of overall misses -system.l2c.overall_misses::cpu1.inst 659 # number of overall misses -system.l2c.overall_misses::cpu1.data 6074 # number of overall misses -system.l2c.overall_misses::total 409132 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 942533250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17665276500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 47722250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 21179000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18676711000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1101962 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10166561 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11268523 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 873463 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 278988 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1152451 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8137748269 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 426449979 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8564198248 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 942533250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 25803024769 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 47722250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 447628979 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 27240909248 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 942533250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 25803024769 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 47722250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 447628979 # number of overall miss cycles -system.l2c.overall_miss_latency::total 27240909248 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 700404 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 939704 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 318699 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 105527 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2064334 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 793856 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 793856 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3137 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2324 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 938 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 940 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1878 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 247869 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 48299 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296168 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 700404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1187573 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 318699 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 153826 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2360502 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 700404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1187573 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 318699 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 153826 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2360502 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.288975 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.002068 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138238 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942939 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.766781 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.867973 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.954158 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975532 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964856 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.475985 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.119692 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.417881 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018369 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.328008 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.002068 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.039486 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173324 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018369 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.328008 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.002068 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.039486 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173324 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73257.675268 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65053.255190 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72416.160850 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 72283.276451 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65447.581903 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 372.536173 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5705.140853 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2377.325527 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 975.936313 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 304.239913 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 636.010486 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68974.489914 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73767.510638 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69198.373084 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73257.675268 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 66240.921229 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72416.160850 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 73695.913566 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 66582.201461 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73257.675268 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 66240.921229 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72416.160850 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 73695.913566 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 66582.201461 # average overall miss latency +system.l2c.tags.replacements 341367 # number of replacements +system.l2c.tags.tagsinuse 65207.739778 # Cycle average of tags in use +system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 25960355 # Number of tag accesses +system.l2c.tags.data_accesses 25960355 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits +system.l2c.Writeback_hits::total 793248 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 686297 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 790979 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 315744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 155940 # number of demand (read+write) hits +system.l2c.demand_hits::total 1948960 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 686297 # number of overall hits +system.l2c.overall_hits::cpu0.data 790979 # number of overall hits +system.l2c.overall_hits::cpu1.inst 315744 # number of overall hits +system.l2c.overall_hits::cpu1.data 155940 # number of overall hits +system.l2c.overall_hits::total 1948960 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13070 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271636 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 457 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 234 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285397 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1736 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4685 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1789 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115627 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6589 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122216 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13070 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387263 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 457 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6823 # number of demand (read+write) misses +system.l2c.demand_misses::total 407613 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13070 # number of overall misses +system.l2c.overall_misses::cpu0.data 387263 # number of overall misses +system.l2c.overall_misses::cpu1.inst 457 # number of overall misses +system.l2c.overall_misses::cpu1.data 6823 # number of overall misses +system.l2c.overall_misses::total 407613 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1052716500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 19700886500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 37366250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 18492250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 20809461500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1635455 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 13268077 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 14903532 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1334957 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 185994 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1520951 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8793297261 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 540094736 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9333391997 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1052716500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 28494183761 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 37366250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 558586986 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30142853497 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1052716500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 28494183761 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 37366250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 558586986 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30142853497 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 699367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 936074 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 316201 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 108940 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2060582 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 793248 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 793248 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3132 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2260 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5392 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 928 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1849 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 242168 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 53823 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295991 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 699367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1178242 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 316201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 162763 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2356573 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 699367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1178242 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 316201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 162763 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2356573 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.290186 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001445 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002148 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138503 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941571 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768142 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.868880 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961207 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.967550 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.477466 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.122420 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.412904 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.328679 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001445 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.041920 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172969 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.328679 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001445 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.041920 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172969 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80544.491201 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 72526.787686 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81764.223195 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79026.709402 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 72914.086343 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 554.579518 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7642.901498 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3181.116756 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1496.588565 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 207.351171 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 850.168250 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.823034 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76368.004165 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 73949.686337 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 73949.686337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1500,8 +1504,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79715 # number of writebacks -system.l2c.writebacks::total 79715 # number of writebacks +system.l2c.writebacks::writebacks 78830 # number of writebacks +system.l2c.writebacks::total 78830 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits @@ -1511,111 +1515,111 @@ system.l2c.demand_mshr_hits::total 11 # nu system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12863 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271551 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 293 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285358 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2958 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1782 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4740 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 895 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 917 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1812 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 117982 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5781 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123763 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12863 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 389533 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 651 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6074 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409121 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12863 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 389533 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 651 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6074 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409121 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 778711500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14270230000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 38887000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 17526500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15105355000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29737455 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17835282 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47572737 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8983895 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9183917 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 18167812 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6655812231 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 353576521 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7009388752 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 778711500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 20926042231 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 38887000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 371103021 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22114743752 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 778711500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 20926042231 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 38887000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 371103021 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22114743752 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1369397500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 20977500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390375000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2137899500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 687012000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2824911500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3507297000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 707989500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4215286500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288975 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002777 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942939 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766781 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867973 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954158 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975532 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964856 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475985 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119692 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417881 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173319 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173319 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52550.828390 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59817.406143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52934.752136 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.230223 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.575758 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.442405 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.871508 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.176663 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10026.386313 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56413.793892 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61161.826847 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56635.575673 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13067 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271636 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 449 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 234 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285386 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1736 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4685 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1789 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115627 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6589 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122216 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13067 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387263 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 449 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6823 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407602 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13067 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387263 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15769892 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15706897 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 31476789 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347142739 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457723764 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7804866503 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 888765750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 23652210239 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 31138500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 473285514 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25045400003 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 888765750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 23652210239 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961207 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967550 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122420 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412904 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172964 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1626,96 +1630,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292731 # Transaction distribution -system.membus.trans_dist::ReadResp 292731 # Transaction distribution -system.membus.trans_dist::WriteReq 14079 # Transaction distribution -system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121235 # Transaction distribution +system.membus.trans_dist::ReadReq 292759 # Transaction distribution +system.membus.trans_dist::ReadResp 292759 # Transaction distribution +system.membus.trans_dist::WriteReq 14052 # Transaction distribution +system.membus.trans_dist::WriteResp 14052 # Transaction distribution +system.membus.trans_dist::Writeback 120350 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution -system.membus.trans_dist::ReadExReq 124107 # Transaction distribution -system.membus.trans_dist::ReadExResp 123261 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution +system.membus.trans_dist::ReadExReq 122543 # Transaction distribution +system.membus.trans_dist::ReadExResp 121713 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22119 # Total snoops (count) -system.membus.snoop_fanout::samples 600328 # Request fanout histogram +system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21558 # Total snoops (count) +system.membus.snoop_fanout::samples 597341 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600328 # Request fanout histogram -system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 597341 # Request fanout histogram +system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99473 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 98552 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5c3a9c7d0..d63246d54 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920419 # Number of seconds simulated -sim_ticks 1920418772000 # Number of ticks simulated -final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922414 # Number of seconds simulated +sim_ticks 1922413663500 # Number of ticks simulated +final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235696 # Simulator instruction rate (inst/s) -host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42298287542 # Simulator tick rate (ticks/s) -host_mem_usage 370580 # Number of bytes of host memory used -host_seconds 45.40 # Real time elapsed on the host -sim_insts 56102800 # Number of instructions simulated -sim_ops 56102800 # Number of ops (including micro ops) simulated +host_inst_rate 1122927 # Simulator instruction rate (inst/s) +host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38428929684 # Simulator tick rate (ticks/s) +host_mem_usage 370248 # Number of bytes of host memory used +host_seconds 50.03 # Real time elapsed on the host +sim_insts 56174594 # Number of instructions simulated +sim_ops 56174594 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory -system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401711 # Number of read requests accepted -system.physmem.writeReqs 157234 # Number of write requests accepted -system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue -system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401737 # Number of read requests accepted +system.physmem.writeReqs 157245 # Number of write requests accepted +system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25160 # Per bank write bursts -system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::0 25230 # Per bank write bursts +system.physmem.perBankRdBursts::1 25660 # Per bank write bursts +system.physmem.perBankRdBursts::2 25603 # Per bank write bursts system.physmem.perBankRdBursts::3 25523 # Per bank write bursts -system.physmem.perBankRdBursts::4 24974 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24210 # Per bank write bursts -system.physmem.perBankRdBursts::7 24487 # Per bank write bursts -system.physmem.perBankRdBursts::8 25140 # Per bank write bursts -system.physmem.perBankRdBursts::9 24800 # Per bank write bursts -system.physmem.perBankRdBursts::10 25360 # Per bank write bursts -system.physmem.perBankRdBursts::11 24834 # Per bank write bursts -system.physmem.perBankRdBursts::12 24395 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts -system.physmem.perBankRdBursts::14 25772 # Per bank write bursts -system.physmem.perBankRdBursts::15 25477 # Per bank write bursts -system.physmem.perBankWrBursts::0 10048 # Per bank write bursts -system.physmem.perBankWrBursts::1 9910 # Per bank write bursts -system.physmem.perBankWrBursts::2 10442 # Per bank write bursts -system.physmem.perBankWrBursts::3 9959 # Per bank write bursts -system.physmem.perBankWrBursts::4 9552 # Per bank write bursts -system.physmem.perBankWrBursts::5 9342 # Per bank write bursts -system.physmem.perBankWrBursts::6 8789 # Per bank write bursts -system.physmem.perBankWrBursts::7 8561 # Per bank write bursts -system.physmem.perBankWrBursts::8 9905 # Per bank write bursts -system.physmem.perBankWrBursts::9 8742 # Per bank write bursts -system.physmem.perBankWrBursts::10 9526 # Per bank write bursts -system.physmem.perBankWrBursts::11 9262 # Per bank write bursts -system.physmem.perBankWrBursts::12 9811 # Per bank write bursts -system.physmem.perBankWrBursts::13 10568 # Per bank write bursts -system.physmem.perBankWrBursts::14 10305 # Per bank write bursts -system.physmem.perBankWrBursts::15 10316 # Per bank write bursts +system.physmem.perBankRdBursts::4 24970 # Per bank write bursts +system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::6 24206 # Per bank write bursts +system.physmem.perBankRdBursts::7 24492 # Per bank write bursts +system.physmem.perBankRdBursts::8 25173 # Per bank write bursts +system.physmem.perBankRdBursts::9 24777 # Per bank write bursts +system.physmem.perBankRdBursts::10 25267 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24505 # Per bank write bursts +system.physmem.perBankRdBursts::13 25378 # Per bank write bursts +system.physmem.perBankRdBursts::14 25651 # Per bank write bursts +system.physmem.perBankRdBursts::15 25357 # Per bank write bursts +system.physmem.perBankWrBursts::0 8677 # Per bank write bursts +system.physmem.perBankWrBursts::1 8490 # Per bank write bursts +system.physmem.perBankWrBursts::2 8972 # Per bank write bursts +system.physmem.perBankWrBursts::3 8549 # Per bank write bursts +system.physmem.perBankWrBursts::4 8030 # Per bank write bursts +system.physmem.perBankWrBursts::5 7962 # Per bank write bursts +system.physmem.perBankWrBursts::6 7256 # Per bank write bursts +system.physmem.perBankWrBursts::7 7133 # Per bank write bursts +system.physmem.perBankWrBursts::8 8241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7447 # Per bank write bursts +system.physmem.perBankWrBursts::10 7887 # Per bank write bursts +system.physmem.perBankWrBursts::11 7738 # Per bank write bursts +system.physmem.perBankWrBursts::12 8187 # Per bank write bursts +system.physmem.perBankWrBursts::13 8962 # Per bank write bursts +system.physmem.perBankWrBursts::14 8876 # Per bank write bursts +system.physmem.perBankWrBursts::15 8644 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1920406851000 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 1922401791500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401711 # Read request sizes (log2) +system.physmem.readPktSize::6 401737 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157234 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,184 +148,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads -system.physmem.totQLat 2115529750 # Total ticks spent queuing -system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads +system.physmem.totQLat 2057087750 # Total ticks spent queuing +system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing -system.physmem.readRowHits 359951 # Number of row buffer hits during reads -system.physmem.writeRowHits 130246 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes -system.physmem.avgGap 3435770.69 # Average gap between requests -system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.686102 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states -system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing +system.physmem.readRowHits 360176 # Number of row buffer hits during reads +system.physmem.writeRowHits 107764 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes +system.physmem.avgGap 3439112.16 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.677845 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states +system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730762 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states -system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.732006 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states +system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052701 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9063642 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6349364 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6355525 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15402065 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15419167 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973977 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974414 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978974 # ITB accesses +system.cpu.itb.fetch_accesses 4979424 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,87 +343,87 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840837544 # number of cpu cycles simulated +system.cpu.numCycles 3844827327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102800 # Number of instructions committed -system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1481300 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls -system.cpu.num_int_insts 51978055 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15454652 # number of memory refs -system.cpu.num_load_insts 9089529 # Number of load instructions -system.cpu.num_store_insts 6365123 # Number of store instructions -system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934485 # Percentage of idle cycles -system.cpu.Branches 8412940 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction +system.cpu.committedInsts 56174594 # Number of instructions committed +system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483106 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls +system.cpu.num_int_insts 52047018 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read +system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15471782 # number of memory refs +system.cpu.num_load_insts 9100493 # Number of load instructions +system.cpu.num_store_insts 6371289 # Number of store instructions +system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles +system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles +system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933046 # Percentage of idle cycles +system.cpu.Branches 8421188 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56114619 # Class of executed instruction +system.cpu.op_class::total 56186427 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -454,10 +459,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -466,101 +471,101 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192900 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.callpal::total 192894 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1389979 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1391374 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits -system.cpu.dcache.overall_hits::total 13648338 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses -system.cpu.dcache.overall_misses::total 1373292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits +system.cpu.dcache.overall_hits::total 13664105 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses +system.cpu.dcache.overall_misses::total 1374617 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42596747630 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42596747630 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42596747630 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8882773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8882773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6155949 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6155949 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15038722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15038722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15038722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15038722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120486 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086325 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086325 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -569,54 +574,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks -system.cpu.dcache.writebacks::total 834368 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304189 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17217 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17217 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373292 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373292 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373292 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373292 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26736955500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26736955500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245884370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091421 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091421 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25008.774178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25008.774178 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33682.626163 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33682.626163 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11252.366847 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11252.366847 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks +system.cpu.dcache.writebacks::total 835634 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091405 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -624,59 +629,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 927664 # number of replacements -system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928205 # number of replacements +system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992326 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992326 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57042955 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57042955 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55186285 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55186285 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55186285 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55186285 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55186285 # number of overall hits -system.cpu.icache.overall_hits::total 55186285 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928335 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928335 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928335 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928335 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928335 # number of overall misses -system.cpu.icache.overall_misses::total 928335 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909899750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12909899750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12909899750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12909899750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12909899750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12909899750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56114620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56114620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56114620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56114620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56114620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56114620 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016544 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016544 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016544 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016544 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016544 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016544 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13906.509773 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13906.509773 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13906.509773 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13906.509773 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57115304 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57115304 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55257552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55257552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55257552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55257552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55257552 # number of overall hits +system.cpu.icache.overall_hits::total 55257552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928876 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928876 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928876 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928876 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928876 # number of overall misses +system.cpu.icache.overall_misses::total 928876 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13004894000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13004894000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13004894000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13004894000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13004894000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13004894000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56186428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56186428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56186428 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56186428 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56186428 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56186428 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14000.678239 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14000.678239 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14000.678239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14000.678239 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,135 +690,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928335 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928335 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928335 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928335 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928335 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928335 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048066250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11048066250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048066250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11048066250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048066250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11048066250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016544 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016544 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016544 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.947664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.947664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928876 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928876 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928876 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928876 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928876 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928876 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11606411000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11606411000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11606411000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11606411000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11606411000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11606411000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12495.113449 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12495.113449 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336225 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65295.018505 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2445535 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401387 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.092711 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55550.770505 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4768.438466 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.809535 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847637 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996323 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 336253 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65287.674931 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2448546 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401415 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.099787 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 7245222750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4753.205077 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5018.688389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.847104 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072528 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.076579 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996211 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3256 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4937 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3234 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55805 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25931322 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25931322 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 915025 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814362 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729387 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834368 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834368 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 25957144 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25957144 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 915565 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 815571 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1731136 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 835634 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835634 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187334 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187334 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915025 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001696 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1916721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 915025 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001696 # number of overall hits -system.cpu.l2cache.overall_hits::total 1916721 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271958 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285248 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187495 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187495 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915565 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1003066 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918631 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915565 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1003066 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918631 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271964 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116838 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116838 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388796 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402086 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388796 # number of overall misses -system.cpu.l2cache.overall_misses::total 402086 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 969461250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17700747500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18670208750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8067922881 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8067922881 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 969461250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 25768670381 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26738131631 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 969461250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 25768670381 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26738131631 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 928315 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086320 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2014635 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 834368 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834368 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116857 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116857 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388821 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 402112 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388821 # number of overall misses +system.cpu.l2cache.overall_misses::total 402112 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1064072500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19718835000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20782907500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220998 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 220998 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8916531881 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8916531881 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1064072500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28635366881 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29699439381 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1064072500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28635366881 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29699439381 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 928856 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1087535 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2016391 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 835634 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835634 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928315 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390492 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318807 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928315 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390492 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318807 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250348 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141588 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304352 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304352 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391887 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320743 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391887 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320743 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250074 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141468 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384118 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384118 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279610 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173402 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279610 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173402 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72946.670429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65086.327668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65452.549185 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69052.216582 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69052.216582 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66498.539196 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66498.539196 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383953 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383953 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014309 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279348 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173269 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014309 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279348 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173269 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80059.626815 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72505.313203 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72857.294351 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16999.846154 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16999.846154 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76302.933337 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76302.933337 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73858.624913 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73858.624913 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,66 +827,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74170 # number of writebacks -system.cpu.l2cache.writebacks::total 74170 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285248 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks +system.cpu.l2cache.writebacks::total 74181 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271964 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116838 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116838 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388796 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402086 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388796 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402086 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802917750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14300848500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103766250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -889,41 +894,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41901 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41937 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -996,23 +1001,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1026,14 +1031,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1050,19 +1055,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1076,14 +1081,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1092,57 +1097,57 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292351 # Transaction distribution -system.membus.trans_dist::ReadResp 292351 # Transaction distribution +system.membus.trans_dist::ReadReq 292358 # Transaction distribution +system.membus.trans_dist::ReadResp 292358 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115682 # Transaction distribution +system.membus.trans_dist::Writeback 115693 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116719 # Transaction distribution -system.membus.trans_dist::ReadExResp 116719 # Transaction distribution +system.membus.trans_dist::ReadExReq 116738 # Transaction distribution +system.membus.trans_dist::ReadExResp 116738 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559506 # Request fanout histogram +system.membus.snoop_fanout::samples 559589 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559506 # Request fanout histogram -system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 559589 # Request fanout histogram +system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index def60114c..cb5fe02ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802895 # Number of seconds simulated -sim_ticks 2802895103500 # Number of ticks simulated -final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802894699500 # Number of ticks simulated +final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834307 # Simulator instruction rate (inst/s) -host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15926512431 # Simulator tick rate (ticks/s) -host_mem_usage 572876 # Number of bytes of host memory used -host_seconds 175.99 # Real time elapsed on the host -sim_insts 146829031 # Number of instructions simulated -sim_ops 178908942 # Number of ops (including micro ops) simulated +host_inst_rate 1337323 # Simulator instruction rate (inst/s) +host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25528979782 # Simulator tick rate (ticks/s) +host_mem_usage 626168 # Number of bytes of host memory used +host_seconds 109.79 # Real time elapsed on the host +sim_insts 146828240 # Number of instructions simulated +sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory +system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory +system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -142,9 +142,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339962 # DTB read hits +system.cpu0.dtb.read_hits 20339720 # DTB read hits system.cpu0.dtb.read_misses 6874 # DTB read misses -system.cpu0.dtb.write_hits 16391171 # DTB write hits +system.cpu0.dtb.write_hits 16391078 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -155,12 +155,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346836 # DTB read accesses -system.cpu0.dtb.write_accesses 16392264 # DTB write accesses +system.cpu0.dtb.read_accesses 20346594 # DTB read accesses +system.cpu0.dtb.write_accesses 16392171 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36731133 # DTB hits +system.cpu0.dtb.hits 36730798 # DTB hits system.cpu0.dtb.misses 7967 # DTB misses -system.cpu0.dtb.accesses 36739100 # DTB accesses +system.cpu0.dtb.accesses 36738765 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -208,7 +208,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97440315 # ITB inst hits +system.cpu0.itb.inst_hits 97439331 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -225,37 +225,37 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses -system.cpu0.itb.hits 97440315 # DTB hits +system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses +system.cpu0.itb.hits 97439331 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97443673 # DTB accesses -system.cpu0.numCycles 5605792176 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442689 # DTB accesses +system.cpu0.numCycles 5605791368 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95427853 # Number of instructions committed -system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses +system.cpu0.committedInsts 95426926 # Number of instructions committed +system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000324 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100763618 # number of integer instructions +system.cpu0.num_func_calls 8000180 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762696 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written -system.cpu0.num_mem_refs 37874145 # number of memory refs -system.cpu0.num_load_insts 20597552 # Number of load instructions -system.cpu0.num_store_insts 17276593 # Number of store instructions -system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles -system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles +system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873810 # number of memory refs +system.cpu0.num_load_insts 20597310 # Number of load instructions +system.cpu0.num_store_insts 17276500 # Number of store instructions +system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles +system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941792 # Number of branches fetched +system.cpu0.Branches 21941499 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction @@ -284,20 +284,20 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116883193 # Class of executed instruction +system.cpu0.op_class::total 116882065 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 693476 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 693477 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -305,50 +305,50 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 74113775 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113775 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108539 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108539 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690376 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690376 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363049 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363049 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798915 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798915 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145008 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145008 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373099 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373099 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295764 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295764 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18436 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18436 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses system.cpu0.dcache.overall_misses::total 769184 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481638 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481638 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986140 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986140 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 35467778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467778 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses @@ -357,8 +357,8 @@ system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048327 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048327 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses @@ -371,14 +371,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks -system.cpu0.dcache.writebacks::total 511648 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511896 # number of writebacks +system.cpu0.dcache.writebacks::total 511896 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1109742 # number of replacements +system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -388,26 +388,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits -system.cpu0.icache.overall_hits::total 96332394 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses -system.cpu0.icache.overall_misses::total 1110263 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits +system.cpu0.icache.overall_hits::total 96331417 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses +system.cpu0.icache.overall_misses::total 1110256 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses @@ -429,123 +429,123 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252403 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 252330 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16129.294754 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1810154 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268529 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.741000 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.492437 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984453 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 8067.926153 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.192846 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.094111 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.670375 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.411269 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.492427 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289836 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201990 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984454 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5587 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7674 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2571 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5555 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7641 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2632 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39450391 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39450391 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7605 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3248 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065251 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 352125 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428229 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511648 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511648 # number of Writeback hits +system.cpu0.l2cache.tags.tag_accesses 39452382 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39452382 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7540 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3225 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065497 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351995 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428257 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511896 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511896 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94130 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94130 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7605 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3248 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065251 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446255 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522359 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7605 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3248 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065251 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446255 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522359 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 134 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 45012 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303423 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348794 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 134 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 45012 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303423 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348794 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94089 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94089 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7540 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3225 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065497 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446084 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522346 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7540 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3225 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065497 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446084 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522346 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 210 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44759 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128167 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173260 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26230 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26230 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18436 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18436 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 210 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44759 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303595 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348688 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 210 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44759 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303595 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348688 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7750 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3349 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480162 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601517 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511896 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511896 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26247 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26247 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18436 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18436 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7750 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3349 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749679 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871034 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7750 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3349 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749679 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1871034 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037026 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040314 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266924 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108185 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650898 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650898 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037026 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040314 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404967 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037026 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040314 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404967 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,45 +554,43 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks -system.cpu0.l2cache.writebacks::total 192841 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks +system.cpu0.l2cache.writebacks::total 192974 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 322042 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322019 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -642,9 +640,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173884 # DTB read hits +system.cpu1.dtb.read_hits 12173916 # DTB read hits system.cpu1.dtb.read_misses 2852 # DTB read misses -system.cpu1.dtb.write_hits 7587193 # DTB write hits +system.cpu1.dtb.write_hits 7587209 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -655,12 +653,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176736 # DTB read accesses -system.cpu1.dtb.write_accesses 7587699 # DTB write accesses +system.cpu1.dtb.read_accesses 12176768 # DTB read accesses +system.cpu1.dtb.write_accesses 7587715 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761077 # DTB hits +system.cpu1.dtb.hits 19761125 # DTB hits system.cpu1.dtb.misses 3358 # DTB misses -system.cpu1.dtb.accesses 19764435 # DTB accesses +system.cpu1.dtb.accesses 19764483 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -708,7 +706,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671431 # ITB inst hits +system.cpu1.itb.inst_hits 53671575 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -725,37 +723,37 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses -system.cpu1.itb.hits 53671431 # DTB hits +system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses +system.cpu1.itb.hits 53671575 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673165 # DTB accesses -system.cpu1.numCycles 5605321082 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673309 # DTB accesses +system.cpu1.numCycles 5605320274 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51401178 # Number of instructions committed -system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses +system.cpu1.committedInsts 51401314 # Number of instructions committed +system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170823 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984089 # number of integer instructions +system.cpu1.num_func_calls 9170855 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984241 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026333 # number of memory refs -system.cpu1.num_load_insts 12289505 # Number of load instructions -system.cpu1.num_store_insts 7736828 # Number of store instructions -system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles -system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026381 # number of memory refs +system.cpu1.num_load_insts 12289537 # Number of load instructions +system.cpu1.num_store_insts 7736844 # Number of store instructions +system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles +system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217445 # Number of branches fetched +system.cpu1.Branches 15217493 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction @@ -784,70 +782,70 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459288 # Class of executed instruction +system.cpu1.op_class::total 65459464 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 191938 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256188 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256188 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306287 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses -system.cpu1.dcache.overall_misses::total 259820 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22519 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229098 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses +system.cpu1.dcache.overall_misses::total 259817 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses @@ -856,10 +854,10 @@ system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -870,42 +868,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks -system.cpu1.dcache.writebacks::total 120709 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks +system.cpu1.dcache.writebacks::total 120855 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits -system.cpu1.icache.overall_hits::total 53148636 # number of overall hits +system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits +system.cpu1.icache.overall_hits::total 53148780 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses system.cpu1.icache.overall_misses::total 523885 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -927,88 +925,88 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48598 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48604 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.430451 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200133 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225368 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934163 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14807 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1735 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510036 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99375 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614297 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1735 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510036 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119159 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634081 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3151 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1735 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634081 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 261 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 261 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 261 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120855 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28852 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28852 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22519 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22519 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses @@ -1021,27 +1019,27 @@ system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.130762 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026435 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424470 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.124979 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689009 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689009 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.130762 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026435 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495694 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171843 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.130762 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026435 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171843 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1050,51 +1048,49 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks -system.cpu1.l2cache.writebacks::total 32919 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32977 # number of writebacks +system.cpu1.l2cache.writebacks::total 32977 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707623 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22876014 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499587 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499492 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram -system.iobus.trans_dist::ReadReq 31002 # Transaction distribution -system.iobus.trans_dist::ReadResp 31002 # Transaction distribution -system.iobus.trans_dist::WriteReq 59433 # Transaction distribution -system.iobus.trans_dist::WriteResp 23209 # Transaction distribution +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram +system.iobus.trans_dist::ReadReq 30995 # Transaction distribution +system.iobus.trans_dist::ReadResp 30995 # Transaction distribution +system.iobus.trans_dist::WriteReq 59419 # Transaction distribution +system.iobus.trans_dist::WriteResp 23195 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1115,11 +1111,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1140,10 +1136,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1193,21 +1189,21 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107620 # number of replacements -system.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use -system.l2c.tags.total_refs 207975 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks. +system.l2c.tags.replacements 107683 # number of replacements +system.l2c.tags.tagsinuse 62052.473518 # Cycle average of tags in use +system.l2c.tags.total_refs 207875 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168125 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.236431 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48595.677496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972785 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7329.722723 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3756.747244 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 1654.505866 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 710.993782 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.741511 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy @@ -1215,161 +1211,161 @@ system.l2c.tags.occ_percent::cpu0.data 0.057323 # Av system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.946844 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1918 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45390 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921509 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4903951 # Number of tag accesses -system.l2c.tags.data_accesses 4903951 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 85 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 75 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28112 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 75977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 41 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11436 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11429 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127191 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 225760 # number of Writeback hits -system.l2c.Writeback_hits::total 225760 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 516 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 573 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17017 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 85 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28112 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89895 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11436 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14528 # number of demand (read+write) hits -system.l2c.demand_hits::total 144208 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 85 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28112 # number of overall hits -system.l2c.overall_hits::cpu0.data 89895 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11436 # number of overall hits -system.l2c.overall_hits::cpu1.data 14528 # number of overall hits -system.l2c.overall_hits::total 144208 # number of overall hits +system.l2c.tags.occ_percent::total 0.946846 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60435 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1875 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13095 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.922165 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4904261 # Number of tag accesses +system.l2c.tags.data_accesses 4904261 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 71 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 27858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 76068 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 39 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 20 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11484 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11410 # number of ReadReq hits +system.l2c.ReadReq_hits::total 127013 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 225951 # number of Writeback hits +system.l2c.Writeback_hits::total 225951 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 487 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 552 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 64 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13938 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3112 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17050 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 27858 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90006 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11484 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14522 # number of demand (read+write) hits +system.l2c.demand_hits::total 144063 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu0.inst 27858 # number of overall hits +system.l2c.overall_hits::cpu0.data 90006 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11484 # number of overall hits +system.l2c.overall_hits::cpu1.data 14522 # number of overall hits +system.l2c.overall_hits::total 144063 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16900 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11311 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16901 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 11313 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2371 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1120 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31713 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9991 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3299 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13290 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 771 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1177 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1948 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152622 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 2365 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1118 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31708 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 10019 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3288 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13307 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 752 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1179 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136795 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152617 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16900 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 148107 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16901 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 148108 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16946 # number of demand (read+write) misses -system.l2c.demand_misses::total 184335 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2365 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16940 # number of demand (read+write) misses +system.l2c.demand_misses::total 184325 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16900 # number of overall misses -system.l2c.overall_misses::cpu0.data 148107 # number of overall misses +system.l2c.overall_misses::cpu0.inst 16901 # number of overall misses +system.l2c.overall_misses::cpu0.data 148108 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses -system.l2c.overall_misses::cpu1.data 16946 # number of overall misses -system.l2c.overall_misses::total 184335 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 92 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 77 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 45012 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 87288 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13807 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12549 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 158904 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 225760 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225760 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10507 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3356 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 823 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2009 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18925 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169639 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 45012 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238002 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13807 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31474 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328543 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 45012 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238002 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13807 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31474 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328543 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.129583 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.171724 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.089250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.199573 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950890 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.983015 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958667 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.936817 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992411 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969637 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907653 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.836248 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899687 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.622293 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.171724 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.538413 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.561068 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses +system.l2c.overall_misses::cpu1.inst 2365 # number of overall misses +system.l2c.overall_misses::cpu1.data 16940 # number of overall misses +system.l2c.overall_misses::total 184325 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 78 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 44759 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 87381 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 41 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 20 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13849 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 158721 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225951 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225951 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10506 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3353 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13859 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 816 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1189 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150733 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18934 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169667 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 78 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238114 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13849 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31462 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328388 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 78 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238114 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13849 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31462 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328388 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.377600 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129468 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170770 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089240 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199772 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953646 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980614 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.960170 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921569 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.991590 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.963092 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907532 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.835640 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899509 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.377600 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622005 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170770 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.538427 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.561302 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.377600 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622005 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170770 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.538427 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.561302 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1378,49 +1374,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94860 # number of writebacks -system.l2c.writebacks::total 94860 # number of writebacks +system.l2c.writebacks::writebacks 94914 # number of writebacks +system.l2c.writebacks::total 94914 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 75978 # Transaction distribution -system.membus.trans_dist::ReadResp 75978 # Transaction distribution -system.membus.trans_dist::WriteReq 30905 # Transaction distribution -system.membus.trans_dist::WriteResp 30905 # Transaction distribution -system.membus.trans_dist::Writeback 131050 # Transaction distribution +system.membus.trans_dist::ReadReq 75966 # Transaction distribution +system.membus.trans_dist::ReadResp 75966 # Transaction distribution +system.membus.trans_dist::WriteReq 30891 # Transaction distribution +system.membus.trans_dist::WriteResp 30891 # Transaction distribution +system.membus.trans_dist::Writeback 131104 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution -system.membus.trans_dist::ReadExReq 196304 # Transaction distribution -system.membus.trans_dist::ReadExResp 152218 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution +system.membus.trans_dist::ReadExReq 196339 # Transaction distribution +system.membus.trans_dist::ReadExResp 152220 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 496844 # Request fanout histogram +system.membus.snoop_fanout::samples 496901 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 496844 # Request fanout histogram +system.membus.snoop_fanout::total 496901 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1452,33 +1448,33 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index fb9bec115..20c993e31 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867165000 # Number of ticks simulated -final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783867052000 # Number of ticks simulated +final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1374338 # Simulator instruction rate (inst/s) -host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26797569978 # Simulator tick rate (ticks/s) -host_mem_usage 615488 # Number of bytes of host memory used -host_seconds 103.89 # Real time elapsed on the host -sim_insts 142773109 # Number of instructions simulated -sim_ops 173803334 # Number of ops (including micro ops) simulated +host_inst_rate 1378466 # Simulator instruction rate (inst/s) +host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26878113924 # Simulator tick rate (ticks/s) +host_mem_usage 614624 # Number of bytes of host memory used +host_seconds 103.57 # Real time elapsed on the host +sim_insts 142772879 # Number of instructions simulated +sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory +system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory +system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526301 # DTB read hits +system.cpu.dtb.read_hits 31526223 # DTB read hits system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124463 # DTB write hits +system.cpu.dtb.write_hits 23124452 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534882 # DTB read accesses -system.cpu.dtb.write_accesses 23125911 # DTB write accesses +system.cpu.dtb.read_accesses 31534804 # DTB read accesses +system.cpu.dtb.write_accesses 23125900 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650764 # DTB hits +system.cpu.dtb.hits 54650675 # DTB hits system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660793 # DTB accesses +system.cpu.dtb.accesses 54660704 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039592 # ITB inst hits +system.cpu.itb.inst_hits 147039346 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,37 +202,37 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044354 # ITB inst accesses -system.cpu.itb.hits 147039592 # DTB hits +system.cpu.itb.inst_accesses 147044108 # ITB inst accesses +system.cpu.itb.hits 147039346 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044354 # DTB accesses -system.cpu.numCycles 5567737414 # number of cpu cycles simulated +system.cpu.itb.accesses 147044108 # DTB accesses +system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142773109 # Number of instructions committed -system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses +system.cpu.committedInsts 142772879 # Number of instructions committed +system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873879 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162826 # number of integer instructions +system.cpu.num_func_calls 16873899 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls +system.cpu.num_int_insts 153162683 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written +system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read +system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written -system.cpu.num_mem_refs 55939365 # number of memory refs -system.cpu.num_load_insts 31855962 # Number of load instructions -system.cpu.num_store_insts 24083403 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles -system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles +system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written +system.cpu.num_mem_refs 55939276 # number of memory refs +system.cpu.num_load_insts 31855884 # Number of load instructions +system.cpu.num_store_insts 24083392 # Number of store instructions +system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles +system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36397028 # Number of branches fetched +system.cpu.Branches 36396981 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction @@ -261,18 +261,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177220138 # Class of executed instruction +system.cpu.op_class::total 177219912 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 819403 # number of replacements +system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,24 +282,24 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits -system.cpu.dcache.overall_hits::total 52864309 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits +system.cpu.dcache.overall_hits::total 52864242 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses @@ -308,24 +308,24 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses -system.cpu.dcache.overall_misses::total 814075 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses +system.cpu.dcache.overall_misses::total 814074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses @@ -348,14 +348,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks -system.cpu.dcache.writebacks::total 682060 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks +system.cpu.dcache.writebacks::total 682059 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699220 # number of replacements +system.cpu.icache.tags.replacements 1699214 # number of replacements system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -366,26 +366,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits -system.cpu.icache.overall_hits::total 145342961 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses -system.cpu.icache.overall_misses::total 1699738 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits +system.cpu.icache.overall_hits::total 145342721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses +system.cpu.icache.overall_misses::total 1699732 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses @@ -401,17 +401,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 110026 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -428,34 +428,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses @@ -464,21 +464,21 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses -system.cpu.l2cache.overall_misses::total 181765 # number of overall misses +system.cpu.l2cache.overall_misses::total 181764 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -487,19 +487,19 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses @@ -508,12 +508,12 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -524,51 +524,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks -system.cpu.l2cache.writebacks::total 101898 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks +system.cpu.l2cache.writebacks::total 101897 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram +system.iobus.trans_dist::ReadReq 30164 # Transaction distribution +system.iobus.trans_dist::ReadResp 30164 # Transaction distribution +system.iobus.trans_dist::WriteReq 59002 # Transaction distribution +system.iobus.trans_dist::WriteResp 22778 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -589,11 +587,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -614,17 +612,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -667,11 +665,11 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74235 # Transaction distribution -system.membus.trans_dist::ReadResp 74235 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 138088 # Transaction distribution +system.membus.trans_dist::ReadReq 74227 # Transaction distribution +system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::WriteReq 27546 # Transaction distribution +system.membus.trans_dist::WriteResp 27546 # Transaction distribution +system.membus.trans_dist::Writeback 138087 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -679,34 +677,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359047 # Request fanout histogram +system.membus.snoop_fanout::samples 359045 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359047 # Request fanout histogram +system.membus.snoop_fanout::total 359045 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 391769400..64a01b6e7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,160 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868319 # Number of seconds simulated -sim_ticks 2868318696500 # Number of ticks simulated -final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868581 # Number of seconds simulated +sim_ticks 2868581440500 # Number of ticks simulated +final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 534652 # Simulator instruction rate (inst/s) -host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11631340017 # Simulator tick rate (ticks/s) -host_mem_usage 586476 # Number of bytes of host memory used -host_seconds 246.60 # Real time elapsed on the host -sim_insts 131846562 # Number of instructions simulated -sim_ops 159471778 # Number of ops (including micro ops) simulated +host_inst_rate 717360 # Simulator instruction rate (inst/s) +host_op_rate 867708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15647358559 # Simulator tick rate (ticks/s) +host_mem_usage 639748 # Number of bytes of host memory used +host_seconds 183.33 # Real time elapsed on the host +sim_insts 131511324 # Number of instructions simulated +sim_ops 159074269 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory +system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory +system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200214 # Number of read requests accepted -system.physmem.writeReqs 175885 # Number of write requests accepted -system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12188 # Per bank write bursts -system.physmem.perBankRdBursts::1 12046 # Per bank write bursts -system.physmem.perBankRdBursts::2 12591 # Per bank write bursts -system.physmem.perBankRdBursts::3 12330 # Per bank write bursts -system.physmem.perBankRdBursts::4 20750 # Per bank write bursts -system.physmem.perBankRdBursts::5 12582 # Per bank write bursts -system.physmem.perBankRdBursts::6 12043 # Per bank write bursts -system.physmem.perBankRdBursts::7 12246 # Per bank write bursts -system.physmem.perBankRdBursts::8 12442 # Per bank write bursts -system.physmem.perBankRdBursts::9 12402 # Per bank write bursts -system.physmem.perBankRdBursts::10 11722 # Per bank write bursts -system.physmem.perBankRdBursts::11 11146 # Per bank write bursts -system.physmem.perBankRdBursts::12 11467 # Per bank write bursts -system.physmem.perBankRdBursts::13 11916 # Per bank write bursts -system.physmem.perBankRdBursts::14 10852 # Per bank write bursts -system.physmem.perBankRdBursts::15 11341 # Per bank write bursts -system.physmem.perBankWrBursts::0 10835 # Per bank write bursts -system.physmem.perBankWrBursts::1 11264 # Per bank write bursts -system.physmem.perBankWrBursts::2 11493 # Per bank write bursts -system.physmem.perBankWrBursts::3 10899 # Per bank write bursts -system.physmem.perBankWrBursts::4 10487 # Per bank write bursts -system.physmem.perBankWrBursts::5 11152 # Per bank write bursts -system.physmem.perBankWrBursts::6 11024 # Per bank write bursts -system.physmem.perBankWrBursts::7 10595 # Per bank write bursts -system.physmem.perBankWrBursts::8 10782 # Per bank write bursts -system.physmem.perBankWrBursts::9 10958 # Per bank write bursts -system.physmem.perBankWrBursts::10 10716 # Per bank write bursts -system.physmem.perBankWrBursts::11 10408 # Per bank write bursts -system.physmem.perBankWrBursts::12 10444 # Per bank write bursts -system.physmem.perBankWrBursts::13 9906 # Per bank write bursts -system.physmem.perBankWrBursts::14 9416 # Per bank write bursts -system.physmem.perBankWrBursts::15 9817 # Per bank write bursts +system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 191448 # Number of read requests accepted +system.physmem.writeReqs 168916 # Number of write requests accepted +system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11402 # Per bank write bursts +system.physmem.perBankRdBursts::1 11523 # Per bank write bursts +system.physmem.perBankRdBursts::2 11617 # Per bank write bursts +system.physmem.perBankRdBursts::3 11771 # Per bank write bursts +system.physmem.perBankRdBursts::4 20348 # Per bank write bursts +system.physmem.perBankRdBursts::5 12097 # Per bank write bursts +system.physmem.perBankRdBursts::6 11123 # Per bank write bursts +system.physmem.perBankRdBursts::7 11241 # Per bank write bursts +system.physmem.perBankRdBursts::8 11419 # Per bank write bursts +system.physmem.perBankRdBursts::9 11532 # Per bank write bursts +system.physmem.perBankRdBursts::10 11480 # Per bank write bursts +system.physmem.perBankRdBursts::11 10715 # Per bank write bursts +system.physmem.perBankRdBursts::12 11252 # Per bank write bursts +system.physmem.perBankRdBursts::13 11225 # Per bank write bursts +system.physmem.perBankRdBursts::14 11052 # Per bank write bursts +system.physmem.perBankRdBursts::15 11518 # Per bank write bursts +system.physmem.perBankWrBursts::0 9249 # Per bank write bursts +system.physmem.perBankWrBursts::1 9496 # Per bank write bursts +system.physmem.perBankWrBursts::2 9535 # Per bank write bursts +system.physmem.perBankWrBursts::3 9435 # Per bank write bursts +system.physmem.perBankWrBursts::4 8870 # Per bank write bursts +system.physmem.perBankWrBursts::5 9467 # Per bank write bursts +system.physmem.perBankWrBursts::6 9116 # Per bank write bursts +system.physmem.perBankWrBursts::7 8737 # Per bank write bursts +system.physmem.perBankWrBursts::8 8796 # Per bank write bursts +system.physmem.perBankWrBursts::9 9230 # Per bank write bursts +system.physmem.perBankWrBursts::10 9164 # Per bank write bursts +system.physmem.perBankWrBursts::11 8822 # Per bank write bursts +system.physmem.perBankWrBursts::12 9029 # Per bank write bursts +system.physmem.perBankWrBursts::13 8642 # Per bank write bursts +system.physmem.perBankWrBursts::14 8756 # Per bank write bursts +system.physmem.perBankWrBursts::15 8750 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2868318254500 # Total gap between requests +system.physmem.numWrRetry 83 # Number of times write queue was full causing retry +system.physmem.totGap 2868581033500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190444 # Read request sizes (log2) +system.physmem.readPktSize::6 181678 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171449 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164480 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 134188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,178 +180,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads -system.physmem.totQLat 4855930250 # Total ticks spent queuing -system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 81717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 263.471640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.531290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.110863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41089 50.28% 50.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16342 20.00% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5746 7.03% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3516 4.30% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2447 2.99% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1416 1.73% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 997 1.22% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 891 1.09% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9273 11.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81717 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5972 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.034494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 599.214233 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5970 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5972 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.295713 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.853114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 39.858214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5595 93.69% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 97 1.62% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 24 0.40% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 14 0.23% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 35 0.59% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 43 0.72% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 25 0.42% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.20% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.30% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 30 0.50% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 15 0.25% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.12% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.07% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.05% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.12% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.12% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5972 # Writes before turning the bus around for reads +system.physmem.totQLat 4538980935 # Total ticks spent queuing +system.physmem.totMemAccLat 8126137185 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing -system.physmem.readRowHits 167229 # Number of row buffer hits during reads -system.physmem.writeRowHits 112615 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes -system.physmem.avgGap 7626497.96 # Average gap between requests -system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.622475 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states -system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing +system.physmem.readRowHits 160412 # Number of row buffer hits during reads +system.physmem.writeRowHits 94279 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes +system.physmem.avgGap 7960231.97 # Average gap between requests +system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.504870 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states +system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.527135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.408745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states +system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -411,57 +391,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7749 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 7634 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 19044092 # DTB read hits -system.cpu0.dtb.read_misses 6608 # DTB read misses -system.cpu0.dtb.write_hits 15688894 # DTB write hits -system.cpu0.dtb.write_misses 1141 # DTB write misses +system.cpu0.dtb.read_hits 25111402 # DTB read hits +system.cpu0.dtb.read_misses 6533 # DTB read misses +system.cpu0.dtb.write_hits 18719047 # DTB write hits +system.cpu0.dtb.write_misses 1101 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 19050700 # DTB read accesses -system.cpu0.dtb.write_accesses 15690035 # DTB write accesses +system.cpu0.dtb.read_accesses 25117935 # DTB read accesses +system.cpu0.dtb.write_accesses 18720148 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 34732986 # DTB hits -system.cpu0.dtb.misses 7749 # DTB misses -system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.dtb.hits 43830449 # DTB hits +system.cpu0.dtb.misses 7634 # DTB misses +system.cpu0.dtb.accesses 43838083 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,20 +480,20 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348 system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated @@ -523,7 +504,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_hits 118783416 # ITB inst hits system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -540,172 +521,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses -system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses +system.cpu0.itb.hits 118783416 # DTB hits system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 91514175 # DTB accesses -system.cpu0.numCycles 5736637393 # number of cpu cycles simulated +system.cpu0.itb.accesses 118786764 # DTB accesses +system.cpu0.numCycles 5737162881 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 89363678 # Number of instructions committed -system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.committedInsts 115118664 # Number of instructions committed +system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 6606472 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls -system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_func_calls 12673072 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123147620 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written -system.cpu0.num_mem_refs 35866705 # number of memory refs -system.cpu0.num_load_insts 19295047 # Number of load instructions -system.cpu0.num_store_insts 16571658 # Number of store instructions -system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles -system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles -system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles -system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written +system.cpu0.num_mem_refs 44965604 # number of memory refs +system.cpu0.num_load_insts 25362826 # Number of load instructions +system.cpu0.num_store_insts 19602778 # Number of store instructions +system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles +system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles +system.cpu0.Branches 29061799 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction -system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction -system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 97796607 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109233 0.08% 68.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8187 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25362826 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19602778 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 109543126 # Class of executed instruction +system.cpu0.op_class::total 142881904 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 690539 # number of replacements -system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 688886 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.817079 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42962889 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 689398 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.319428 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1149671500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.817079 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966440 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966440 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 364927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361705 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361705 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 32744668 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 32744668 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 33063193 # number of overall hits -system.cpu0.dcache.overall_hits::total 33063193 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394905 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394905 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324481 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324481 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127732 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127732 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21710 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses -system.cpu0.dcache.overall_misses::total 847118 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.021497 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.021497 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.024981 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.024981 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88293922 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88293922 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23854264 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23854264 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17989541 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17989541 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318725 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318725 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364533 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364533 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361797 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361797 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41843805 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41843805 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42162530 # number of overall hits +system.cpu0.dcache.overall_hits::total 42162530 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 393288 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 393288 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 323540 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 323540 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127427 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127427 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21927 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21927 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19722 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19722 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 716828 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 716828 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 844255 # number of overall misses +system.cpu0.dcache.overall_misses::total 844255 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10110788611 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10110788611 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016843 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016843 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019631 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019631 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22089.648616 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14104.901889 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14104.901889 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11975.989021 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11975.989021 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -714,82 +695,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks -system.cpu0.dcache.writebacks::total 504116 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks +system.cpu0.dcache.writebacks::total 504121 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25265 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25265 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 791883 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 791883 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20570.984180 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12902.028637 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12902.028637 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -797,58 +778,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1099798 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1101309 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.453846 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117681586 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1101821 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.806447 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13496302250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.453846 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998933 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998933 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits -system.cpu0.icache.overall_hits::total 90410508 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses -system.cpu0.icache.overall_misses::total 1100319 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 238668662 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 238668662 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 117681586 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117681586 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117681586 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117681586 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117681586 # number of overall hits +system.cpu0.icache.overall_hits::total 117681586 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1101830 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1101830 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1101830 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1101830 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1101830 # number of overall misses +system.cpu0.icache.overall_misses::total 1101830 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10869872254 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10869872254 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 118783416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 118783416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 118783416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 118783416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9865.289794 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9865.289794 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9865.289794 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,223 +838,224 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101830 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1101830 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1839936 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1839962 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 268426 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 237006 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 267761 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16103.938258 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1970214 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284001 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.937349 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.273057 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.106410 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982294 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1127 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15106 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 7915.761025 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.539297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.155291 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4574.741605 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1897.934094 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1714.806946 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.483140 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000033 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.279220 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.115841 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104664 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982906 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1117 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 261 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7809 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3908 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068787 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921997 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39654154 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39654154 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7774 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3610 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053168 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 381762 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1446314 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 504114 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 504114 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28406 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28406 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1700 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1700 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227802 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 227802 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7774 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3610 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1053168 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 609564 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1674116 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7774 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3610 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1053168 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 609564 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1674116 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 215 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 122 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47151 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 94947 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 142435 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26586 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26586 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18299 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18299 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41687 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 41687 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 215 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 122 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 47151 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 136634 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 184122 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 215 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 122 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 47151 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 136634 # number of overall misses -system.cpu0.l2cache.overall_misses::total 184122 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4899750 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2713500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2213649997 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2684439955 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 4905703202 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 458226521 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 458226521 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 356750783 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356750783 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1434495 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1434495 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1789174823 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1789174823 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4899750 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2713500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2213649997 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4473614778 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 6694878025 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4899750 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2713500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2213649997 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4473614778 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 6694878025 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7989 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3732 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1100319 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 476709 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1588749 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 504114 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 504114 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54992 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 54992 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19999 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19999 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269489 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269489 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7989 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3732 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1100319 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 746198 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1858238 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7989 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3732 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1100319 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 746198 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1858238 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032690 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042852 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199172 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.089652 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.483452 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.483452 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.914996 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.914996 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8038 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3680 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068176 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39636813 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39636813 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 8046 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3668 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1054676 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 380878 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1447268 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 504119 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 504119 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28198 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28198 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1754 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1754 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225223 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 225223 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 8046 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3668 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1054676 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 606101 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1672491 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 8046 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3668 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1054676 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 606101 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1672491 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 133 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47154 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 94223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 141733 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26109 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26109 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17961 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 17961 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44010 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44010 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 223 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 133 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 47154 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 138233 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 185743 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 223 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 133 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 47154 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 138233 # number of overall misses +system.cpu0.l2cache.overall_misses::total 185743 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5218750 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3033000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2351090746 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2761351258 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 5120693754 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 483042430 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 483042430 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 364663752 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 364663752 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1698997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1698997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1948619833 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1948619833 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5218750 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3033000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2351090746 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4709971091 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7069313587 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5218750 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3033000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2351090746 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4709971091 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7069313587 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8269 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3801 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1101830 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 475101 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1589001 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 504119 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 504119 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54307 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 54307 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19715 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19715 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8269 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3801 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1101830 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 744334 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1858234 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8269 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3801 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1101830 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 744334 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1858234 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.034991 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042796 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.198322 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.089196 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.480767 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.480767 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911032 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911032 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154689 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154689 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032690 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042852 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183107 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.099084 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032690 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042852 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183107 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.099084 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22241.803279 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46948.102840 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28273.036062 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34441.697630 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17235.632325 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17235.632325 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19495.643642 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19495.643642 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 179311.875000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 179311.875000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 42919.251157 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 42919.251157 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 36361.097669 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 36361.097669 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163464 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163464 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.034991 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042796 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.185714 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.099957 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.034991 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042796 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.185714 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.099957 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22804.511278 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49859.836833 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29306.552094 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36129.156611 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18500.993144 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18500.993144 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.087356 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.087356 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 242713.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 242713.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44276.751488 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44276.751488 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 38059.650092 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 38059.650092 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1082,128 +1064,128 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 196247 # number of writebacks -system.cpu0.l2cache.writebacks::total 196247 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 195381 # number of writebacks +system.cpu0.l2cache.writebacks::total 195381 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 32 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1242 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1242 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1242 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1242 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 215 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 122 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47151 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94915 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 142403 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 246323 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26586 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26586 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18299 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18299 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40477 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 40477 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 215 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 122 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47151 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135392 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 182880 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 215 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 122 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47151 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135392 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 429203 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1859500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 1877090003 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2013208709 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 3895552462 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13906201830 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 448274629 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 448274629 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 246009723 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 246009723 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1112495 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1112495 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1381066645 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1381066645 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1859500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1877090003 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3394275354 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5276619107 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1859500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1877090003 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3394275354 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19182820937 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647209500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5743013251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6390222751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4419325000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4419325000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647209500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10162338251 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10809547751 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199105 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089632 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1212 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1212 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1244 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1244 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1244 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1244 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 223 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 133 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47154 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94191 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 141701 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 243995 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26109 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26109 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17961 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17961 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42798 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 42798 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 223 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 133 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47154 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136989 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 184499 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 223 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 133 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47154 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136989 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 428494 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2168500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2038167254 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2142124308 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4186228812 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13497828640 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 512289208 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 512289208 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 258190050 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 258190050 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1347997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1347997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1547245660 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1547245660 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2168500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2038167254 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3689369968 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5733474472 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2168500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2038167254 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3689369968 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19231303112 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 730253500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5927208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6657462000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4606674000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4606674000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10533882500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11264136000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198255 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089176 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914996 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914996 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911032 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911032 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099287 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230592 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31075.910829 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1213,57 +1195,55 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2221704 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 633519 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1294,59 +1274,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3332 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3283 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10115566 # DTB read hits -system.cpu1.dtb.read_misses 2828 # DTB read misses -system.cpu1.dtb.write_hits 6544640 # DTB write hits -system.cpu1.dtb.write_misses 504 # DTB write misses +system.cpu1.dtb.read_hits 3974119 # DTB read hits +system.cpu1.dtb.read_misses 2776 # DTB read misses +system.cpu1.dtb.write_hits 3444686 # DTB write hits +system.cpu1.dtb.write_misses 507 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10118394 # DTB read accesses -system.cpu1.dtb.write_accesses 6545144 # DTB write accesses +system.cpu1.dtb.read_accesses 3976895 # DTB read accesses +system.cpu1.dtb.write_accesses 3445193 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16660206 # DTB hits -system.cpu1.dtb.misses 3332 # DTB misses -system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.dtb.hits 7418805 # DTB hits +system.cpu1.dtb.misses 3283 # DTB misses +system.cpu1.dtb.accesses 7422088 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1376,42 +1359,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1740 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 44359905 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 16749094 # ITB inst hits +system.cpu1.itb.inst_misses 1740 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1420,178 +1404,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses -system.cpu1.itb.hits 44359905 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 44361651 # DTB accesses -system.cpu1.numCycles 5735725430 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses +system.cpu1.itb.hits 16749094 # DTB hits +system.cpu1.itb.misses 1740 # DTB misses +system.cpu1.itb.accesses 16750834 # DTB accesses +system.cpu1.numCycles 5736248293 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42482884 # Number of instructions committed -system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.committedInsts 16392660 # Number of instructions committed +system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 7121857 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_func_calls 1033061 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17976734 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written -system.cpu1.num_mem_refs 16924073 # number of memory refs -system.cpu1.num_load_insts 10229886 # Number of load instructions -system.cpu1.num_store_insts 6694187 # Number of store instructions -system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles -system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles -system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles -system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written +system.cpu1.num_mem_refs 7653523 # number of memory refs +system.cpu1.num_load_insts 4085696 # Number of load instructions +system.cpu1.num_store_insts 3567827 # Number of store instructions +system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles +system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles +system.cpu1.Branches 2968133 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction -system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction -system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction +system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 54073981 # Class of executed instruction +system.cpu1.op_class::total 20309210 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 191058 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits -system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses -system.cpu1.dcache.overall_misses::total 260939 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2726 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 187627 # number of replacements +system.cpu1.dcache.tags.tagsinuse 465.215072 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7146939 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187994 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.016846 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104853894000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.215072 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 52 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15057330 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15057330 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3659340 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3659340 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3255921 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3255921 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49714 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49714 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79782 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79782 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71812 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71812 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6915261 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6915261 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6964975 # number of overall hits +system.cpu1.dcache.overall_hits::total 6964975 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134401 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134401 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 90853 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 90853 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30496 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30496 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17326 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23466 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23466 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225254 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225254 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255750 # number of overall misses +system.cpu1.dcache.overall_misses::total 255750 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4185537359 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4185537359 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031546 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031546 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035419 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035419 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23524.534987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18581.411913 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16365.737474 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1600,82 +1584,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks -system.cpu1.dcache.writebacks::total 118649 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 117066 # number of writebacks +system.cpu1.dcache.writebacks::total 117066 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 249 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254798 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254798 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21974.250490 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21974.250490 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16860.103466 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16860.103466 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1683,58 +1667,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 526723 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 506368 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.574535 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16242209 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 506880 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.043499 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84702777500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.574535 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973778 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973778 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits -system.cpu1.icache.overall_hits::total 43832665 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 527235 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527235 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 527235 # number of overall misses -system.cpu1.icache.overall_misses::total 527235 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4617960760 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4617960760 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 34005058 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34005058 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16242209 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16242209 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16242209 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16242209 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16242209 # number of overall hits +system.cpu1.icache.overall_hits::total 16242209 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506880 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506880 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506880 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506880 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506880 # number of overall misses +system.cpu1.icache.overall_misses::total 506880 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4441098014 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4441098014 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4441098014 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4441098014 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4441098014 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4441098014 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16749089 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16749089 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16749089 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16749089 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16749089 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16749089 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030263 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030263 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030263 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030263 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8761.635918 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8761.635918 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8761.635918 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1743,219 +1727,220 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506880 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506880 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506880 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506880 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194594 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 194618 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47689 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58318 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 39568 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14853.795199 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 710508 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 54174 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 13.115295 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.748297 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.024093 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.068283 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3300.044649 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1917.167815 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 684.742061 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.546005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000246 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201419 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.117015 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041793 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.906604 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1123 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13469 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1075 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15244499 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15244499 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1729 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 513133 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 102720 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 620673 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 118649 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 118649 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1485 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1485 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 867 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 867 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28139 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28139 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1729 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 513133 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 130859 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 648812 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1729 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 513133 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 130859 # number of overall hits -system.cpu1.l2cache.overall_hits::total 648812 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 14102 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 69212 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 83911 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28339 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28339 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22509 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22509 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35184 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35184 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 14102 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 104396 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 119095 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 14102 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 104396 # number of overall misses -system.cpu1.l2cache.overall_misses::total 119095 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6369000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5421000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 483830740 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1476489366 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1972110106 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 522569379 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 522569379 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 435248439 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 435248439 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1586000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1586000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1289152696 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1289152696 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6369000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5421000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 483830740 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2765642062 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3261262802 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6369000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5421000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 483830740 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2765642062 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3261262802 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3412 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2005 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 527235 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171932 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 704584 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 118649 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 118649 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29824 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29824 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23376 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23376 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63323 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63323 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3412 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2005 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 527235 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 235255 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 767907 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3412 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2005 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 527235 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 235255 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 767907 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137656 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026747 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402554 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.119093 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950208 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950208 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962911 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962911 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1497 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11681 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068542 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.822083 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 14802624 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 14802624 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2949 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1668 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 493694 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 102403 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 600714 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 117066 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 117066 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1062 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1062 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 911 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 911 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27911 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27911 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2949 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1668 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 493694 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 130314 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 628625 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2949 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1668 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 493694 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130314 # number of overall hits +system.cpu1.l2cache.overall_hits::total 628625 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 319 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13186 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 66797 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 80569 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27938 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 27938 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22546 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22546 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33942 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33942 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 319 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13186 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 100739 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 114511 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 319 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13186 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 100739 # number of overall misses +system.cpu1.l2cache.overall_misses::total 114511 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6370500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5365500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 469517986 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1430715000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1911968986 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536455892 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 536455892 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 454234073 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 454234073 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2847500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2847500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1211409437 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1211409437 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6370500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5365500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 469517986 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2642124437 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3123378423 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6370500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5365500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 469517986 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2642124437 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3123378423 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3268 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1935 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 506880 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 169200 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 681283 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 117066 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 117066 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29000 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29000 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61853 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61853 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3268 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1935 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 506880 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 231053 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 743136 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3268 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1935 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 506880 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 231053 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 743136 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137984 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026014 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.394781 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.118261 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.963379 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.963379 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961163 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961163 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555627 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555627 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137656 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026747 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443757 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.155090 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137656 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026747 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443757 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.155090 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19641.304348 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34309.370302 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21332.852193 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23502.402617 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18439.937154 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18439.937154 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19336.640411 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19336.640411 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 528666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36640.310823 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36640.310823 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 27383.708821 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 27383.708821 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.548753 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.548753 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137984 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026014 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.436000 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.154092 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137984 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026014 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.436000 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.154092 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20095.505618 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35607.309722 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21418.851146 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23730.826819 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19201.656955 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19201.656955 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20146.991617 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20146.991617 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 316388.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 316388.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 35690.573243 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35690.573243 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 27275.793793 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 27275.793793 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1964,126 +1949,126 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 31472 # number of writebacks -system.cpu1.l2cache.writebacks::total 31472 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 76 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 76 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 76 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 76 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 276 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 14102 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 69212 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 83911 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 24018 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28339 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28339 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22509 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22509 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35108 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 35108 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 276 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 14102 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104320 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 119019 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 276 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 14102 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104320 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 143037 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3489000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 384250260 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 991800372 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1383661632 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 814752860 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 402368047 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 402368047 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306023777 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306023777 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031661014 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031661014 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3489000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 384250260 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2023461386 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2415322646 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3489000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 384250260 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2023461386 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3230075506 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12590000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 494236499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 506826499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 356773500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 356773500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 25242 # number of writebacks +system.cpu1.l2cache.writebacks::total 25242 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 89 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 89 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 89 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 319 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 13186 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66797 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 80569 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 22684 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27938 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27938 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22546 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22546 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33853 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33853 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 319 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13186 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 100650 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 114422 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 319 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13186 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 100650 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 137106 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3630000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 382998014 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 996392500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1387317514 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 708613533 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 439996296 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 439996296 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 340047738 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 340047738 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2503000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2503000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 980626782 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 980626782 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3630000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 382998014 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1977019282 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2367944296 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3630000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 382998014 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1977019282 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3076557829 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14041750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 382270250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 396312000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 262085000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 262085000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14041750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 644355250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 658397000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.394781 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.118261 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961163 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961163 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153972 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184497 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14916.725302 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17218.998796 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20694.834000 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22439.264722 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2093,64 +2078,62 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1026038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 726618 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75553 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 567913 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31024 # Transaction distribution -system.iobus.trans_dist::ReadResp 31024 # Transaction distribution -system.iobus.trans_dist::WriteReq 59440 # Transaction distribution -system.iobus.trans_dist::WriteResp 23216 # Transaction distribution +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59423 # Transaction distribution +system.iobus.trans_dist::WriteResp 23199 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2171,11 +2154,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2196,11 +2179,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2240,23 +2223,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2270,14 +2253,14 @@ system.iocache.demand_misses::realview.ide 255 # system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2294,19 +2277,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128115.203922 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128115.203922 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22637 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3456 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.550058 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2320,14 +2303,14 @@ system.iocache.demand_mshr_misses::realview.ide 255 system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19398377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19398377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19398377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19398377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2336,303 +2319,290 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76072.066667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76072.066667 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130735 # number of replacements -system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use -system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. +system.l2c.tags.replacements 120296 # number of replacements +system.l2c.tags.tagsinuse 63905.436039 # Cycle average of tags in use +system.l2c.tags.total_refs 339434 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 184689 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.837868 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4931105 # Number of tag accesses -system.l2c.tags.data_accesses 4931105 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits -system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits -system.l2c.Writeback_hits::total 227719 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits -system.l2c.demand_hits::total 151998 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits -system.l2c.overall_hits::cpu0.data 49428 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits -system.l2c.overall_hits::cpu1.data 10034 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits -system.l2c.overall_hits::total 151998 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 11082.113172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.011404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.058569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7219.690376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2883.100910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39595.862719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1402.790170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 257.162663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1460.646056 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.169100 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.110164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.604185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.975120 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33682 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 30706 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 154 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4910 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 28614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1859 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28608 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.513947 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.468536 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4789457 # Number of tag accesses +system.l2c.tags.data_accesses 4789457 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 70 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 29564 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45272 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 28 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 10986 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 7565 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4624 # number of ReadReq hits +system.l2c.ReadReq_hits::total 145969 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 220623 # number of Writeback hits +system.l2c.Writeback_hits::total 220623 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2700 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 726 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3426 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 152 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 169 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 321 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4139 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2014 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6153 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29564 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49411 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 28 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10986 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9579 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 4624 # number of demand (read+write) hits +system.l2c.demand_hits::total 152122 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits +system.l2c.overall_hits::cpu0.inst 29564 # number of overall hits +system.l2c.overall_hits::cpu0.data 49411 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47744 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 28 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits +system.l2c.overall_hits::cpu1.inst 10986 # number of overall hits +system.l2c.overall_hits::cpu1.data 9579 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 4624 # number of overall hits +system.l2c.overall_hits::total 152122 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 17779 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8894 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2435 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 924 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq misses -system.l2c.ReadReq_misses::total 170945 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8889 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11787 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1209 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1967 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11387 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8562 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19949 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 17590 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2200 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 584 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq misses +system.l2c.ReadReq_misses::total 164735 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8579 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2656 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11235 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 453 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 10640 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6753 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 17393 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17779 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2435 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9486 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) misses -system.l2c.demand_misses::total 190894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17590 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19401 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 130188 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2200 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7337 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5403 # number of demand (read+write) misses +system.l2c.demand_misses::total 182128 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17779 # number of overall misses -system.l2c.overall_misses::cpu0.data 20281 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 134996 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2435 # number of overall misses -system.l2c.overall_misses::cpu1.data 9486 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5907 # number of overall misses -system.l2c.overall_misses::total 190894 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 494750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1299838245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 708631748 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 182647247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 78676500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16020624042 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 5423319 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2108409 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7531728 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 679977 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 605974 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1285951 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 888864663 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 627516972 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1516381635 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 494750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1299838245 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1597496411 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 182647247 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 706193472 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17537005677 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 494750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1299838245 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1597496411 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 182647247 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 706193472 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17537005677 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 89 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 47151 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 54460 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180488 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 35 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 41 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 14102 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 9461 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 317584 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 227719 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 227719 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11251 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3668 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 14919 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 922 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1373 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2295 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10059 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25308 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 89 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 47151 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 69709 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180488 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 41 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 14102 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19520 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11692 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 342892 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 89 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 47151 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 69709 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180488 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 41 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 14102 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19520 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11692 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 342892 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.377065 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.163313 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.172671 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.097664 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.538267 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.790063 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790076 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.790066 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822126 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.880554 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.857081 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.746737 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.851178 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.788249 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.377065 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290938 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.172671 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.485963 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.556718 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.377065 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290938 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.172671 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.485963 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.556718 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73110.874909 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 79675.258376 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75009.136345 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 85147.727273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 93718.003112 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 610.115761 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 727.539337 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 638.986002 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 897.067282 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 501.219189 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 653.762583 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78059.599807 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73290.933427 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76012.914682 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 91867.767855 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 91867.767855 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 17590 # number of overall misses +system.l2c.overall_misses::cpu0.data 19401 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 130188 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2200 # number of overall misses +system.l2c.overall_misses::cpu1.data 7337 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5403 # number of overall misses +system.l2c.overall_misses::total 182128 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 549750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1421225252 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 758301308 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 181920507 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 52732500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15758293199 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 14082590 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2976406 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 17058996 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1006973 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1562950 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2569923 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 947359927 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 541992722 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1489352649 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 549750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1421225252 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1705661235 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 181920507 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 594725222 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17247645848 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 549750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1421225252 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1705661235 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 181920507 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 594725222 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17247645848 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 90 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 72 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 47154 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 54033 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 177932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 28 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13186 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 8149 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 10027 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 310704 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 220623 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 220623 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3382 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 14661 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 605 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1431 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2036 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 14779 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8767 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 23546 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 90 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 47154 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 68812 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13186 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 16916 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10027 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 334250 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 90 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 47154 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 68812 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13186 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 16916 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10027 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 334250 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.373033 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.162142 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.166844 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.071665 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.530199 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.760617 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.785334 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.766319 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.748760 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.881901 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.842338 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.719940 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.770275 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.738682 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.373033 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281942 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.166844 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.433731 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.544886 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.373033 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281942 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.166844 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.433731 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.544886 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80797.342354 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 86554.195640 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82691.139545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 90295.376712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 95658.440520 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1641.518825 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1120.634789 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1518.379706 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2222.898455 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1238.470681 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1498.497376 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89037.587124 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80259.547164 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85629.428448 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94700.682202 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94700.682202 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2641,186 +2611,174 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99035 # number of writebacks -system.l2c.writebacks::total 99035 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 4 # number of overall MSHR hits +system.l2c.writebacks::writebacks 92066 # number of writebacks +system.l2c.writebacks::total 92066 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 17779 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8894 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2432 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 923 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 170941 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8889 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2898 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11787 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 758 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1209 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1967 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8562 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19949 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 17588 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8761 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2195 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 584 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 164728 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8579 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2656 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11235 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 453 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1262 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 10640 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6753 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 17393 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17779 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20281 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2432 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9485 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 190890 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19401 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2195 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7337 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 182121 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17779 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20281 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2432 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9485 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 190890 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 408750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1075716745 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 597785248 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 151904497 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 67178000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 13890498792 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90106352 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 29086385 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 119192737 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7710755 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12095707 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 19806462 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 746306335 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 519227026 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1265533361 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1075716745 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1344091583 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 151904497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 586405026 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15156032153 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 408750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1075716745 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1344091583 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 151904497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 586405026 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15156032153 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476665000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5183212748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9260500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 424539000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6093677248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3944737000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 304049000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4248786000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476665000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9127949748 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9260500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728588000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10342463248 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163313 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.097558 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.538254 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790063 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790076 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.790066 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.822126 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.880554 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857081 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746737 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851178 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.788249 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.556706 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.556706 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 17588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19401 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2195 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 7337 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 182121 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 462250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1200652248 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 648693692 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 154097993 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 45421500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 13719540491 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 153128559 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47338644 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 200467203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8146450 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22467762 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 30614212 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 815815573 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457532278 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1273347851 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 462250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1200652248 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1464509265 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 154097993 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 502953778 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 14992888342 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 462250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1200652248 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1464509265 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 154097993 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 502953778 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14992888342 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 549810500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5306549000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10505750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 321692750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6188558000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4079142000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 216691500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4295833500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 549810500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9385691000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10505750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538384250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10484391500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.162142 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.530177 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.760617 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.785334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.766319 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.748760 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.881901 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.842338 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719940 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.770275 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.738682 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.544865 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.544865 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74043.338888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77776.541096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83286.026000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.231729 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17823.284639 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17843.097730 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17983.333333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.297940 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17850.852478 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76674.395959 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67752.447505 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73210.363422 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2835,58 +2793,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215303 # Transaction distribution -system.membus.trans_dist::ReadResp 215303 # Transaction distribution -system.membus.trans_dist::WriteReq 30982 # Transaction distribution -system.membus.trans_dist::WriteResp 30982 # Transaction distribution -system.membus.trans_dist::Writeback 135225 # Transaction distribution +system.membus.trans_dist::ReadReq 209058 # Transaction distribution +system.membus.trans_dist::ReadResp 209058 # Transaction distribution +system.membus.trans_dist::WriteReq 30943 # Transaction distribution +system.membus.trans_dist::WriteResp 30943 # Transaction distribution +system.membus.trans_dist::Writeback 128256 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 40350 # Transaction distribution -system.membus.trans_dist::ReadExResp 19836 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40095 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13060 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.membus.trans_dist::ReadExReq 37613 # Transaction distribution +system.membus.trans_dist::ReadExResp 17283 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 634735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 756359 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 865267 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17575592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17765802 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123675 # Total snoops (count) -system.membus.snoop_fanout::samples 499419 # Request fanout histogram +system.membus.pkt_size::total 22401258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125085 # Total snoops (count) +system.membus.snoop_fanout::samples 484369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 484369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 499419 # Request fanout histogram -system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484369 # Request fanout histogram +system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2919,44 +2877,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 286323 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 289326 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b3648bdab..08c475a80 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902862 # Number of seconds simulated -sim_ticks 2902861767000 # Number of ticks simulated -final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903548 # Number of seconds simulated +sim_ticks 2903547931500 # Number of ticks simulated +final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 747193 # Simulator instruction rate (inst/s) -host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19275657141 # Simulator tick rate (ticks/s) -host_mem_usage 615228 # Number of bytes of host memory used -host_seconds 150.60 # Real time elapsed on the host -sim_insts 112525269 # Number of instructions simulated -sim_ops 135672104 # Number of ops (including micro ops) simulated +host_inst_rate 732027 # Simulator instruction rate (inst/s) +host_op_rate 882601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18897780106 # Simulator tick rate (ticks/s) +host_mem_usage 614620 # Number of bytes of host memory used +host_seconds 153.65 # Real time elapsed on the host +sim_insts 112472279 # Number of instructions simulated +sim_ops 135607130 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory +system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory +system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168015 # Number of read requests accepted -system.physmem.writeReqs 158980 # Number of write requests accepted -system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9689 # Per bank write bursts -system.physmem.perBankRdBursts::1 9230 # Per bank write bursts -system.physmem.perBankRdBursts::2 10198 # Per bank write bursts -system.physmem.perBankRdBursts::3 10267 # Per bank write bursts -system.physmem.perBankRdBursts::4 18984 # Per bank write bursts -system.physmem.perBankRdBursts::5 10226 # Per bank write bursts -system.physmem.perBankRdBursts::6 10551 # Per bank write bursts -system.physmem.perBankRdBursts::7 10350 # Per bank write bursts -system.physmem.perBankRdBursts::8 9702 # Per bank write bursts -system.physmem.perBankRdBursts::9 9930 # Per bank write bursts -system.physmem.perBankRdBursts::10 9908 # Per bank write bursts -system.physmem.perBankRdBursts::11 8848 # Per bank write bursts -system.physmem.perBankRdBursts::12 9929 # Per bank write bursts -system.physmem.perBankRdBursts::13 10408 # Per bank write bursts -system.physmem.perBankRdBursts::14 9925 # Per bank write bursts -system.physmem.perBankRdBursts::15 9750 # Per bank write bursts -system.physmem.perBankWrBursts::0 9389 # Per bank write bursts -system.physmem.perBankWrBursts::1 8975 # Per bank write bursts -system.physmem.perBankWrBursts::2 10251 # Per bank write bursts -system.physmem.perBankWrBursts::3 9953 # Per bank write bursts -system.physmem.perBankWrBursts::4 9418 # Per bank write bursts -system.physmem.perBankWrBursts::5 9499 # Per bank write bursts -system.physmem.perBankWrBursts::6 9770 # Per bank write bursts -system.physmem.perBankWrBursts::7 9764 # Per bank write bursts -system.physmem.perBankWrBursts::8 9682 # Per bank write bursts -system.physmem.perBankWrBursts::9 9836 # Per bank write bursts -system.physmem.perBankWrBursts::10 9791 # Per bank write bursts -system.physmem.perBankWrBursts::11 9091 # Per bank write bursts -system.physmem.perBankWrBursts::12 9681 # Per bank write bursts -system.physmem.perBankWrBursts::13 9852 # Per bank write bursts -system.physmem.perBankWrBursts::14 9372 # Per bank write bursts -system.physmem.perBankWrBursts::15 9026 # Per bank write bursts +system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168876 # Number of read requests accepted +system.physmem.writeReqs 160010 # Number of write requests accepted +system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10030 # Per bank write bursts +system.physmem.perBankRdBursts::1 9665 # Per bank write bursts +system.physmem.perBankRdBursts::2 10302 # Per bank write bursts +system.physmem.perBankRdBursts::3 9920 # Per bank write bursts +system.physmem.perBankRdBursts::4 18863 # Per bank write bursts +system.physmem.perBankRdBursts::5 10093 # Per bank write bursts +system.physmem.perBankRdBursts::6 10296 # Per bank write bursts +system.physmem.perBankRdBursts::7 10601 # Per bank write bursts +system.physmem.perBankRdBursts::8 9928 # Per bank write bursts +system.physmem.perBankRdBursts::9 10198 # Per bank write bursts +system.physmem.perBankRdBursts::10 9956 # Per bank write bursts +system.physmem.perBankRdBursts::11 9036 # Per bank write bursts +system.physmem.perBankRdBursts::12 9857 # Per bank write bursts +system.physmem.perBankRdBursts::13 10481 # Per bank write bursts +system.physmem.perBankRdBursts::14 9974 # Per bank write bursts +system.physmem.perBankRdBursts::15 9528 # Per bank write bursts +system.physmem.perBankWrBursts::0 8313 # Per bank write bursts +system.physmem.perBankWrBursts::1 8253 # Per bank write bursts +system.physmem.perBankWrBursts::2 9067 # Per bank write bursts +system.physmem.perBankWrBursts::3 8494 # Per bank write bursts +system.physmem.perBankWrBursts::4 8419 # Per bank write bursts +system.physmem.perBankWrBursts::5 8394 # Per bank write bursts +system.physmem.perBankWrBursts::6 8676 # Per bank write bursts +system.physmem.perBankWrBursts::7 8975 # Per bank write bursts +system.physmem.perBankWrBursts::8 8824 # Per bank write bursts +system.physmem.perBankWrBursts::9 8984 # Per bank write bursts +system.physmem.perBankWrBursts::10 8586 # Per bank write bursts +system.physmem.perBankWrBursts::11 8136 # Per bank write bursts +system.physmem.perBankWrBursts::12 8548 # Per bank write bursts +system.physmem.perBankWrBursts::13 8715 # Per bank write bursts +system.physmem.perBankWrBursts::14 8203 # Per bank write bursts +system.physmem.perBankWrBursts::15 7843 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2902861390500 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 2903547607000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158443 # Read request sizes (log2) +system.physmem.readPktSize::6 159304 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 154599 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see +system.physmem.writePktSize::6 155629 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,178 +159,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 324.004977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.393020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.651376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21725 36.04% 36.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14933 24.77% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5631 9.34% 70.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2561 4.25% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1497 2.48% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1055 1.75% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 577.316613 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5492 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads -system.physmem.totQLat 1487834250 # Total ticks spent queuing -system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5494 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.832545 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.556239 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 46.623010 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5170 94.10% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 87 1.58% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.31% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.22% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.35% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 28 0.51% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 22 0.40% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.25% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 9 0.16% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 4 0.07% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 29 0.53% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 12 0.22% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 6 0.11% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.04% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.13% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 8 0.15% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 4 0.07% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.07% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 10 0.18% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads +system.physmem.totQLat 1499821694 # Total ticks spent queuing +system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 138089 # Number of row buffer hits during reads -system.physmem.writeRowHits 122193 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes -system.physmem.avgGap 8877387.70 # Average gap between requests -system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.522458 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states -system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing +system.physmem.readRowHits 138826 # Number of row buffer hits during reads +system.physmem.writeRowHits 106054 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes +system.physmem.avgGap 8828431.76 # Average gap between requests +system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.525264 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states +system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.435479 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states -system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.425095 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states +system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -380,57 +365,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9552 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9545 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24537663 # DTB read hits -system.cpu.dtb.read_misses 8142 # DTB read misses -system.cpu.dtb.write_hits 19618927 # DTB write hits -system.cpu.dtb.write_misses 1410 # DTB write misses +system.cpu.dtb.read_hits 24524755 # DTB read hits +system.cpu.dtb.read_misses 8132 # DTB read misses +system.cpu.dtb.write_hits 19610055 # DTB write hits +system.cpu.dtb.write_misses 1413 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24545805 # DTB read accesses -system.cpu.dtb.write_accesses 19620337 # DTB write accesses +system.cpu.dtb.read_accesses 24532887 # DTB read accesses +system.cpu.dtb.write_accesses 19611468 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44156590 # DTB hits -system.cpu.dtb.misses 9552 # DTB misses -system.cpu.dtb.accesses 44166142 # DTB accesses +system.cpu.dtb.hits 44134810 # DTB hits +system.cpu.dtb.misses 9545 # DTB misses +system.cpu.dtb.accesses 44144355 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,18 +453,18 @@ system.cpu.itb.walker.walkWaitTime::samples 4762 # system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated @@ -490,7 +475,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115624412 # ITB inst hits +system.cpu.itb.inst_hits 115569545 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -507,38 +492,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115629174 # ITB inst accesses -system.cpu.itb.hits 115624412 # DTB hits +system.cpu.itb.inst_accesses 115574307 # ITB inst accesses +system.cpu.itb.hits 115569545 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115629174 # DTB accesses -system.cpu.numCycles 5805723534 # number of cpu cycles simulated +system.cpu.itb.accesses 115574307 # DTB accesses +system.cpu.numCycles 5807095863 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112525269 # Number of instructions committed -system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9899985 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls -system.cpu.num_int_insts 119969678 # number of integer instructions -system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read -system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read +system.cpu.committedInsts 112472279 # Number of instructions committed +system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses +system.cpu.num_func_calls 9892504 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls +system.cpu.num_int_insts 119910547 # number of integer instructions +system.cpu.num_fp_insts 11161 # number of float instructions +system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read +system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written -system.cpu.num_mem_refs 45438019 # number of memory refs -system.cpu.num_load_insts 24860597 # Number of load instructions -system.cpu.num_store_insts 20577422 # Number of store instructions -system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles -system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927847 # Percentage of idle cycles -system.cpu.Branches 25932360 # Number of branches fetched +system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written +system.cpu.num_mem_refs 45415290 # number of memory refs +system.cpu.num_load_insts 24846976 # Number of load instructions +system.cpu.num_store_insts 20568314 # Number of store instructions +system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles +system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles +system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927424 # Percentage of idle cycles +system.cpu.Branches 25918910 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -562,194 +547,194 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138794587 # Class of executed instruction +system.cpu.op_class::total 138727463 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 823321 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 820494 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18835651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits -system.cpu.dcache.overall_hits::total 42354457 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 299019 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 299019 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177143306 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177143306 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23115915 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23115915 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18827300 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18827300 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392830 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392830 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443506 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443506 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460403 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460403 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41943215 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41943215 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42336045 # number of overall hits +system.cpu.dcache.overall_hits::total 42336045 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 400875 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 400875 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298693 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298693 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118357 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118357 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 701722 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 820894 # number of overall misses -system.cpu.dcache.overall_misses::total 820894 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916458250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5916458250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11650381750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280295250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 280295250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17566840000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17566840000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17566840000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17566840000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23529387 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23529387 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19134670 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19134670 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511294 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511294 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466379 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466379 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460572 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460572 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42664057 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42664057 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43175351 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43175351 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017115 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015627 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233079 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.233079 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048765 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048765 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 699568 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 699568 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 817925 # number of overall misses +system.cpu.dcache.overall_misses::total 817925 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5965444702 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5965444702 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639649008 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12639649008 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280760500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 280760500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18605093710 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18605093710 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18605093710 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18605093710 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23516790 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23516790 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19125993 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19125993 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511187 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511187 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466191 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466191 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460405 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460405 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42642783 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42642783 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43153970 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43153970 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231534 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231534 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048660 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048660 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019013 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019013 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38962.011611 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12324.462472 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12324.462472 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25033.902315 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25033.902315 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21399.644778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21399.644778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.016405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018954 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018954 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14881.059437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14881.059437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42316.522342 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42316.522342 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12376.482257 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12376.482257 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26595.118287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22746.698915 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 686487 # number of writebacks -system.cpu.dcache.writebacks::total 686487 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 629 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14254 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14254 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 629 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 629 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 629 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 402074 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 402074 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299019 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299019 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8489 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8489 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683915 # number of writebacks +system.cpu.dcache.writebacks::total 683915 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 674 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14143 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14143 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 400201 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298693 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298693 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116343 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116343 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 701093 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 701093 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 818114 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 818114 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5098164750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5098164750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994871250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994871250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411142000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411142000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 100012000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 100012000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16093036000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16093036000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17504178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17504178000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791398250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791398250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429682000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429682000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483461242 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17483461242 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18953838790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18953838790 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833129500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833129500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4513032000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4513032000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346161500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346161500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227594 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227594 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018323 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018323 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016390 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018891 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018891 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13367.614649 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13367.614649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40622.741383 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40622.741383 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12638.298376 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12638.298376 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -757,59 +742,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1701491 # number of replacements -system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1698619 # number of replacements +system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997528 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997528 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117326421 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117326421 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113922403 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113922403 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113922403 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113922403 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113922403 # number of overall hits -system.cpu.icache.overall_hits::total 113922403 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1702009 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1702009 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1702009 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1702009 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1702009 # number of overall misses -system.cpu.icache.overall_misses::total 1702009 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23268250500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23268250500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23268250500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23268250500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23268250500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23268250500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115624412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115624412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115624412 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115624412 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115624412 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115624412 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014720 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014720 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014720 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014720 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014720 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014720 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13671.050212 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13671.050212 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13671.050212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13671.050212 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117268682 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117268682 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113870408 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113870408 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113870408 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113870408 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113870408 # number of overall hits +system.cpu.icache.overall_hits::total 113870408 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699137 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699137 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699137 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699137 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699137 # number of overall misses +system.cpu.icache.overall_misses::total 1699137 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23363194999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23363194999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23363194999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23363194999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23363194999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23363194999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115569545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115569545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115569545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115569545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115569545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115569545 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13750.036047 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13750.036047 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13750.036047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13750.036047 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -818,196 +803,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1702009 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1702009 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1702009 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1702009 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1702009 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1702009 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19857660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19857660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19857660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19857660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19857660500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19857660500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014720 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014720 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014720 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11667.188893 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11667.188893 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 677067750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 88884 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64931.599128 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2763158 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 154151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.925009 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 89783 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50668.289778 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9584.205539 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4675.282236 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.773137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9560.730853 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4902.381289 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.769944 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146243 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.071339 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.990778 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145885 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.074804 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.990692 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65262 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65228 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6961 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995819 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26260695 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26260695 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6986 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3658 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1683931 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 515395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2209970 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 686487 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 686487 # number of Writeback hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26192754 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26192754 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6798 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681053 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 512833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2204235 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 683915 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 683915 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 166042 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 166042 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6986 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3658 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1683931 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 681437 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2376012 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6986 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3658 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1683931 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 681437 # number of overall hits -system.cpu.l2cache.overall_hits::total 2376012 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 164921 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164921 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6798 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681053 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 677754 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2369156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6798 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681053 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 677754 # number of overall hits +system.cpu.l2cache.overall_hits::total 2369156 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 12189 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 30251 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2710 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2710 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 18063 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 12253 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 30325 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2714 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2714 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130244 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130244 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131035 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131035 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18053 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142433 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 160495 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18063 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143288 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 161360 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18053 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142433 # number of overall misses -system.cpu.l2cache.overall_misses::total 160495 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 495250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1316295500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 927332750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2244273000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 444481 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 444481 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8974834460 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8974834460 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 495250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1316295500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9902167210 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11219107460 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 495250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1316295500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9902167210 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11219107460 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6993 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3660 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1701984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 527584 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2240221 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 686487 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 686487 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2733 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2733 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 18063 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143288 # number of overall misses +system.cpu.l2cache.overall_misses::total 161360 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 722250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 165500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1457697500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1014855798 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2473441048 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 528483 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 528483 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10018114706 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10018114706 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 722250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 165500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1457697500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11032970504 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12491555754 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 722250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 165500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1457697500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11032970504 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12491555754 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6805 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699116 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 525086 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2234560 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 683915 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 683915 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2737 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2737 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296286 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296286 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6993 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3660 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1701984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 823870 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2536507 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6993 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3660 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1701984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 823870 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2536507 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001001 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000546 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013504 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991584 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991584 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295956 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295956 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6805 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699116 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 821042 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530516 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6805 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699116 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 821042 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530516 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001029 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010631 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023335 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013571 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991597 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991597 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439589 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.439589 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001001 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000546 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063274 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001001 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000546 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063274 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72912.839971 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76079.477398 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74188.390466 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 164.015129 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 164.015129 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68907.853414 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68907.853414 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69903.158728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69903.158728 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442752 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.442752 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001029 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010631 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.174520 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063766 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001029 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010631 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.174520 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063766 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103178.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80700.741848 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82825.087570 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81564.420379 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 194.724761 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 194.724761 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76453.731492 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76453.731492 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77414.202739 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77414.202739 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1016,100 +1001,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 82185 # number of writebacks -system.cpu.l2cache.writebacks::total 82185 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83215 # number of writebacks +system.cpu.l2cache.writebacks::total 83215 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18053 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12189 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 30251 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2710 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2710 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12253 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 30325 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2714 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2714 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130244 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130244 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131035 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131035 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 18053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142433 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 160495 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 18053 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142433 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 160495 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 408750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1090271000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 775288750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1866093500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27282710 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27282710 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7345006540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7345006540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1090271000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8120295290 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9211100040 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 408750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1090271000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8120295290 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9211100040 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098165500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8377798294 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8377798294 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 635250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 140500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1231366500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9239411996 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10471554246 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 635250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 140500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1231366500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9239411996 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10471554246 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 546237750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5396778750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5943016500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4154268500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4154268500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 546237750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551047250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10097285000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023335 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991597 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991597 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442752 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442752 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063766 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063766 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1119,61 +1104,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53107 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53413 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1194,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1219,11 +1202,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1263,23 +1246,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1293,14 +1276,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1317,19 +1300,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1343,14 +1326,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1359,66 +1342,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70661 # Transaction distribution -system.membus.trans_dist::ReadResp 70661 # Transaction distribution -system.membus.trans_dist::WriteReq 27618 # Transaction distribution -system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 118375 # Transaction distribution +system.membus.trans_dist::ReadReq 70719 # Transaction distribution +system.membus.trans_dist::ReadResp 70719 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 119405 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution -system.membus.trans_dist::ReadExReq 128454 # Transaction distribution -system.membus.trans_dist::ReadExResp 128454 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution +system.membus.trans_dist::ReadExReq 129241 # Transaction distribution +system.membus.trans_dist::ReadExResp 129241 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 318040 # Request fanout histogram +system.membus.snoop_fanout::samples 319985 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 318040 # Request fanout histogram -system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 319985 # Request fanout histogram +system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index f0c87683a..33aa26eaf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867165000 # Number of ticks simulated -final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783867052000 # Number of ticks simulated +final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1311458 # Simulator instruction rate (inst/s) -host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25571502260 # Simulator tick rate (ticks/s) -host_mem_usage 616488 # Number of bytes of host memory used -host_seconds 108.87 # Real time elapsed on the host -sim_insts 142773109 # Number of instructions simulated -sim_ops 173803334 # Number of ops (including micro ops) simulated +host_inst_rate 1291395 # Simulator instruction rate (inst/s) +host_op_rate 1572066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25180347721 # Simulator tick rate (ticks/s) +host_mem_usage 616688 # Number of bytes of host memory used +host_seconds 110.56 # Real time elapsed on the host +sim_insts 142772879 # Number of instructions simulated +sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 728420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 728356 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4660384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 482432 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 5667588 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 728420 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 11540232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 728356 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 482432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837248 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837184 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8854772 # Number of bytes written to this memory +system.physmem.bytes_written::total 8854708 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19834 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 73337 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 7538 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 88557 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189290 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138082 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189289 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138081 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142463 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142462 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 261635 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1674068 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 173296 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 2035869 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 261635 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 173296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174450 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174427 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174427 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 261635 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1680360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 173296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 2035872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326119 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5682 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 5683 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5683 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5683 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5683 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5683 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.40% 65.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1613 34.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4662 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5683 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5683 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4662 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4662 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10345 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15994592 # DTB read hits -system.cpu0.dtb.read_misses 4787 # DTB read misses -system.cpu0.dtb.write_hits 11285776 # DTB write hits +system.cpu0.dtb.read_hits 15994593 # DTB read hits +system.cpu0.dtb.read_misses 4788 # DTB read misses +system.cpu0.dtb.write_hits 11285810 # DTB write hits system.cpu0.dtb.write_misses 895 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3233 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 774 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 773 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 200 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 15999379 # DTB read accesses -system.cpu0.dtb.write_accesses 11286671 # DTB write accesses +system.cpu0.dtb.read_accesses 15999381 # DTB read accesses +system.cpu0.dtb.write_accesses 11286705 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27280368 # DTB hits -system.cpu0.dtb.misses 5682 # DTB misses -system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.dtb.hits 27280403 # DTB hits +system.cpu0.dtb.misses 5683 # DTB misses +system.cpu0.dtb.accesses 27286086 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,7 +202,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74779253 # ITB inst hits +system.cpu0.itb.inst_hits 74779098 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -219,38 +219,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74781864 # ITB inst accesses -system.cpu0.itb.hits 74779253 # DTB hits +system.cpu0.itb.inst_accesses 74781709 # ITB inst accesses +system.cpu0.itb.hits 74779098 # DTB hits system.cpu0.itb.misses 2611 # DTB misses -system.cpu0.itb.accesses 74781864 # DTB accesses -system.cpu0.numCycles 5536444795 # number of cpu cycles simulated +system.cpu0.itb.accesses 74781709 # DTB accesses +system.cpu0.numCycles 5536444792 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72626511 # Number of instructions committed -system.cpu0.committedOps 87972361 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77485845 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5272 # Number of float alu accesses -system.cpu0.num_func_calls 8692455 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9458284 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77485845 # number of integer instructions -system.cpu0.num_fp_insts 5272 # number of float instructions -system.cpu0.num_int_register_reads 144065543 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54441741 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4114 # number of times the floating registers were read +system.cpu0.committedInsts 72626333 # Number of instructions committed +system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5256 # Number of float alu accesses +system.cpu0.num_func_calls 8692525 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9458276 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77485858 # number of integer instructions +system.cpu0.num_fp_insts 5256 # number of float instructions +system.cpu0.num_int_register_reads 144065688 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54441738 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4098 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1160 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268855206 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31825195 # number of times the CC registers were written -system.cpu0.num_mem_refs 27911692 # number of memory refs -system.cpu0.num_load_insts 16162187 # Number of load instructions -system.cpu0.num_store_insts 11749505 # Number of store instructions -system.cpu0.num_idle_cycles 5353607103.050808 # Number of idle cycles -system.cpu0.num_busy_cycles 182837691.949192 # Number of busy cycles +system.cpu0.num_cc_register_reads 268855171 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31825079 # number of times the CC registers were written +system.cpu0.num_mem_refs 27911721 # number of memory refs +system.cpu0.num_load_insts 16162181 # Number of load instructions +system.cpu0.num_store_insts 11749540 # Number of store instructions +system.cpu0.num_idle_cycles 5353607317.458248 # Number of idle cycles +system.cpu0.num_busy_cycles 182837474.541752 # Number of busy cycles system.cpu0.not_idle_fraction 0.033024 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.966976 # Percentage of idle cycles -system.cpu0.Branches 18597060 # Number of branches fetched +system.cpu0.Branches 18597106 # Number of branches fetched system.cpu0.op_class::No_OpClass 2189 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61764761 68.82% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59661 0.07% 68.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 61764727 68.82% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59660 0.07% 68.89% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction @@ -274,25 +274,25 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.89% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4406 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4403 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16162187 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11749505 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16162181 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89742709 # Class of executed instruction +system.cpu0.op_class::total 89742700 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 819403 # number of replacements +system.cpu0.dcache.tags.replacements 819402 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53784478 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597627 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597629 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821680 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821817 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175357 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929339 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070655 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -301,86 +301,86 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219237567 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219237567 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15302739 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14826353 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30129092 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10898468 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11441639 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186053 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209002 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395055 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235062 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222268 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219237306 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219237306 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15302738 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14826284 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30129022 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10898497 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11441613 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186051 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209007 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395058 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235059 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222271 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457330 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236768 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223368 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236765 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223371 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26201207 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26267992 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52469199 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26387260 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26476994 # number of overall hits -system.cpu0.dcache.overall_hits::total 52864254 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197067 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199240 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396307 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137729 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 163949 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26201235 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26267897 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52469132 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26387286 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26476904 # number of overall hits +system.cpu0.dcache.overall_hits::total 52864190 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197065 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 199241 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396306 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137741 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 163937 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54389 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61684 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54401 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61672 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 116073 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3967 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334796 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 363189 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697985 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389185 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424873 # number of overall misses -system.cpu0.dcache.overall_misses::total 814058 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499806 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025593 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605588 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240442 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270686 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511128 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239724 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334806 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 363178 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697984 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389207 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424850 # number of overall misses +system.cpu0.dcache.overall_misses::total 814057 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025525 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036238 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605550 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240452 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270679 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511131 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239721 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226238 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236768 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223370 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236765 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223373 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26536003 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631181 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26776445 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26901867 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53678312 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26536041 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631075 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26776493 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26901754 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53678247 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012714 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013260 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012480 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014127 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012481 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014126 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226204 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227880 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227092 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019447 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226245 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227842 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227091 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019448 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017535 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012617 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013638 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013637 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014535 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015793 # miss rate for overall accesses @@ -393,19 +393,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682284 # number of writebacks -system.cpu0.dcache.writebacks::total 682284 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682283 # number of writebacks +system.cpu0.dcache.writebacks::total 682283 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699220 # number of replacements +system.cpu0.icache.tags.replacements 1699214 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145342961 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 145342721 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127365 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127325 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536356 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110422 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110423 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -413,43 +413,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148742437 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148742437 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73936562 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71406399 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145342961 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73936562 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71406399 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145342961 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73936562 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71406399 # number of overall hits -system.cpu0.icache.overall_hits::total 145342961 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844577 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855161 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699738 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844577 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855161 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699738 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844577 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855161 # number of overall misses -system.cpu0.icache.overall_misses::total 1699738 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74781139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261560 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74781139 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72261560 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74781139 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72261560 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 148742185 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148742185 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73936444 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71406277 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145342721 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73936444 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71406277 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145342721 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73936444 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71406277 # number of overall hits +system.cpu0.icache.overall_hits::total 145342721 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844540 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855192 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699732 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844540 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855192 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699732 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844540 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855192 # number of overall misses +system.cpu0.icache.overall_misses::total 1699732 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74780984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261469 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74780984 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72261469 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74780984 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72261469 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011294 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011834 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011835 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011294 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011834 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011835 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011294 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011834 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011835 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -509,25 +509,25 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15530019 # DTB read hits -system.cpu1.dtb.read_misses 5412 # DTB read misses -system.cpu1.dtb.write_hits 11838449 # DTB write hits -system.cpu1.dtb.write_misses 791 # DTB write misses +system.cpu1.dtb.read_hits 15529940 # DTB read hits +system.cpu1.dtb.read_misses 5414 # DTB read misses +system.cpu1.dtb.write_hits 11838406 # DTB write hits +system.cpu1.dtb.write_misses 789 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 3183 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 909 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15535431 # DTB read accesses -system.cpu1.dtb.write_accesses 11839240 # DTB write accesses +system.cpu1.dtb.read_accesses 15535354 # DTB read accesses +system.cpu1.dtb.write_accesses 11839195 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368468 # DTB hits +system.cpu1.dtb.hits 27368346 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses -system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.dtb.accesses 27374549 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -557,26 +557,26 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3040 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 3041 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3041 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3041 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3041 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3041 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1721 81.53% 81.53% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.47% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2111 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3041 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3041 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72259450 # ITB inst hits -system.cpu1.itb.inst_misses 3040 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5152 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 72259358 # ITB inst hits +system.cpu1.itb.inst_misses 3041 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -585,45 +585,45 @@ system.cpu1.itb.flush_tlb 2817 # Nu system.cpu1.itb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2022 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72262490 # ITB inst accesses -system.cpu1.itb.hits 72259450 # DTB hits -system.cpu1.itb.misses 3040 # DTB misses -system.cpu1.itb.accesses 72262490 # DTB accesses -system.cpu1.numCycles 88040872 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72262399 # ITB inst accesses +system.cpu1.itb.hits 72259358 # DTB hits +system.cpu1.itb.misses 3041 # DTB misses +system.cpu1.itb.accesses 72262399 # DTB accesses +system.cpu1.numCycles 88040649 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70146598 # Number of instructions committed -system.cpu1.committedOps 85830973 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75676981 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6212 # Number of float alu accesses -system.cpu1.num_func_calls 8181424 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9272106 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75676981 # number of integer instructions -system.cpu1.num_fp_insts 6212 # number of float instructions -system.cpu1.num_int_register_reads 140994581 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52737823 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4658 # number of times the floating registers were read +system.cpu1.committedInsts 70146546 # Number of instructions committed +system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6228 # Number of float alu accesses +system.cpu1.num_func_calls 8181374 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9272054 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75676825 # number of integer instructions +system.cpu1.num_fp_insts 6228 # number of float instructions +system.cpu1.num_int_register_reads 140994115 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52737742 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4674 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1556 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261999475 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30539263 # number of times the CC registers were written -system.cpu1.num_mem_refs 28027673 # number of memory refs -system.cpu1.num_load_insts 15693775 # Number of load instructions -system.cpu1.num_store_insts 12333898 # Number of store instructions -system.cpu1.num_idle_cycles 85385179.520823 # Number of idle cycles -system.cpu1.num_busy_cycles 2655692.479177 # Number of busy cycles +system.cpu1.num_cc_register_reads 261998832 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30539220 # number of times the CC registers were written +system.cpu1.num_mem_refs 28027555 # number of memory refs +system.cpu1.num_load_insts 15693703 # Number of load instructions +system.cpu1.num_store_insts 12333852 # Number of store instructions +system.cpu1.num_idle_cycles 85384966.713327 # Number of idle cycles +system.cpu1.num_busy_cycles 2655682.286673 # Number of busy cycles system.cpu1.not_idle_fraction 0.030164 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969836 # Percentage of idle cycles -system.cpu1.Branches 17799968 # Number of branches fetched +system.cpu1.Branches 17799875 # Number of branches fetched system.cpu1.op_class::No_OpClass 148 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59388214 67.89% 67.89% # Class of executed instruction -system.cpu1.op_class::IntMult 57231 0.07% 67.96% # Class of executed instruction +system.cpu1.op_class::IntAlu 59388111 67.89% 67.89% # Class of executed instruction +system.cpu1.op_class::IntMult 57232 0.07% 67.96% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.96% # Class of executed instruction @@ -647,23 +647,23 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.96% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4163 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4166 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::MemRead 15693775 17.94% 85.90% # Class of executed instruction -system.cpu1.op_class::MemWrite 12333898 14.10% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15693703 17.94% 85.90% # Class of executed instruction +system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87477429 # Class of executed instruction +system.cpu1.op_class::total 87477212 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.iobus.trans_dist::ReadReq 30164 # Transaction distribution +system.iobus.trans_dist::ReadResp 30164 # Transaction distribution +system.iobus.trans_dist::WriteReq 59002 # Transaction distribution +system.iobus.trans_dist::WriteResp 22778 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -684,11 +684,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -709,17 +709,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -762,20 +762,20 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.309065 # Cycle average of tags in use -system.l2c.tags.total_refs 2731330 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.580712 # Average number of references to valid blocks. +system.l2c.tags.replacements 110020 # number of replacements +system.l2c.tags.tagsinuse 65155.309107 # Cycle average of tags in use +system.l2c.tags.total_refs 2731325 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175301 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 15.580772 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.434420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48893.438134 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.359026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.332054 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.354241 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.333214 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 4020.194257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.086185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.086137 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -795,143 +795,143 @@ system.l2c.tags.age_task_id_blocks_1024::3 10700 # system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26231923 # Number of tag accesses -system.l2c.tags.data_accesses 26231923 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4699 # number of ReadReq hits +system.l2c.tags.tag_accesses 26231874 # Number of tag accesses +system.l2c.tags.data_accesses 26231874 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833747 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5000 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847615 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 259132 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201281 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682284 # number of Writeback hits -system.l2c.Writeback_hits::total 682284 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 847646 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 259121 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201277 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682283 # number of Writeback hits +system.l2c.Writeback_hits::total 682283 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72504 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78554 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 72515 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78543 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 151058 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4699 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 4700 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 2287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833747 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 318852 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5000 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 318873 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5001 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847615 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337686 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352339 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4699 # number of overall hits +system.l2c.demand_hits::cpu1.inst 847646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337664 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352335 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4700 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 2287 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833747 # number of overall hits -system.l2c.overall_hits::cpu0.data 318852 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5000 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833711 # number of overall hits +system.l2c.overall_hits::cpu0.data 318873 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5001 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2453 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847615 # number of overall hits -system.l2c.overall_hits::cpu1.data 337686 # number of overall hits -system.l2c.overall_hits::total 2352339 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847646 # number of overall hits +system.l2c.overall_hits::cpu1.data 337664 # number of overall hits +system.l2c.overall_hits::total 2352335 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10820 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10819 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 9770 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 7538 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5759 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses +system.l2c.ReadReq_misses::total 33894 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83901 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63964 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83900 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10820 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73733 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10819 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73734 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 7538 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89660 # number of demand (read+write) misses -system.l2c.demand_misses::total 181759 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89659 # number of demand (read+write) misses +system.l2c.demand_misses::total 181758 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10820 # number of overall misses -system.l2c.overall_misses::cpu0.data 73733 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10819 # number of overall misses +system.l2c.overall_misses::cpu0.data 73734 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu1.inst 7538 # number of overall misses -system.l2c.overall_misses::cpu1.data 89660 # number of overall misses -system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4704 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 89659 # number of overall misses +system.l2c.overall_misses::total 181758 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4705 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844567 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256118 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5002 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256128 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855153 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264891 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2235176 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682284 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682284 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855184 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264880 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2235171 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682283 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682283 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136467 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162455 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 136479 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162443 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4704 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 4705 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 2288 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392585 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392607 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5003 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855153 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427346 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2534098 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4704 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855184 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427323 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2534093 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4705 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 2288 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392585 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392607 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5003 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855153 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427346 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2534098 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855184 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427323 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2534093 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.012811 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038145 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008815 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021741 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008814 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021742 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989699 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989960 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.468707 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.516457 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.468673 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.516489 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.012811 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187806 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209807 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209816 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071725 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.012811 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187806 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209807 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209816 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071725 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -941,14 +941,14 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101892 # number of writebacks -system.l2c.writebacks::total 101892 # number of writebacks +system.l2c.writebacks::writebacks 101891 # number of writebacks +system.l2c.writebacks::total 101891 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74229 # Transaction distribution -system.membus.trans_dist::ReadResp 74229 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 138082 # Transaction distribution +system.membus.trans_dist::ReadReq 74221 # Transaction distribution +system.membus.trans_dist::ReadResp 74221 # Transaction distribution +system.membus.trans_dist::WriteReq 27546 # Transaction distribution +system.membus.trans_dist::WriteResp 27546 # Transaction distribution +system.membus.trans_dist::Writeback 138081 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -956,34 +956,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606133 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715296 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 715251 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258521 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22908547 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359035 # Request fanout histogram +system.membus.snoop_fanout::samples 359033 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359035 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359033 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359035 # Request fanout histogram +system.membus.snoop_fanout::total 359033 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1015,41 +1015,39 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2291995 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291995 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682284 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2291984 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682283 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924754 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324555 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205268491 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444881 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924703 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324385 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272329 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011143 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3272324 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011143 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235865 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3235860 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36464 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272329 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272324 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 83b8a4ab7..b412f009d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.177080 # Number of seconds simulated -sim_ticks 47177080006500 # Number of ticks simulated -final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.216814 # Number of seconds simulated +sim_ticks 47216814145000 # Number of ticks simulated +final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1049876 # Simulator instruction rate (inst/s) -host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50706899360 # Simulator tick rate (ticks/s) -host_mem_usage 670076 # Number of bytes of host memory used -host_seconds 930.39 # Real time elapsed on the host -sim_insts 976792036 # Number of instructions simulated -sim_ops 1149086878 # Number of ops (including micro ops) simulated +host_inst_rate 1225013 # Simulator instruction rate (inst/s) +host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59296512316 # Simulator tick rate (ticks/s) +host_mem_usage 723320 # Number of bytes of host memory used +host_seconds 796.28 # Real time elapsed on the host +sim_insts 975457230 # Number of instructions simulated +sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 149696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 124032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3867700 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35125336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 224640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 222848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2692808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38798848 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 404992 # Number of bytes read from this memory -system.physmem.bytes_read::total 81610900 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3867700 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2692808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 100759808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory +system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 100780624 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2339 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1938 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 100840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 548855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3482 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 42182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 606250 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6328 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315724 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1574372 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1576975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 744542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 57079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 822409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1729885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 57079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 139061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2135779 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2136220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2135779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 744984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 57079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 822409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3866105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -134,45 +134,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 123914 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 125229 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91355479 # DTB read hits -system.cpu0.dtb.read_misses 87819 # DTB read misses -system.cpu0.dtb.write_hits 84601943 # DTB write hits -system.cpu0.dtb.write_misses 36095 # DTB write misses +system.cpu0.dtb.read_hits 92662773 # DTB read hits +system.cpu0.dtb.read_misses 88786 # DTB read misses +system.cpu0.dtb.write_hits 85694958 # DTB write hits +system.cpu0.dtb.write_misses 36443 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36260 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5461 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10344 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91443298 # DTB read accesses -system.cpu0.dtb.write_accesses 84638038 # DTB write accesses +system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92751559 # DTB read accesses +system.cpu0.dtb.write_accesses 85731401 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175957422 # DTB hits -system.cpu0.dtb.misses 123914 # DTB misses -system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.dtb.hits 178357731 # DTB hits +system.cpu0.dtb.misses 125229 # DTB misses +system.cpu0.dtb.accesses 178482960 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,187 +202,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 60226 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 61377 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 491372488 # ITB inst hits -system.cpu0.itb.inst_misses 60226 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 497696393 # ITB inst hits +system.cpu0.itb.inst_misses 61377 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25015 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 491432714 # ITB inst accesses -system.cpu0.itb.hits 491372488 # DTB hits -system.cpu0.itb.misses 60226 # DTB misses -system.cpu0.itb.accesses 491432714 # DTB accesses -system.cpu0.numCycles 94354173207 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses +system.cpu0.itb.hits 497696393 # DTB hits +system.cpu0.itb.misses 61377 # DTB misses +system.cpu0.itb.accesses 497757770 # DTB accesses +system.cpu0.numCycles 94433641544 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 491139120 # Number of instructions committed -system.cpu0.committedOps 577575160 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 529301791 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 523058 # Number of float alu accesses -system.cpu0.num_func_calls 28573576 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75495865 # number of instructions that are conditional controls -system.cpu0.num_int_insts 529301791 # number of integer instructions -system.cpu0.num_fp_insts 523058 # number of float instructions -system.cpu0.num_int_register_reads 775565033 # number of times the integer registers were read -system.cpu0.num_int_register_writes 419986522 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 843711 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 444676 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132153354 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 131825344 # number of times the CC registers were written -system.cpu0.num_mem_refs 176058068 # number of memory refs -system.cpu0.num_load_insts 91428761 # Number of load instructions -system.cpu0.num_store_insts 84629307 # Number of store instructions -system.cpu0.num_idle_cycles 93776262262.183929 # Number of idle cycles -system.cpu0.num_busy_cycles 577910944.816068 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006125 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993875 # Percentage of idle cycles -system.cpu0.Branches 109891880 # Number of branches fetched +system.cpu0.committedInsts 497466384 # Number of instructions committed +system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses +system.cpu0.num_func_calls 28869117 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls +system.cpu0.num_int_insts 536103359 # number of integer instructions +system.cpu0.num_fp_insts 526132 # number of float instructions +system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read +system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written +system.cpu0.num_mem_refs 178459396 # number of memory refs +system.cpu0.num_load_insts 92737001 # Number of load instructions +system.cpu0.num_store_insts 85722395 # Number of store instructions +system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles +system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles +system.cpu0.Branches 111287587 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 400497126 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1218559 0.21% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 59561 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 73140 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 91428761 15.82% 85.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 84629307 14.64% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction +system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction +system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction +system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 577906497 # Class of executed instruction +system.cpu0.op_class::total 585300003 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13193 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 6189405 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.263112 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169698310 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6189917 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.415280 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 6272759 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 172015744 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6273271 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.263112 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988795 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988795 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 358274198 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 358274198 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 84971856 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 84971856 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79868150 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79868150 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214674 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 214674 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 260533 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 260533 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2068908 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2068908 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028668 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2028668 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164840006 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164840006 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165054680 # number of overall hits -system.cpu0.dcache.overall_hits::total 165054680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3260277 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3260277 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1458399 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1458399 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 767112 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 767112 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 819206 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 819206 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 116959 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 116959 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156094 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 156094 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4718676 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4718676 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5485788 # number of overall misses -system.cpu0.dcache.overall_misses::total 5485788 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88232133 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88232133 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81326549 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81326549 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 981786 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 981786 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079739 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079739 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185867 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2185867 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2184762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169558682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169558682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170540468 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170540468 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036951 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036951 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017933 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017933 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.758707 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.758707 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053507 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053507 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071447 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071447 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027829 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027829 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032167 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032167 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 363162158 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 363162158 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86214905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86214905 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80919887 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80919887 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215655 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036774 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2036774 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 167134792 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 167134792 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167350447 # number of overall hits +system.cpu0.dcache.overall_hits::total 167350447 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3309378 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3309378 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1475526 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1475526 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772138 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 772138 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158369 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 158369 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4784904 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4784904 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5557042 # number of overall misses +system.cpu0.dcache.overall_misses::total 5557042 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89524283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395413 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82395413 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 171919696 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 171919696 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 172907489 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 172907489 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017908 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017908 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072145 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072145 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027832 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027832 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,50 +391,50 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4407988 # number of writebacks -system.cpu0.dcache.writebacks::total 4407988 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks +system.cpu0.dcache.writebacks::total 4469723 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5467768 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 485959047 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5468280 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.868721 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 5539081 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 988322949 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 988322949 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 485959047 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 485959047 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 485959047 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 485959047 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 485959047 # number of overall hits -system.cpu0.icache.overall_hits::total 485959047 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5468285 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5468285 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5468285 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5468285 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5468285 # number of overall misses -system.cpu0.icache.overall_misses::total 5468285 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 491427332 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 491427332 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 491427332 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 491427332 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 491427332 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 491427332 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011127 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011127 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011127 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011127 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011127 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011127 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits +system.cpu0.icache.overall_hits::total 492212891 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses +system.cpu0.icache.overall_misses::total 5539598 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,132 +450,132 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2648971 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2665005 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.283598 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2710840 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5428.449185 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.127041 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.911966 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4608.843039 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 6080.573004 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.331326 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003060 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003168 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.281301 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.371129 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989984 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15969 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 5735.641953 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.550576 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.046098 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4528.763909 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5835.841004 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.350076 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003268 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003360 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276414 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.356191 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989309 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15944 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 50 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1130 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4626 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4547 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.974670 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 274915962 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 274915962 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 266204 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 139155 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4917807 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2910870 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 8234036 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4407988 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4407988 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 219663 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 219663 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3562 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 3562 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630387 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 630387 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 266204 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 139155 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4917807 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3541257 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8864423 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 266204 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 139155 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4917807 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3541257 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8864423 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10959 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8288 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 550478 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1233478 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1803203 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 599179 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 599179 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 125865 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 125865 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156094 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 156094 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 698949 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 698949 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10959 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8288 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 550478 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1932427 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2502152 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10959 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8288 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 550478 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1932427 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2502152 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277163 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 147443 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5468285 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4144348 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 10037239 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4407988 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4407988 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 818842 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 818842 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 129427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 129427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156094 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 156094 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1329336 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1329336 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277163 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 147443 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5468285 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5473684 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11366575 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277163 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 147443 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5468285 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5473684 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11366575 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056212 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.100667 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.297629 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.179651 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731739 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731739 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.972479 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.972479 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1162 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4591 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5299 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4659 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973145 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 278654950 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 278654950 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 269350 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 141753 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971397 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944075 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 8326575 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4469723 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4469723 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222737 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 222737 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3521 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 3521 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634814 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 634814 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 269350 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 141753 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4971397 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3578889 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8961389 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 269350 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 141753 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4971397 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3578889 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8961389 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11316 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8593 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 568201 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257257 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1845367 # number of ReadReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608598 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 608598 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128143 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 128143 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158369 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709409 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 709409 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11316 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8593 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 568201 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2554776 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11316 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8593 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 568201 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 280666 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150346 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539598 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4469723 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 280666 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 280666 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150346 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525788 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525788 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056212 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100667 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.353040 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.220132 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056212 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100667 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.353040 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.220132 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,47 +584,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1542533 # number of writebacks -system.cpu0.l2cache.writebacks::total 1542533 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks +system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 10228504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10228504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4407988 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 818842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 818842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 129427 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 285521 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1329336 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1329336 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11022820 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17694214 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 359792 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 720614 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 29797440 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350142740 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 685026670 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2882456 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1039491034 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3383860 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20196192 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.158528 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.365236 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 16994523 84.15% 84.15% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 3201669 15.85% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -654,45 +652,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 144852 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 144041 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91720002 # DTB read hits -system.cpu1.dtb.read_misses 112244 # DTB read misses -system.cpu1.dtb.write_hits 82499013 # DTB write hits -system.cpu1.dtb.write_misses 32608 # DTB write misses +system.cpu1.dtb.read_hits 90153061 # DTB read hits +system.cpu1.dtb.read_misses 111753 # DTB read misses +system.cpu1.dtb.write_hits 81132787 # DTB write hits +system.cpu1.dtb.write_misses 32288 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 45118 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4542 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11534 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91832246 # DTB read accesses -system.cpu1.dtb.write_accesses 82531621 # DTB write accesses +system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90264814 # DTB read accesses +system.cpu1.dtb.write_accesses 81165075 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 174219015 # DTB hits -system.cpu1.dtb.misses 144852 # DTB misses -system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.dtb.hits 171285848 # DTB hits +system.cpu1.dtb.misses 144041 # DTB misses +system.cpu1.dtb.accesses 171429889 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -722,186 +720,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 61939 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 60885 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 485906850 # ITB inst hits -system.cpu1.itb.inst_misses 61939 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 478248118 # ITB inst hits +system.cpu1.itb.inst_misses 60885 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31863 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 485968789 # ITB inst accesses -system.cpu1.itb.hits 485906850 # DTB hits -system.cpu1.itb.misses 61939 # DTB misses -system.cpu1.itb.accesses 485968789 # DTB accesses -system.cpu1.numCycles 94354166192 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses +system.cpu1.itb.hits 478248118 # DTB hits +system.cpu1.itb.misses 60885 # DTB misses +system.cpu1.itb.accesses 478309003 # DTB accesses +system.cpu1.numCycles 94433634550 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 485652916 # Number of instructions committed -system.cpu1.committedOps 571511718 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 524558211 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 375128 # Number of float alu accesses -system.cpu1.num_func_calls 28666071 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 74347572 # number of instructions that are conditional controls -system.cpu1.num_int_insts 524558211 # number of integer instructions -system.cpu1.num_fp_insts 375128 # number of float instructions -system.cpu1.num_int_register_reads 774388464 # number of times the integer registers were read -system.cpu1.num_int_register_writes 417530639 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 610571 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 303256 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 128278137 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 127991607 # number of times the CC registers were written -system.cpu1.num_mem_refs 174340371 # number of memory refs -system.cpu1.num_load_insts 91819242 # Number of load instructions -system.cpu1.num_store_insts 82521129 # Number of store instructions -system.cpu1.num_idle_cycles 93782340058.888657 # Number of idle cycles -system.cpu1.num_busy_cycles 571826133.111340 # Number of busy cycles -system.cpu1.not_idle_fraction 0.006060 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.993940 # Percentage of idle cycles -system.cpu1.Branches 108195111 # Number of branches fetched +system.cpu1.committedInsts 477990846 # Number of instructions committed +system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses +system.cpu1.num_func_calls 28237407 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls +system.cpu1.num_int_insts 516282159 # number of integer instructions +system.cpu1.num_fp_insts 374678 # number of float instructions +system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read +system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written +system.cpu1.num_mem_refs 171406825 # number of memory refs +system.cpu1.num_load_insts 90251973 # Number of load instructions +system.cpu1.num_store_insts 81154852 # Number of store instructions +system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles +system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles +system.cpu1.Branches 106497601 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 396230726 69.29% 69.29% # Class of executed instruction -system.cpu1.op_class::IntMult 1151823 0.20% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 61886 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 36426 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 91819242 16.06% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 82521129 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction +system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction +system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 571821232 # Class of executed instruction +system.cpu1.op_class::total 562879339 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6178 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 6025220 # number of replacements -system.cpu1.dcache.tags.tagsinuse 443.938244 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 168203685 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6025731 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.914237 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5945049 # number of replacements +system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.938244 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867067 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.867067 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 354758936 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 354758936 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 85201700 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 85201700 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 78314445 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 78314445 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188411 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 188411 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 65692 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 65692 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2073864 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2073864 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2064069 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2064069 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 163516145 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 163516145 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 163704556 # number of overall hits -system.cpu1.dcache.overall_hits::total 163704556 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3403274 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3403274 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1467363 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1467363 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 796168 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 796168 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 438523 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 438523 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 149383 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 149383 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157982 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 157982 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4870637 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4870637 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5666805 # number of overall misses -system.cpu1.dcache.overall_misses::total 5666805 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 88604974 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 88604974 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 79781808 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 79781808 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 984579 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 984579 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 504215 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 504215 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2223247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2223247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2222051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2222051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 168386782 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 168386782 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 169371361 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 169371361 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038410 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038410 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018392 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018392 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808638 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808638 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.869714 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.869714 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067191 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067191 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071097 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071097 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028925 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028925 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033458 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033458 # miss rate for overall accesses +system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits +system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses +system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -910,49 +909,49 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4091318 # number of writebacks -system.cpu1.dcache.writebacks::total 4091318 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks +system.cpu1.dcache.writebacks::total 4030826 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4818195 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.412963 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 481143593 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4818707 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.849107 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 4741297 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412963 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 976743307 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 976743307 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 481143593 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 481143593 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 481143593 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 481143593 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 481143593 # number of overall hits -system.cpu1.icache.overall_hits::total 481143593 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4818707 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4818707 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4818707 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4818707 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4818707 # number of overall misses -system.cpu1.icache.overall_misses::total 4818707 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 485962300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 485962300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 485962300 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 485962300 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 485962300 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 485962300 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits +system.cpu1.icache.overall_hits::total 473560604 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses +system.cpu1.icache.overall_misses::total 4741809 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -968,133 +967,132 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2333825 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2349876 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.683889 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9726491548000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5253.379361 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.604678 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.064726 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2656.476360 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5431.499219 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.320641 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004582 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.162138 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.331512 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15948 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1580 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5821 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4453 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4016 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973389 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 257480243 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 257480243 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 323221 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141798 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4279723 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3095607 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7840349 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 4091318 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 4091318 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 167179 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 167179 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3859 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 3859 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 621347 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 621347 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 323221 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141798 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4279723 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3716954 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8461696 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 323221 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141798 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4279723 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3716954 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8461696 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12537 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9802 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 538984 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1253218 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1814541 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271117 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 271117 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133664 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 133664 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157982 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 157982 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708720 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 708720 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12537 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9802 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 538984 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1961938 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2523261 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12537 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9802 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 538984 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1961938 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2523261 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 335758 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 151600 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4818707 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4348825 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9654890 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 4091318 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 4091318 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 438296 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 438296 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137523 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 137523 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157982 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 157982 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1330067 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1330067 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 335758 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 151600 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4818707 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5678892 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10984957 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 335758 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 151600 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4818707 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5678892 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10984957 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064657 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.111852 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288174 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.187940 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.618571 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.618571 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971939 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971939 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.tags.replacements 2278914 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13451.937852 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10861278 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.732680 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5180.760257 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2828.453932 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.316209 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004177 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005597 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.172635 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322423 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.821041 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 254019378 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 325118 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141158 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4217165 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 3057891 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 7741332 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 4030826 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 4030826 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161366 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 161366 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3865 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 3865 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614191 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 614191 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 325118 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141158 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4217165 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3672082 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8355523 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 325118 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141158 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4217165 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3672082 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8355523 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12489 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9780 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 524644 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239502 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1786415 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265480 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 265480 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133591 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 133591 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158842 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 158842 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701699 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 701699 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12489 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9780 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 524644 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1941201 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2488114 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12489 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9780 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 524644 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1941201 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2488114 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337607 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150938 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 9527747 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 4030826 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150938 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532845 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532845 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064657 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111852 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345479 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.229701 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064657 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111852 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345479 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.229701 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1103,53 +1101,51 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1212706 # number of writebacks -system.cpu1.l2cache.writebacks::total 1212706 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks +system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 9779239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9779239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4091318 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 438296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 438296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 137523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 295505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1330067 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1330067 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9637674 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16942172 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370292 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 840154 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27790292 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 308397768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 653382681 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1481168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3360616 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 966622233 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 3659793 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19426876 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.180108 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.384277 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15927941 81.99% 81.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 3498935 18.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19426876 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40346 # Transaction distribution -system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136741 # Transaction distribution -system.iobus.trans_dist::WriteResp 30013 # Transaction distribution +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40295 # Transaction distribution +system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::WriteReq 136634 # Transaction distribution +system.iobus.trans_dist::WriteResp 29906 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1164,13 +1160,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122884 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354174 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47970 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1185,54 +1181,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155991 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496933 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115586 # number of replacements -system.iocache.tags.tagsinuse 11.286927 # Cycle average of tags in use +system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115585 # number of replacements +system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115602 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.855232 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.431695 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240952 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464481 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705433 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040802 # Number of tag accesses -system.iocache.tags.data_accesses 1040802 # Number of data accesses +system.iocache.tags.tag_accesses 1040793 # Number of tag accesses +system.iocache.tags.data_accesses 1040793 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses -system.iocache.demand_misses::total 8917 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses +system.iocache.demand_misses::total 8916 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8877 # number of overall misses -system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.overall_misses::realview.ide 8876 # number of overall misses +system.iocache.overall_misses::total 8916 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1257,205 +1253,205 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1764050 # number of replacements -system.l2c.tags.tagsinuse 62893.103184 # Cycle average of tags in use -system.l2c.tags.total_refs 3693923 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1823047 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.026236 # Average number of references to valid blocks. +system.l2c.tags.replacements 1759966 # number of replacements +system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use +system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35252.715261 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 32.297168 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 36.889266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3199.431904 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6870.253722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 308.072507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 447.332489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2890.642136 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13855.468731 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.537914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000493 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000563 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048819 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.104832 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006826 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.211418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.959673 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 209 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 58788 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 35219.340736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 46.907098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 57.886687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13514.968494 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.537404 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000716 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.106280 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006565 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.206222 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.958896 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58508 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3602 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49009 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003189 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.897034 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 66315846 # Number of tag accesses -system.l2c.tags.data_accesses 66315846 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4325 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 492739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 723130 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3764 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 496903 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 707011 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2439522 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2755239 # number of Writeback hits -system.l2c.Writeback_hits::total 2755239 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 115462 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 102925 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 218387 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 13978 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24721 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1494 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1282 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2776 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 196550 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 177871 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 374421 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5920 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4325 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 492739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 919680 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 496903 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 884882 # number of demand (read+write) hits -system.l2c.demand_hits::total 2813943 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5920 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4325 # number of overall hits -system.l2c.overall_hits::cpu0.inst 492739 # number of overall hits -system.l2c.overall_hits::cpu0.data 919680 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5730 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3764 # number of overall hits -system.l2c.overall_hits::cpu1.inst 496903 # number of overall hits -system.l2c.overall_hits::cpu1.data 884882 # number of overall hits -system.l2c.overall_hits::total 2813943 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2339 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1938 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 57739 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 182657 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3510 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 3482 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 42081 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 192722 # number of ReadReq misses -system.l2c.ReadReq_misses::total 486468 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 475939 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 161383 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 637322 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 57732 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 55051 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 112783 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7557 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7409 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 14966 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 376574 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 420815 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 797389 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2339 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1938 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 57739 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 559231 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3510 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3482 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 42081 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 613537 # number of demand (read+write) misses -system.l2c.demand_misses::total 1283857 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2339 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1938 # number of overall misses -system.l2c.overall_misses::cpu0.inst 57739 # number of overall misses -system.l2c.overall_misses::cpu0.data 559231 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3510 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3482 # number of overall misses -system.l2c.overall_misses::cpu1.inst 42081 # number of overall misses -system.l2c.overall_misses::cpu1.data 613537 # number of overall misses -system.l2c.overall_misses::total 1283857 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8259 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6263 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 550478 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 905787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9240 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 538984 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 899733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2925990 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2755239 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2755239 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 591401 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 264308 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 855709 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 71710 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 65794 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 137504 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9051 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8691 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17742 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 573124 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 598686 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1171810 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8259 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6263 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 550478 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1478911 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7246 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 538984 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1498419 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4097800 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8259 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6263 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 550478 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1478911 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7246 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 538984 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1498419 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4097800 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309436 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.104889 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.201656 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.480541 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.078075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.214199 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.166258 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.804765 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.610587 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.744788 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805076 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836718 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.820216 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.834935 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.852491 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.843535 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.657055 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.702898 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680476 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.309436 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.104889 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.378137 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.480541 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.078075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.409456 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.313304 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.309436 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.104889 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.378137 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.480541 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.078075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.409456 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.313304 # miss rate for overall accesses +system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 549 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3406 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48840 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.892761 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 66406004 # Number of tag accesses +system.l2c.tags.data_accesses 66406004 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6334 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4677 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 509782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 744386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3610 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 483417 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 692017 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2449792 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2756939 # number of Writeback hits +system.l2c.Writeback_hits::total 2756939 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 121538 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 97977 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 219515 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 13827 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10932 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24759 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1566 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1304 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2870 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 202688 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 171255 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 373943 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6334 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4677 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 509782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 947074 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3610 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 483417 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 863272 # number of demand (read+write) hits +system.l2c.demand_hits::total 2823735 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6334 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4677 # number of overall hits +system.l2c.overall_hits::cpu0.inst 509782 # number of overall hits +system.l2c.overall_hits::cpu0.data 947074 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5569 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3610 # number of overall hits +system.l2c.overall_hits::cpu1.inst 483417 # number of overall hits +system.l2c.overall_hits::cpu1.data 863272 # number of overall hits +system.l2c.overall_hits::total 2823735 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2407 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 58419 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 184134 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3483 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 3456 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 41227 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 189746 # number of ReadReq misses +system.l2c.ReadReq_misses::total 484883 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 479213 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 160846 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 640059 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 58018 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 53853 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 111871 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 7722 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7423 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 15145 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 377543 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 418309 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 795852 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2407 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 58419 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 561677 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3483 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3456 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41227 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 608055 # number of demand (read+write) misses +system.l2c.demand_misses::total 1280735 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2407 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses +system.l2c.overall_misses::cpu0.inst 58419 # number of overall misses +system.l2c.overall_misses::cpu0.data 561677 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3483 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3456 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41227 # number of overall misses +system.l2c.overall_misses::cpu1.data 608055 # number of overall misses +system.l2c.overall_misses::total 1280735 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8741 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6688 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 568201 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 928520 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9052 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7066 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 524644 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 881763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2934675 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2756939 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2756939 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 600751 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 258823 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 859574 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 71845 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 64785 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 136630 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9288 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8727 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18015 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 580231 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 589564 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1169795 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6688 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 568201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1508751 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7066 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 524644 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1471327 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4104470 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6688 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 568201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1508751 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7066 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 524644 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1471327 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4104470 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.300688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.102814 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.198309 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.489103 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.078581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.215189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.165225 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.797690 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.621452 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.744623 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807544 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831257 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.831395 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850579 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.840688 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.650677 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.709523 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680335 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.300688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.102814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.372279 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.489103 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.078581 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.413270 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.312034 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.300688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.102814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.372279 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.489103 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.078581 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.413270 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.312034 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1464,49 +1460,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1467678 # number of writebacks -system.l2c.writebacks::total 1467678 # number of writebacks +system.l2c.writebacks::writebacks 1464604 # number of writebacks +system.l2c.writebacks::total 1464604 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 577534 # Transaction distribution -system.membus.trans_dist::ReadResp 577534 # Transaction distribution -system.membus.trans_dist::WriteReq 38903 # Transaction distribution -system.membus.trans_dist::WriteResp 38903 # Transaction distribution -system.membus.trans_dist::Writeback 1574372 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 739425 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 739425 # Transaction distribution -system.membus.trans_dist::UpgradeReq 325897 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 311300 # Transaction distribution -system.membus.trans_dist::UpgradeResp 149445 # Transaction distribution -system.membus.trans_dist::ReadExReq 961374 # Transaction distribution -system.membus.trans_dist::ReadExResp 780321 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122884 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 575939 # Transaction distribution +system.membus.trans_dist::ReadResp 575939 # Transaction distribution +system.membus.trans_dist::WriteReq 38831 # Transaction distribution +system.membus.trans_dist::WriteResp 38831 # Transaction distribution +system.membus.trans_dist::Writeback 1571298 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution +system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution +system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution +system.membus.trans_dist::ReadExReq 965776 # Transaction distribution +system.membus.trans_dist::ReadExResp 778482 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27406 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6326067 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6476449 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337984 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337984 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6814433 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155991 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215692580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 215903587 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14229504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 230133091 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4407750 # Request fanout histogram +system.membus.snoop_fanout::samples 4414869 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4407750 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4407750 # Request fanout histogram +system.membus.snoop_fanout::total 4414869 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1549,35 +1545,35 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 3699896 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3699896 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38903 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38903 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2755239 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 855709 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 855709 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 328922 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 314076 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 642998 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1352863 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1352863 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8525495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7410482 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15935977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295216066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 254408545 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 549624611 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 117315 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9340198 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012381 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110581 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 117306 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9224553 98.76% 98.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115645 1.24% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9340198 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 70b8700c6..b381100ef 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111151 # Number of seconds simulated -sim_ticks 51111150553500 # Number of ticks simulated -final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111153 # Number of seconds simulated +sim_ticks 51111152682000 # Number of ticks simulated +final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1336104 # Simulator instruction rate (inst/s) -host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69344550867 # Simulator tick rate (ticks/s) -host_mem_usage 712616 # Number of bytes of host memory used -host_seconds 737.06 # Real time elapsed on the host -sim_insts 984789519 # Number of instructions simulated -sim_ops 1157289961 # Number of ops (including micro ops) simulated +host_inst_rate 1276359 # Simulator instruction rate (inst/s) +host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66258489115 # Simulator tick rate (ticks/s) +host_mem_usage 712024 # Number of bytes of host memory used +host_seconds 771.39 # Real time elapsed on the host +sim_insts 984570519 # Number of instructions simulated +sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 411136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 373504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5556020 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 75320200 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 82098556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5556020 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5556020 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 127220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1176891 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1323210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 108705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1473655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1606275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020647 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1474058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3627324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -103,45 +103,45 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 265618 # Table walker walks requested -system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 265715 # Table walker walks requested +system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184057973 # DTB read hits -system.cpu.dtb.read_misses 194269 # DTB read misses -system.cpu.dtb.write_hits 168276300 # DTB write hits -system.cpu.dtb.write_misses 71349 # DTB write misses +system.cpu.dtb.read_hits 184014035 # DTB read hits +system.cpu.dtb.read_misses 194198 # DTB read misses +system.cpu.dtb.write_hits 168232768 # DTB write hits +system.cpu.dtb.write_misses 71517 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 81439 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9105 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184252242 # DTB read accesses -system.cpu.dtb.write_accesses 168347649 # DTB write accesses +system.cpu.dtb.read_accesses 184208233 # DTB read accesses +system.cpu.dtb.write_accesses 168304285 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 352334273 # DTB hits -system.cpu.dtb.misses 265618 # DTB misses -system.cpu.dtb.accesses 352599891 # DTB accesses +system.cpu.dtb.hits 352246803 # DTB hits +system.cpu.dtb.misses 265715 # DTB misses +system.cpu.dtb.accesses 352512518 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -171,26 +171,26 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 126829 # Table walker walks requested -system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 126837 # Table walker walks requested +system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 985266544 # ITB inst hits -system.cpu.itb.inst_misses 126829 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 985047321 # ITB inst hits +system.cpu.itb.inst_misses 126837 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -199,46 +199,46 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57079 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 985393373 # ITB inst accesses -system.cpu.itb.hits 985266544 # DTB hits -system.cpu.itb.misses 126829 # DTB misses -system.cpu.itb.accesses 985393373 # DTB accesses -system.cpu.numCycles 102222317883 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 985174158 # ITB inst accesses +system.cpu.itb.hits 985047321 # DTB hits +system.cpu.itb.misses 126837 # DTB misses +system.cpu.itb.accesses 985174158 # DTB accesses +system.cpu.numCycles 102222322140 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 984789519 # Number of instructions committed -system.cpu.committedOps 1157289961 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1060698532 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 880773 # Number of float alu accesses -system.cpu.num_func_calls 57075493 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151966445 # number of instructions that are conditional controls -system.cpu.num_int_insts 1060698532 # number of integer instructions -system.cpu.num_fp_insts 880773 # number of float instructions -system.cpu.num_int_register_reads 1564314393 # number of times the integer registers were read -system.cpu.num_int_register_writes 842633326 # number of times the integer registers were written +system.cpu.committedInsts 984570519 # Number of instructions committed +system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses +system.cpu.num_func_calls 57056367 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls +system.cpu.num_int_insts 1060455466 # number of integer instructions +system.cpu.num_fp_insts 880805 # number of float instructions +system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read +system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read -system.cpu.num_fp_register_writes 747792 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264443211 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263865511 # number of times the CC registers were written -system.cpu.num_mem_refs 352552781 # number of memory refs -system.cpu.num_load_insts 184224242 # Number of load instructions -system.cpu.num_store_insts 168328539 # Number of store instructions -system.cpu.num_idle_cycles 101064381138.333679 # Number of idle cycles -system.cpu.num_busy_cycles 1157936744.666323 # Number of busy cycles -system.cpu.not_idle_fraction 0.011328 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988672 # Percentage of idle cycles -system.cpu.Branches 220135160 # Number of branches fetched +system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written +system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written +system.cpu.num_mem_refs 352465606 # number of memory refs +system.cpu.num_load_insts 184180431 # Number of load instructions +system.cpu.num_store_insts 168285175 # Number of store instructions +system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles +system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles +system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.988675 # Percentage of idle cycles +system.cpu.Branches 220088562 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 802806903 69.33% 69.33% # Class of executed instruction -system.cpu.op_class::IntMult 2355402 0.20% 69.53% # Class of executed instruction -system.cpu.op_class::IntDiv 101851 0.01% 69.54% # Class of executed instruction +system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction +system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction @@ -265,93 +265,93 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::MemRead 184224242 15.91% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 168328539 14.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction +system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1157924802 # Class of executed instruction +system.cpu.op_class::total 1157666593 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 11615783 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 340859576 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.343227 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 11612141 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999718 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1421519854 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1421519854 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 171606610 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171606610 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159566138 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159566138 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424146 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424146 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337798 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310377 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4310377 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4563246 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 331172748 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 331172748 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 331596894 # number of overall hits -system.cpu.dcache.overall_hits::total 331596894 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6013361 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6013361 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2569466 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2569466 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1584813 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1584813 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245259 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 254671 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 254671 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits +system.cpu.dcache.overall_hits::total 331514149 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8582827 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8582827 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10167640 # number of overall misses -system.cpu.dcache.overall_misses::total 10167640 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177619971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 162135604 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008959 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2008959 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 339755575 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 341764534 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 341764534 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033855 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015848 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788873 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788873 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses +system.cpu.dcache.overall_misses::total 10164734 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029750 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,49 +360,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8923646 # number of writebacks -system.cpu.dcache.writebacks::total 8923646 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks +system.cpu.dcache.writebacks::total 8921315 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 14287218 # number of replacements +system.cpu.icache.tags.replacements 14295641 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 971093500 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 999668970 # Number of tag accesses -system.cpu.icache.tags.data_accesses 999668970 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 971093500 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 971093500 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 971093500 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 971093500 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 971093500 # number of overall hits -system.cpu.icache.overall_hits::total 971093500 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14287735 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14287735 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14287735 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14287735 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14287735 # number of overall misses -system.cpu.icache.overall_misses::total 14287735 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 985381235 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 985381235 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 985381235 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014500 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014500 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014500 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses +system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits +system.cpu.icache.overall_hits::total 970865862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses +system.cpu.icache.overall_misses::total 14296158 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,130 +412,129 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1726949 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65261.456081 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29978708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1789688 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 16.750801 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1722692 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37844.065183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 274.121350 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 368.710071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6273.950851 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20500.608627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.577455 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004183 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095733 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.312814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953537 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 290358067 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 290358067 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 511193 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 258912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14203603 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7508372 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22482080 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8923646 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8923646 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 697316 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 697316 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11232 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11232 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1684603 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1684603 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 511193 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 258912 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14203603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9192975 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24166683 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 511193 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 258912 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14203603 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9192975 # number of overall hits -system.cpu.l2cache.overall_hits::total 24166683 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6424 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5836 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84132 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 344473 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 440865 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 547943 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 547943 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 40028 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 40028 # number of UpgradeReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.323257 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961594 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 14211921 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7504232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 22478388 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694333 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 694333 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 255623 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14211921 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9196842 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24170998 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits +system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5883 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 84237 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 440529 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 833603 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 833603 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6424 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5836 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84132 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1178076 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1274468 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6424 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5836 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84132 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1178076 # number of overall misses -system.cpu.l2cache.overall_misses::total 1274468 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 517617 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 264748 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14287735 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7852845 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22922945 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8923646 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8923646 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245259 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245259 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51260 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 51260 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses +system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2518206 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2518206 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 517617 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 264748 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14287735 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10371051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25441151 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 517617 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 264748 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14287735 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10371051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25441151 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012411 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022044 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043866 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019232 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.440023 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.440023 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780882 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780882 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.331031 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012411 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022044 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005888 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.113593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.050095 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012411 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022044 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005888 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.113593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.050095 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,53 +543,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1507081 # number of writebacks -system.cpu.l2cache.writebacks::total 1507081 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks +system.cpu.l2cache.writebacks::total 1503415 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23368238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23368238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28661720 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32393426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 63356998 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6174720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2238542120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 116335 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 36145396 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.056442 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 116338 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 36029878 99.68% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 36145396 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40296 # Transaction distribution -system.iobus.trans_dist::ReadResp 40296 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40246 # Transaction distribution +system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.iobus.trans_dist::WriteReq 136515 # Transaction distribution +system.iobus.trans_dist::WriteResp 29851 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -605,13 +602,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -626,54 +623,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115460 # number of replacements +system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115463 # number of replacements system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses -system.iocache.demand_misses::total 8854 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8814 # number of overall misses -system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -698,46 +695,46 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526448 # Transaction distribution -system.membus.trans_dist::ReadResp 526448 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1613712 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 654602 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 654602 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40596 # Transaction distribution +system.membus.trans_dist::ReadReq 526062 # Transaction distribution +system.membus.trans_dist::ReadResp 526062 # Transaction distribution +system.membus.trans_dist::WriteReq 33606 # Transaction distribution +system.membus.trans_dist::WriteResp 33606 # Transaction distribution +system.membus.trans_dist::Writeback 1610046 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40597 # Transaction distribution -system.membus.trans_dist::ReadExReq 833043 # Transaction distribution -system.membus.trans_dist::ReadExResp 833043 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution +system.membus.trans_dist::ReadExReq 825948 # Transaction distribution +system.membus.trans_dist::ReadExResp 825948 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5323339 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5452849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5790516 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213244448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213413816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227631160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3591670 # Request fanout histogram +system.membus.snoop_fanout::samples 3583537 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3591670 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3591670 # Request fanout histogram +system.membus.snoop_fanout::total 3583537 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index cd0cb8f17..fb0fbc4a7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.410782 # Number of seconds simulated -sim_ticks 47410781652000 # Number of ticks simulated -final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.367818 # Number of seconds simulated +sim_ticks 47367817574000 # Number of ticks simulated +final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787433 # Simulator instruction rate (inst/s) -host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41969003911 # Simulator tick rate (ticks/s) -host_mem_usage 699232 # Number of bytes of host memory used -host_seconds 1129.66 # Real time elapsed on the host -sim_insts 889532971 # Number of instructions simulated -sim_ops 1046714541 # Number of ops (including micro ops) simulated +host_inst_rate 678056 # Simulator instruction rate (inst/s) +host_op_rate 798173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38043399524 # Simulator tick rate (ticks/s) +host_mem_usage 751768 # Number of bytes of host memory used +host_seconds 1245.10 # Real time elapsed on the host +sim_insts 844246943 # Number of instructions simulated +sim_ops 993804803 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory -system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory +system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory -system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory +system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 921890 # Number of read requests accepted -system.physmem.writeReqs 1829645 # Number of write requests accepted -system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue -system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54393 # Per bank write bursts -system.physmem.perBankRdBursts::1 56084 # Per bank write bursts -system.physmem.perBankRdBursts::2 54659 # Per bank write bursts -system.physmem.perBankRdBursts::3 58883 # Per bank write bursts -system.physmem.perBankRdBursts::4 54974 # Per bank write bursts -system.physmem.perBankRdBursts::5 58047 # Per bank write bursts -system.physmem.perBankRdBursts::6 51881 # Per bank write bursts -system.physmem.perBankRdBursts::7 58759 # Per bank write bursts -system.physmem.perBankRdBursts::8 52533 # Per bank write bursts -system.physmem.perBankRdBursts::9 95950 # Per bank write bursts -system.physmem.perBankRdBursts::10 53815 # Per bank write bursts -system.physmem.perBankRdBursts::11 56993 # Per bank write bursts -system.physmem.perBankRdBursts::12 52328 # Per bank write bursts -system.physmem.perBankRdBursts::13 55917 # Per bank write bursts -system.physmem.perBankRdBursts::14 52932 # Per bank write bursts -system.physmem.perBankRdBursts::15 53389 # Per bank write bursts -system.physmem.perBankWrBursts::0 113787 # Per bank write bursts -system.physmem.perBankWrBursts::1 117144 # Per bank write bursts -system.physmem.perBankWrBursts::2 115098 # Per bank write bursts -system.physmem.perBankWrBursts::3 118536 # Per bank write bursts -system.physmem.perBankWrBursts::4 116769 # Per bank write bursts -system.physmem.perBankWrBursts::5 120895 # Per bank write bursts -system.physmem.perBankWrBursts::6 109520 # Per bank write bursts -system.physmem.perBankWrBursts::7 112924 # Per bank write bursts -system.physmem.perBankWrBursts::8 111914 # Per bank write bursts -system.physmem.perBankWrBursts::9 117541 # Per bank write bursts -system.physmem.perBankWrBursts::10 111832 # Per bank write bursts -system.physmem.perBankWrBursts::11 116807 # Per bank write bursts -system.physmem.perBankWrBursts::12 108182 # Per bank write bursts -system.physmem.perBankWrBursts::13 109739 # Per bank write bursts -system.physmem.perBankWrBursts::14 110202 # Per bank write bursts -system.physmem.perBankWrBursts::15 111930 # Per bank write bursts +system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 684685 # Number of read requests accepted +system.physmem.writeReqs 1596629 # Number of write requests accepted +system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue +system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 42136 # Per bank write bursts +system.physmem.perBankRdBursts::1 44080 # Per bank write bursts +system.physmem.perBankRdBursts::2 34958 # Per bank write bursts +system.physmem.perBankRdBursts::3 41288 # Per bank write bursts +system.physmem.perBankRdBursts::4 39326 # Per bank write bursts +system.physmem.perBankRdBursts::5 49165 # Per bank write bursts +system.physmem.perBankRdBursts::6 40428 # Per bank write bursts +system.physmem.perBankRdBursts::7 47118 # Per bank write bursts +system.physmem.perBankRdBursts::8 36254 # Per bank write bursts +system.physmem.perBankRdBursts::9 81044 # Per bank write bursts +system.physmem.perBankRdBursts::10 36070 # Per bank write bursts +system.physmem.perBankRdBursts::11 40557 # Per bank write bursts +system.physmem.perBankRdBursts::12 34453 # Per bank write bursts +system.physmem.perBankRdBursts::13 38158 # Per bank write bursts +system.physmem.perBankRdBursts::14 37145 # Per bank write bursts +system.physmem.perBankRdBursts::15 42231 # Per bank write bursts +system.physmem.perBankWrBursts::0 97165 # Per bank write bursts +system.physmem.perBankWrBursts::1 99476 # Per bank write bursts +system.physmem.perBankWrBursts::2 95543 # Per bank write bursts +system.physmem.perBankWrBursts::3 98326 # Per bank write bursts +system.physmem.perBankWrBursts::4 92692 # Per bank write bursts +system.physmem.perBankWrBursts::5 102230 # Per bank write bursts +system.physmem.perBankWrBursts::6 96747 # Per bank write bursts +system.physmem.perBankWrBursts::7 98806 # Per bank write bursts +system.physmem.perBankWrBursts::8 93672 # Per bank write bursts +system.physmem.perBankWrBursts::9 100275 # Per bank write bursts +system.physmem.perBankWrBursts::10 92352 # Per bank write bursts +system.physmem.perBankWrBursts::11 96579 # Per bank write bursts +system.physmem.perBankWrBursts::12 94667 # Per bank write bursts +system.physmem.perBankWrBursts::13 97213 # Per bank write bursts +system.physmem.perBankWrBursts::14 92658 # Per bank write bursts +system.physmem.perBankWrBursts::15 99164 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 47410778671000 # Total gap between requests +system.physmem.numWrRetry 352 # Number of times write queue was full causing retry +system.physmem.totGap 47367814519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 878653 # Read request sizes (log2) +system.physmem.readPktSize::6 641448 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1827042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1594026 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 16379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 14128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 9819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,181 +188,170 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 50983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 63815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 77905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 83850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 82535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 80562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 80737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 81986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 81840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 82529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 95240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 86941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 82400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 79288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads -system.physmem.totQLat 32913462781 # Total ticks spent queuing -system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads +system.physmem.totQLat 20326500723 # Total ticks spent queuing +system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing -system.physmem.readRowHits 687654 # Number of row buffer hits during reads -system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes -system.physmem.avgGap 17230665.31 # Average gap between requests -system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.749637 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states -system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing +system.physmem.readRowHits 509481 # Number of row buffer hits during reads +system.physmem.writeRowHits 909439 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes +system.physmem.avgGap 20763390.98 # Average gap between requests +system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.635370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.723459 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states -system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.605711 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -393,9 +382,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1673 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -426,66 +415,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 107972 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walks 95467 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83792624 # DTB read hits -system.cpu0.dtb.read_misses 78614 # DTB read misses -system.cpu0.dtb.write_hits 76883618 # DTB write hits -system.cpu0.dtb.write_misses 29358 # DTB write misses +system.cpu0.dtb.read_hits 81219280 # DTB read hits +system.cpu0.dtb.read_misses 71070 # DTB read misses +system.cpu0.dtb.write_hits 73504932 # DTB write hits +system.cpu0.dtb.write_misses 24397 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83871238 # DTB read accesses -system.cpu0.dtb.write_accesses 76912976 # DTB write accesses +system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81290350 # DTB read accesses +system.cpu0.dtb.write_accesses 73529329 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 160676242 # DTB hits -system.cpu0.dtb.misses 107972 # DTB misses -system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.dtb.hits 154724212 # DTB hits +system.cpu0.dtb.misses 95467 # DTB misses +system.cpu0.dtb.accesses 154819679 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -515,236 +505,239 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 64255 # Table walker walks requested -system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walks 56383 # Table walker walks requested +system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 448595101 # ITB inst hits -system.cpu0.itb.inst_misses 64255 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 434853798 # ITB inst hits +system.cpu0.itb.inst_misses 56383 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses -system.cpu0.itb.hits 448595101 # DTB hits -system.cpu0.itb.misses 64255 # DTB misses -system.cpu0.itb.accesses 448659356 # DTB accesses -system.cpu0.numCycles 94821563304 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses +system.cpu0.itb.hits 434853798 # DTB hits +system.cpu0.itb.misses 56383 # DTB misses +system.cpu0.itb.accesses 434910181 # DTB accesses +system.cpu0.numCycles 94735635148 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 448345930 # Number of instructions committed -system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses -system.cpu0.num_func_calls 26890258 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls -system.cpu0.num_int_insts 484594714 # number of integer instructions -system.cpu0.num_fp_insts 558267 # number of float instructions -system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read -system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written -system.cpu0.num_mem_refs 160668093 # number of memory refs -system.cpu0.num_load_insts 83788812 # Number of load instructions -system.cpu0.num_store_insts 76879281 # Number of store instructions -system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles -system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles -system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.committedInsts 434594659 # Number of instructions committed +system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses +system.cpu0.num_func_calls 25685063 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls +system.cpu0.num_int_insts 468245604 # number of integer instructions +system.cpu0.num_fp_insts 368958 # number of float instructions +system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written +system.cpu0.num_mem_refs 154715442 # number of memory refs +system.cpu0.num_load_insts 81215665 # Number of load instructions +system.cpu0.num_store_insts 73499777 # Number of store instructions +system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles +system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles +system.cpu0.Branches 96525602 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction -system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction -system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction +system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction +system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 527943731 # Class of executed instruction +system.cpu0.op_class::total 510121531 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5753925 # number of replacements -system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits -system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses -system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 71351766758 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 71351766758 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 71351766758 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80912816 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80912816 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73974681 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73974681 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 879214 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 879214 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 900164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 900164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986482 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1986482 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1985214 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1985214 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154887497 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154887497 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 155766711 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 155766711 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038058 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029173 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029173 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033491 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.033491 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14731.899328 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.899328 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18056.936792 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5284481 # number of replacements +system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits +system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses +system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,92 +746,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks -system.cpu0.dcache.writebacks::total 3895213 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21470 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46933 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46933 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 56590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 56590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 56590 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 56590 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3044295 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3044295 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417652 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1417652 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 692633 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 692633 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 782756 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 782756 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200615 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200615 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4461947 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4461947 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5154580 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5154580 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37795344499 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37795344499 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22579422262 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22579422262 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14234213672 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14234213672 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24458156109 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24458156109 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564829744 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564829744 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3853276103 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028808 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028808 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033092 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033092 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12415.138644 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12415.138644 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15927.337782 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks +system.cpu0.dcache.writebacks::total 3634622 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 49969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 49969 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2791784 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -846,58 +839,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5166576 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5167088 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.817778 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30209622750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.910022 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999824 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999824 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 4499955 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 902357290 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 902357290 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 443428013 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 443428013 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 443428013 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 443428013 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 443428013 # number of overall hits -system.cpu0.icache.overall_hits::total 443428013 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5167088 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5167088 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5167088 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5167088 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5167088 # number of overall misses -system.cpu0.icache.overall_misses::total 5167088 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53694723563 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 53694723563 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 53694723563 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 53694723563 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 53694723563 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 53694723563 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 448595101 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 448595101 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 448595101 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 448595101 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 448595101 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 448595101 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011518 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011518 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011518 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011518 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011518 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011518 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10391.679717 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10391.679717 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10391.679717 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 430353331 # number of overall hits +system.cpu0.icache.overall_hits::total 430353331 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4500467 # number of overall misses +system.cpu0.icache.overall_misses::total 4500467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47768563979 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 47768563979 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 47768563979 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 47768563979 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 47768563979 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 47768563979 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 434853798 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 434853798 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 434853798 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 434853798 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -906,241 +899,240 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5167088 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5167088 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5167088 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5167088 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5167088 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5167088 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45925261947 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 45925261947 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45925261947 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 45925261947 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010349 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010349 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010349 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9611.013820 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7865373 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7866135 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 648 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7625512 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 985913 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2427001 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16243.780061 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11146490 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2442996 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.562631 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 4729494500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7283.700781 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.630524 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.657228 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3931.432813 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3992.358247 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 865.000469 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.444562 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004799 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005655 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.239956 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.243674 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052795 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.991442 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1466 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14457 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 313 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 947 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4330 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6826 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089478 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.882385 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 256470983 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 256470983 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 224791 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 150515 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4652887 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2883530 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 7911723 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3895212 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3895212 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 236831 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 236831 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 106550 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 106550 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 34358 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 34358 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 952634 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 952634 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 224791 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 150515 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4652887 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3836164 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8864357 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 224791 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 150515 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4652887 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3836164 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8864357 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10425 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9020 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 514201 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 979370 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1513016 # number of ReadReq misses +system.cpu0.l2cache.prefetcher.pfSpanPage 975949 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2276475 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16164.000425 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9930056 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2292579 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.331391 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5342662500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7643.384526 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.376858 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.669060 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3718.900652 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3598.062438 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1070.606892 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.466515 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003502 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004618 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226984 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219608 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065345 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986572 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1394 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 811 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4617 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5283 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3880 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085083 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 232158629 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 232158629 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 184213 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122134 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 3989528 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2659243 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 6955118 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3634621 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3634621 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 174040 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 174040 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 97614 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 97614 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30602 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 30602 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 869323 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 869323 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 184213 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122134 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 3989528 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3528566 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 7824441 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 184213 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122134 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 3989528 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3528566 # number of overall hits +system.cpu0.l2cache.overall_hits::total 7824441 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8450 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6821 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 510939 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 880615 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1406825 # number of ReadReq misses system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 544650 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 544650 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 122779 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 122779 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 166249 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 166249 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 253376 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 253376 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10425 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9020 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 514201 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1232746 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1766392 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10425 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9020 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 514201 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1232746 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1766392 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 401624493 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 376564494 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15423284566 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32417465776 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 48618939329 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 194184961 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 194184961 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2456096364 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2456096364 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3361972231 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3361972231 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2084000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2084000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11515878505 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 11515878505 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 401624493 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 376564494 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15423284566 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 43933344281 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 60134817834 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 401624493 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 376564494 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15423284566 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 43933344281 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 60134817834 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 235216 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 159535 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5167088 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3862900 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 9424739 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3895213 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3895213 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 781481 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 781481 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 229329 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 229329 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200607 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 200607 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1206010 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1206010 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 235216 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 159535 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5167088 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5068910 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 10630749 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 235216 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 159535 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5167088 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5068910 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 10630749 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056539 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.099515 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.253532 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.160537 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570673 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 570673 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121192 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 121192 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 152342 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 152342 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228613 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 228613 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8450 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 6821 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 510939 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1109228 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1635438 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8450 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 6821 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 510939 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1109228 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1635438 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 233396250 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 201613986 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15055870276 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 27344253636 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 42835134148 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 214216390 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 214216390 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2669808389 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2669808389 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3193098671 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3193098671 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1181000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1181000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10520875436 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 10520875436 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 233396250 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 201613986 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15055870276 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 37865129072 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 53356009584 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 233396250 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 201613986 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15055870276 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 37865129072 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 53356009584 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 192663 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 128955 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4500467 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3539858 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 8361943 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3634622 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3634622 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 744713 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 744713 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218806 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 218806 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 182944 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 182944 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1097936 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1097936 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 192663 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 128955 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 4500467 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4637794 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 9459879 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 192663 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 128955 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 4500467 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4637794 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 9459879 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052894 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.113530 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.248771 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.168241 # miss rate for ReadReq accesses system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.696946 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.696946 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.535384 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.535384 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.828730 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.828730 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.766299 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.766299 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.553879 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.553879 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.832725 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.832725 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.210094 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.210094 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056539 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.099515 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.243197 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.166159 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056539 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.099515 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.243197 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.166159 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41747.726608 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29994.660777 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33100.325491 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32133.790607 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 356.531646 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 356.531646 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20004.205638 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20004.205638 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20222.510999 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.510999 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 260500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 260500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45449.760455 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45449.760455 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41747.726608 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29994.660777 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35638.602178 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 34043.868991 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41747.726608 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29994.660777 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35638.602178 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 34043.868991 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.208221 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.208221 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052894 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.113530 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.239171 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.172881 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052894 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.113530 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.239171 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.172881 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 29557.834042 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29467.060209 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 31051.314861 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30448.089953 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 375.375022 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 375.375022 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22029.576119 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22029.576119 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20960.067946 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20960.067946 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 393666.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 393666.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46020.460061 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46020.460061 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 32624.905123 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 32624.905123 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1149,140 +1141,140 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1390929 # number of writebacks -system.cpu0.l2cache.writebacks::total 1390929 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 412 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5653 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5653 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6065 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6065 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6065 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6065 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10425 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9020 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 514201 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 978958 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1512604 # number of ReadReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 1283433 # number of writebacks +system.cpu0.l2cache.writebacks::total 1283433 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 443 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 443 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3351 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3351 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3794 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3794 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3794 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3794 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8450 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6821 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 510939 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 880172 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1406382 # number of ReadReq MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 705771 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 705771 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 544650 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 544650 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 122779 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 122779 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 166249 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 166249 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247723 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 247723 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10425 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9020 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 514201 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1226681 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1760327 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10425 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9020 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 514201 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1226681 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 705771 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2466098 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 312733504 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11805310434 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25478803206 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 37924779653 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34882867408 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 34882867408 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 18696199399 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18696199399 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2085589258 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2085589258 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2284466860 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2284466860 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1713000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1713000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9147060396 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9147060396 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 312733504 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11805310434 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34625863602 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 47071840049 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312733504 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11805310434 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34625863602 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34882867408 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 81954707457 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2174725243 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5236589993 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129495502 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2129495502 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4304220745 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7366085495 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253426 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160493 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 635942 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570673 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570673 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121192 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121192 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 152342 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 152342 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 225262 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 225262 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8450 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6821 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 510939 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1105434 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1631644 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8450 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6821 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 510939 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1105434 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2267586 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 157112514 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11720586224 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 21558629277 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33614638265 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 23030840367 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24220184845 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24220184845 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529730528 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529730528 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2304861456 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304861456 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1005500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1005500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8691962659 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8691962659 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 157112514 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11720586224 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 30250591936 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 42306600924 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 157112514 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11720586224 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 30250591936 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.696946 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.696946 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.535384 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.535384 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.828730 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.828730 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205407 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205407 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1292,58 +1284,56 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1374,74 +1364,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 99527 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walks 92509 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83767099 # DTB read hits -system.cpu1.dtb.read_misses 74857 # DTB read misses -system.cpu1.dtb.write_hits 75685520 # DTB write hits -system.cpu1.dtb.write_misses 24670 # DTB write misses +system.cpu1.dtb.read_hits 78277454 # DTB read hits +system.cpu1.dtb.read_misses 68245 # DTB read misses +system.cpu1.dtb.write_hits 71517077 # DTB write hits +system.cpu1.dtb.write_misses 24264 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83841956 # DTB read accesses -system.cpu1.dtb.write_accesses 75710190 # DTB write accesses +system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78345699 # DTB read accesses +system.cpu1.dtb.write_accesses 71541341 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 159452619 # DTB hits -system.cpu1.dtb.misses 99527 # DTB misses -system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.dtb.hits 149794531 # DTB hits +system.cpu1.dtb.misses 92509 # DTB misses +system.cpu1.dtb.accesses 149887040 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1471,239 +1454,242 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 55326 # Table walker walks requested -system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walks 60524 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 441493680 # ITB inst hits -system.cpu1.itb.inst_misses 55326 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 409921957 # ITB inst hits +system.cpu1.itb.inst_misses 60524 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses -system.cpu1.itb.hits 441493680 # DTB hits -system.cpu1.itb.misses 55326 # DTB misses -system.cpu1.itb.accesses 441549006 # DTB accesses -system.cpu1.numCycles 94821563303 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses +system.cpu1.itb.hits 409921957 # DTB hits +system.cpu1.itb.misses 60524 # DTB misses +system.cpu1.itb.accesses 409982481 # DTB accesses +system.cpu1.numCycles 94735635148 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 441187041 # Number of instructions committed -system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses -system.cpu1.num_func_calls 26570520 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls -system.cpu1.num_int_insts 477531543 # number of integer instructions -system.cpu1.num_fp_insts 364386 # number of float instructions -system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read -system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written -system.cpu1.num_mem_refs 159443034 # number of memory refs -system.cpu1.num_load_insts 83763663 # Number of load instructions -system.cpu1.num_store_insts 75679371 # Number of store instructions -system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles -system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles -system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.committedInsts 409652284 # Number of instructions committed +system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses +system.cpu1.num_func_calls 25682090 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls +system.cpu1.num_int_insts 446181756 # number of integer instructions +system.cpu1.num_fp_insts 565626 # number of float instructions +system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read +system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written +system.cpu1.num_mem_refs 149782083 # number of memory refs +system.cpu1.num_load_insts 78271508 # Number of load instructions +system.cpu1.num_store_insts 71510575 # Number of store instructions +system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles +system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles +system.cpu1.Branches 91673037 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction -system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction +system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 519369853 # Class of executed instruction +system.cpu1.op_class::total 484255317 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 4977655 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1712714 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1712714 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1673213 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1673213 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150096526 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150096526 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150288224 # number of overall hits -system.cpu1.dcache.overall_hits::total 150288224 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2870044 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2870044 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1235849 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1235849 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 574884 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 574884 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 468795 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 468795 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 161452 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 161452 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199386 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 199386 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4105893 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4105893 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4680777 # number of overall misses -system.cpu1.dcache.overall_misses::total 4680777 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 59961592307 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81102062 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81102062 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73100357 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73100357 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 766582 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 766582 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 680241 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 680241 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026627 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026627 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030205 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030205 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13728.194596 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13728.194596 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16637.202260 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16637.202260 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 25851.783916 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 25851.783916 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14296.089593 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14296.089593 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21372.987346 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21372.987346 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4752540 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits +system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses +system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1712,92 +1698,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3230902 # number of writebacks -system.cpu1.dcache.writebacks::total 3230902 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11797 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 11797 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 280 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42800 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42800 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 12077 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 12077 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 12077 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 12077 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858247 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2858247 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1235569 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1235569 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 574884 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 574884 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 468795 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 468795 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118652 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118652 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199386 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 199386 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4093816 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4093816 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4668700 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4668700 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 33045194740 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 33045194740 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18021373474 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18021373474 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10397149259 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10397149259 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11178014959 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11178014959 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1426804491 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1426804491 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3852246545 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3852246545 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1872000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1872000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51066568214 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 51066568214 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 61463717473 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks +system.cpu1.dcache.writebacks::total 3063492 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1805,59 +1791,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4937125 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5523110 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits -system.cpu1.icache.overall_hits::total 436556038 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4937642 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4937642 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4937642 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4937642 # number of overall misses -system.cpu1.icache.overall_misses::total 4937642 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50835870381 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50835870381 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50835870381 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50835870381 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50835870381 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50835870381 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 441493680 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 441493680 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011184 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011184 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011184 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011184 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011184 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011184 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 404398330 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 404398330 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 404398330 # number of overall hits +system.cpu1.icache.overall_hits::total 404398330 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5523627 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5523627 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5523627 # number of overall misses +system.cpu1.icache.overall_misses::total 5523627 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54612807078 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 409921957 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 409921957 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013475 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1866,239 +1852,236 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4937642 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4937642 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4937642 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4937642 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4937642 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4937642 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43414323627 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 43414323627 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43414323627 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 43414323627 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43414323627 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 43414323627 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8951000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8951000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8951000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8951000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011184 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011184 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011184 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5523627 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5523627 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5523627 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5523627 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5523627 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5523627 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49075741422 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49075741422 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6896094 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6896721 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 539 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 5870481 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 853759 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1907013 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13040.746764 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10338978 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1923015 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.376442 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9789299685500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5807.381964 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.245810 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 78.947620 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2946.895146 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3156.020749 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 990.255474 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.354454 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003738 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004819 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.179864 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192628 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060440 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.795944 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1412 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 94 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1121 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 188 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1044 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1799 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10295 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.086182 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005737 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 227501804 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 227501804 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 207163 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 127057 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4446186 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2697591 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7477997 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3230902 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3230902 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 181429 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 181429 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59189 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 59189 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31769 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 31769 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 842543 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 842543 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 207163 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 127057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4446186 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3540134 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8320540 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 207163 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 127057 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4446186 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3540134 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8320540 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 8925 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 6995 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 491456 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 854192 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1361568 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 285701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 285701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 127179 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 127179 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167611 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 167611 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 208488 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 208488 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 8925 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 6995 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 491456 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1062680 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1570056 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 8925 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 6995 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 491456 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1062680 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1570056 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 266500250 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 219567495 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 14267491069 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 25122385610 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 39875944424 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 189007871 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 189007871 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2544221753 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2544221753 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3390574541 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3390574541 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1824999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1824999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8358339864 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 8358339864 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 266500250 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 219567495 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14267491069 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 33480725474 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 48234284288 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 266500250 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 219567495 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14267491069 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 33480725474 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 48234284288 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 216088 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 134052 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4937642 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3551783 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 8839565 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3230902 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3230902 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 467130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 467130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 186368 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 186368 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199380 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 199380 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051031 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1051031 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 216088 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 134052 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4937642 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4602814 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 9890596 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 216088 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 134052 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4937642 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4602814 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 9890596 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052181 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.099533 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.240497 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.154031 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.611609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.611609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.682408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.682408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.840661 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.840661 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 1638473 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.512494 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5186.730932 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005424 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.231268 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.210756 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050163 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.818494 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1616 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 744 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.098633 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 229858181 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 229858181 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 196843 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 146711 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5082589 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2590406 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 8016549 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3063492 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3063492 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 265137 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 265137 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 50742 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 50742 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 28295 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 28295 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 777406 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 777406 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 196843 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 146711 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5082589 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3367812 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8793955 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 196843 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 146711 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5082589 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3367812 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8793955 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9130 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7601 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 441038 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 776098 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1233867 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 229595 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 229595 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120541 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 120541 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 147968 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 147968 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 207551 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 207551 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9130 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7601 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 441038 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 983649 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1441418 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9130 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7601 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 441038 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 983649 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1441418 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 287537248 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 274641499 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 13255864672 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 23821498253 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 37639541672 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 209637116 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 209637116 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2569493734 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2569493734 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3076594441 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3076594441 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1773498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1773498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8057830380 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 8057830380 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 287537248 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 274641499 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 13255864672 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 31879328633 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 45697372052 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 287537248 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 274641499 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 13255864672 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 31879328633 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 45697372052 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 205973 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 154312 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5523627 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3366504 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 9250416 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3063492 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3063492 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 494732 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 494732 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 171283 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 171283 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 176263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 176263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 984957 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 984957 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 205973 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 154312 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5523627 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4351461 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10235373 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 205973 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 154312 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5523627 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4351461 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10235373 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049257 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079846 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.230535 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.133385 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.464080 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.464080 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.703753 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.703753 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.839473 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.839473 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.198365 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.198365 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052181 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.099533 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.230876 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.158742 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052181 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.099533 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.230876 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.158742 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 31389.205861 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29031.064976 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 29410.701119 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29286.781434 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 661.558311 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 661.558311 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20005.046061 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20005.046061 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20228.830691 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20228.830691 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 304166.500000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 304166.500000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40090.268332 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40090.268332 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 31389.205861 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29031.064976 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 31505.933559 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 30721.378274 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 31389.205861 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29031.064976 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 31505.933559 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 30721.378274 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210721 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210721 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049257 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079846 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.226050 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.140827 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049257 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079846 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.226050 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.140827 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36132.285094 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30056.060185 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30693.930732 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30505.347555 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 913.073525 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 913.073525 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21316.346587 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21316.346587 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20792.295909 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20792.295909 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354699.600000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354699.600000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38823.375363 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38823.375363 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31703.067432 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31703.067432 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2107,136 +2090,136 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 911309 # number of writebacks -system.cpu1.l2cache.writebacks::total 911309 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 380 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5401 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 5401 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5781 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 5781 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5781 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 5781 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 8925 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 6995 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 491456 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 853812 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1361188 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 639196 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 639196 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 285701 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 285701 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 127179 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 127179 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167611 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167611 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 203087 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 203087 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 8925 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 6995 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 491456 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1056899 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1564275 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 8925 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 6995 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 491456 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1056899 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 639196 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2203471 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 170362507 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10812394931 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 19078738641 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 30265237329 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29755594933 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7736539648 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7736539648 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2151571523 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2151571523 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2290441908 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2290441908 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1495999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1495999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6293487581 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6293487581 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 170362507 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10812394931 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25372226222 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 36558724910 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 170362507 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10812394931 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25372226222 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 66314319843 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8087000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3880010250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3888097250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3784845500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3784845500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8087000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7664855750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7672942750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.240390 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.153988 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 764216 # number of writebacks +system.cpu1.l2cache.writebacks::total 764216 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 2534 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 2534 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 2857 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 2857 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 2857 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 2857 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9130 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7601 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 441038 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 775775 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1233544 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 524912 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 229595 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 229595 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120541 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120541 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 147968 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147968 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 205017 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 205017 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9130 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7601 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 441038 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 980792 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1438561 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9130 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7601 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 441038 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 980792 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 1963473 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224849501 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10375497328 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 18713747169 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29541935250 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 17727784992 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7402905507 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7402905507 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2380480811 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224849501 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10375497328 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25150532637 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 35978720718 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224849501 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 53706505710 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.611609 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.611609 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.682408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.682408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.840661 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.840661 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193226 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193226 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158158 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2246,66 +2229,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40416 # Transaction distribution -system.iobus.trans_dist::ReadResp 40416 # Transaction distribution -system.iobus.trans_dist::WriteReq 136984 # Transaction distribution -system.iobus.trans_dist::WriteResp 30064 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40336 # Transaction distribution +system.iobus.trans_dist::ReadResp 40336 # Transaction distribution +system.iobus.trans_dist::WriteReq 136623 # Transaction distribution +system.iobus.trans_dist::WriteResp 29895 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2315,18 +2295,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2336,18 +2316,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2367,7 +2347,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2375,71 +2355,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115804 # number of replacements -system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use +system.iocache.tags.replacements 115606 # number of replacements +system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042755 # Number of tag accesses -system.iocache.tags.data_accesses 1042755 # Number of data accesses +system.iocache.tags.tag_accesses 1040802 # Number of tag accesses +system.iocache.tags.data_accesses 1040802 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses -system.iocache.demand_misses::total 8942 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses +system.iocache.demand_misses::total 8917 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8902 # number of overall misses -system.iocache.overall_misses::total 8942 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8877 # number of overall misses +system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2453,55 +2433,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106887 # number of writebacks -system.iocache.writebacks::total 106887 # number of writebacks +system.iocache.writebacks::writebacks 106699 # number of writebacks +system.iocache.writebacks::total 106699 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1479616613 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1483399613 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427435940 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427435940 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1479616613 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2515,560 +2495,561 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1354462 # number of replacements -system.l2c.tags.tagsinuse 64231.297434 # Cycle average of tags in use -system.l2c.tags.total_refs 4107458 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1415378 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.902022 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9445810500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19768.926665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 228.224478 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 327.605712 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4403.400979 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 13076.363837 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14280.609802 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 81.212634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 119.963342 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.036513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.054542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.091211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.980092 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11341 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49312 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 2022 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9958 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38095 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.173050 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.752441 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 56299103 # Number of tag accesses -system.l2c.tags.data_accesses 56299103 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4570 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461305 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 560254 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 286198 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 447471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 478954 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 267354 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2519544 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2302237 # number of Writeback hits -system.l2c.Writeback_hits::total 2302237 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 120106 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 132921 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 253027 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 30097 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 26085 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 56182 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6492 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6040 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12532 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53617 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43662 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97279 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4570 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 461305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 613871 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 286198 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3561 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 447471 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 522616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 267354 # number of demand (read+write) hits -system.l2c.demand_hits::total 2616823 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5350 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4570 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461305 # number of overall hits -system.l2c.overall_hits::cpu0.data 613871 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 286198 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4527 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3561 # number of overall hits -system.l2c.overall_hits::cpu1.inst 447471 # number of overall hits -system.l2c.overall_hits::cpu1.data 522616 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 267354 # number of overall hits -system.l2c.overall_hits::total 2616823 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2413 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2450 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 52896 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 145508 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 228001 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1040 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 43985 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 87538 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 186786 # number of ReadReq misses -system.l2c.ReadReq_misses::total 751553 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 416232 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 144931 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 561163 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 42338 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 43944 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 86282 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 11190 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 10651 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21841 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76863 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48194 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125057 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2413 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2450 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 52896 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 222371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 228001 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1040 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 43985 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 135732 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 186786 # number of demand (read+write) misses -system.l2c.demand_misses::total 876610 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2413 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2450 # number of overall misses -system.l2c.overall_misses::cpu0.inst 52896 # number of overall misses -system.l2c.overall_misses::cpu0.data 222371 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 228001 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1040 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 936 # number of overall misses -system.l2c.overall_misses::cpu1.inst 43985 # number of overall misses -system.l2c.overall_misses::cpu1.data 135732 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 186786 # number of overall misses -system.l2c.overall_misses::total 876610 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195380250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 200494999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 4090074480 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 12129961164 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 84415498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 77437999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3371676973 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 7239872891 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 80786955615 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 28586777 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 37049410 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 65636187 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 168593848 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 188274034 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 356867882 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 43019164 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45414580 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 88433744 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6101127950 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3658485827 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9759613777 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 195380250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 200494999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 4090074480 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 18231089114 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 84415498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 77437999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3371676973 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 10898358718 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 90546569392 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 195380250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 200494999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 4090074480 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 18231089114 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 84415498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 77437999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3371676973 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 10898358718 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of overall miss cycles -system.l2c.overall_miss_latency::total 90546569392 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 7763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7020 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 514201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 705762 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 514199 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5567 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 4497 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 491456 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 566492 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 454140 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3271097 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2302237 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2302237 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 536338 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 277852 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 814190 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 72435 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 70029 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 142464 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 17682 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 16691 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 34373 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 130480 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 91856 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 222336 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 7763 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7020 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 514201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 836242 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 514199 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 4497 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 491456 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 658348 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454140 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3493433 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 7763 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7020 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 514201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 836242 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 514199 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 4497 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 491456 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 658348 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454140 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3493433 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.349003 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.102870 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.206171 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.208139 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.089499 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.154526 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.229756 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.776063 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.521612 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.689229 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584496 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.627511 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.605641 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.632847 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.638128 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.635412 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.589079 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.524669 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.562469 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.349003 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.102870 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.265917 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.208139 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.089499 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.206171 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.250931 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.349003 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.102870 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.265917 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.208139 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.089499 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.206171 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.250931 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 81834.693469 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77322.944646 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 83362.847156 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 82732.904915 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76655.154553 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 82705.486657 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 107493.357907 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 68.679912 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 255.634819 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 116.964566 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3982.092872 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4284.408201 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4136.064092 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3844.429312 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4263.879448 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4048.978710 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79376.656519 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75911.645163 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 78041.323373 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 81834.693469 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 77322.944646 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 81985.012047 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82732.904915 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76655.154553 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 80293.215439 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 103291.736795 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 81834.693469 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 77322.944646 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 81985.012047 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82732.904915 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76655.154553 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 80293.215439 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 103291.736795 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 198 # number of cycles access was blocked +system.l2c.tags.replacements 1063912 # number of replacements +system.l2c.tags.tagsinuse 64178.177670 # Cycle average of tags in use +system.l2c.tags.total_refs 3766892 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1123413 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.353079 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11093199000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 24092.358885 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 75.949373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 107.097830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4212.805606 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7550.293396 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7226.795277 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.211397 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 222.509709 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4405.039325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 7865.744621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8270.372252 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.367620 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001159 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.064282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.115208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110272 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002277 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.067216 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.120022 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.126196 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979281 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9644 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 191 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49666 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 226 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9286 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43236 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.147156 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002914 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.757843 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 50574940 # Number of tag accesses +system.l2c.tags.data_accesses 50574940 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5180 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4259 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 469863 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 537542 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 313027 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3587 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 401752 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 405704 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 231220 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2376624 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2047649 # number of Writeback hits +system.l2c.Writeback_hits::total 2047649 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 135493 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 115685 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 251178 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 31239 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 22507 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 53746 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6431 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5062 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11493 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47681 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 46115 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 93796 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5180 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4259 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 469863 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 585223 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 313027 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4490 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3587 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 401752 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 451819 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 231220 # number of demand (read+write) hits +system.l2c.demand_hits::total 2470420 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5180 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4259 # number of overall hits +system.l2c.overall_hits::cpu0.inst 469863 # number of overall hits +system.l2c.overall_hits::cpu0.data 585223 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 313027 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4490 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3587 # number of overall hits +system.l2c.overall_hits::cpu1.inst 401752 # number of overall hits +system.l2c.overall_hits::cpu1.data 451819 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 231220 # number of overall hits +system.l2c.overall_hits::total 2470420 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 577 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 634 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 41076 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 94183 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 149529 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1129 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1344 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 39286 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 84710 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq misses +system.l2c.ReadReq_misses::total 531147 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 427179 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 105657 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 532836 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 47914 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 38699 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 86613 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 10572 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7951 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18523 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 64089 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 43672 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107761 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 577 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 634 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 41076 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 158272 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 149529 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1129 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1344 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 39286 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 128382 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) misses +system.l2c.demand_misses::total 638908 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 577 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 634 # number of overall misses +system.l2c.overall_misses::cpu0.inst 41076 # number of overall misses +system.l2c.overall_misses::cpu0.data 158272 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 149529 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1129 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1344 # number of overall misses +system.l2c.overall_misses::cpu1.inst 39286 # number of overall misses +system.l2c.overall_misses::cpu1.data 128382 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 118679 # number of overall misses +system.l2c.overall_misses::total 638908 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 51297750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 55466264 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 3464868273 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 8461586857 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 98269250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 120308250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3289147097 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 7432991468 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 55049336677 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 56781694 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 44775578 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 101557272 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 267824472 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 195648800 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 463473272 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46262535 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 41400197 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 87662732 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5583608052 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3566659435 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9150267487 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 51297750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 55466264 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 3464868273 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 14045194909 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 98269250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 120308250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3289147097 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 10999650903 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 64199604164 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 51297750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 55466264 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 3464868273 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 14045194909 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 98269250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 120308250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3289147097 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 10999650903 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of overall miss cycles +system.l2c.overall_miss_latency::total 64199604164 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5757 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4893 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 510939 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 631725 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 462556 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5619 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 4931 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 441038 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 490414 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 349899 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2907771 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2047649 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2047649 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 562672 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 221342 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 784014 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 79153 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 61206 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 140359 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 17003 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 13013 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 30016 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111770 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 89787 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 201557 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5757 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4893 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 510939 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 743495 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 462556 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5619 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 4931 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 441038 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 580201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 349899 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3109328 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5757 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4893 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 510939 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 743495 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 462556 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5619 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 4931 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 441038 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 580201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 349899 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3109328 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129573 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.080393 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.149089 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.272561 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.089076 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.172732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.182665 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.759197 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.477347 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.679626 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605334 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.632275 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.617082 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.621773 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.611004 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.617104 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.573401 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.486396 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.534643 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.129573 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.080393 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.212876 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.272561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.089076 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.221272 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.205481 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.129573 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.080393 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.212876 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.272561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.089076 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.221272 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.205481 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87486.220820 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84352.621312 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 89841.976333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89515.066964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83723.135392 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 87746.328273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 103642.375231 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 132.922484 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 423.782409 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 190.597617 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5589.691364 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5055.655185 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5351.082078 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4375.949205 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5206.916992 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4732.642229 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87122.720779 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81669.248832 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84912.607409 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 100483.331190 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 100483.331190 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 154 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 154 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1054885 # number of writebacks -system.l2c.writebacks::total 1054885 # number of writebacks +system.l2c.writebacks::writebacks 850996 # number of writebacks +system.l2c.writebacks::total 850996 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 92 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 68 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 78 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 88 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 92 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 68 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 78 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 88 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 92 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 68 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 78 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 256 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2413 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2450 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 52804 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 145440 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1040 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 936 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 43907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 87520 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 751297 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 416232 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 144931 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 561163 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 42338 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 43944 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 86282 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11190 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10651 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 21841 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 76863 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 48194 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 125057 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2413 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2450 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 52804 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 222303 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1040 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 936 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 43907 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 135714 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 876354 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2413 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2450 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 52804 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 222303 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1040 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 936 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 43907 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 135714 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 876354 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 169847499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3419732984 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10297367216 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 65754499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2814972981 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6141826747 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 71448154035 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 9351321200 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2933979052 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 12285300252 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 426814585 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 447026638 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 873841223 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 112957622 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 108321571 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 221279193 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5133347486 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3050003137 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8183350623 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 169847499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 3419732984 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15430714702 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 65754499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2814972981 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 9191829884 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 79631504658 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 169847499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 3419732984 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15430714702 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 65754499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2814972981 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 9191829884 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 79631504658 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1919142750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6014500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3441525748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7612880248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1867778498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3390717000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5258495498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3786921248 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6014500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6832242748 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12871375746 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.206075 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.154495 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.229677 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.776063 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.521612 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.689229 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584496 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.627511 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.605641 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.632847 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.638128 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.635412 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589079 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524669 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.562469 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.250858 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.250858 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70801.479758 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70176.265391 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 95099.746219 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22466.608046 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 88 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 223 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 577 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 634 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 40984 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 94163 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1129 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1344 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 39198 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 84689 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 530924 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 427179 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 105657 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 532836 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 47914 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 38699 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 86613 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10572 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7951 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18523 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 64089 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 43672 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 107761 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 577 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 634 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 40984 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 158252 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1129 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1344 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 39198 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 128361 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 638685 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 577 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 634 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 40984 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 158252 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1129 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1344 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 39198 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 128361 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 638685 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 47468736 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2944278477 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7281223143 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 103357750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2790521653 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6370080782 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 48441561155 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13848705306 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3323050924 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17171756230 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 851924300 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 688614575 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1540538875 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 188348548 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 142101429 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 330449977 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4782492948 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3019981565 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7802474513 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 47468736 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2944278477 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12063716091 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 103357750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 2790521653 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 9390062347 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 56244035668 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 47468736 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2944278477 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12063716091 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 103357750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 2790521653 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 9390062347 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 56244035668 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3774730500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6744750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1609448501 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7996683251 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3450397000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1827911500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5278308500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7225127500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6744750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3437360001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13274991751 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.149057 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3083,58 +3064,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 841910 # Transaction distribution -system.membus.trans_dist::ReadResp 841910 # Transaction distribution -system.membus.trans_dist::WriteReq 38471 # Transaction distribution -system.membus.trans_dist::WriteResp 38471 # Transaction distribution -system.membus.trans_dist::Writeback 1161772 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution -system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution -system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138806 # Transaction distribution -system.membus.trans_dist::ReadExResp 121371 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 622157 # Transaction distribution +system.membus.trans_dist::ReadResp 622157 # Transaction distribution +system.membus.trans_dist::WriteReq 38973 # Transaction distribution +system.membus.trans_dist::WriteResp 38973 # Transaction distribution +system.membus.trans_dist::Writeback 957695 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution +system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution +system.membus.trans_dist::ReadExReq 123220 # Transaction distribution +system.membus.trans_dist::ReadExResp 104410 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 613627 # Total snoops (count) -system.membus.snoop_fanout::samples 3433927 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 581158 # Total snoops (count) +system.membus.snoop_fanout::samples 2928688 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3433927 # Request fanout histogram -system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2928688 # Request fanout histogram +system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3178,45 +3159,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1593139 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1518303 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 11eb5dd0c..d577712e0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821157 # Number of seconds simulated -sim_ticks 51821157171000 # Number of ticks simulated -final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.824462 # Number of seconds simulated +sim_ticks 51824462100500 # Number of ticks simulated +final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734878 # Simulator instruction rate (inst/s) -host_op_rate 863519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42416153440 # Simulator tick rate (ticks/s) -host_mem_usage 712380 # Number of bytes of host memory used -host_seconds 1221.73 # Real time elapsed on the host -sim_insts 897823750 # Number of instructions simulated -sim_ops 1054987960 # Number of ops (including micro ops) simulated +host_inst_rate 723017 # Simulator instruction rate (inst/s) +host_op_rate 849578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41937024652 # Simulator tick rate (ticks/s) +host_mem_usage 712044 # Number of bytes of host memory used +host_seconds 1235.77 # Real time elapsed on the host +sim_insts 893481288 # Number of instructions simulated +sim_ops 1049881338 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory -system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory +system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory +system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 959908 # Number of read requests accepted -system.physmem.writeReqs 1865455 # Number of write requests accepted -system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue -system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56974 # Per bank write bursts -system.physmem.perBankRdBursts::1 60608 # Per bank write bursts -system.physmem.perBankRdBursts::2 56247 # Per bank write bursts -system.physmem.perBankRdBursts::3 58787 # Per bank write bursts -system.physmem.perBankRdBursts::4 55621 # Per bank write bursts -system.physmem.perBankRdBursts::5 61105 # Per bank write bursts -system.physmem.perBankRdBursts::6 53454 # Per bank write bursts -system.physmem.perBankRdBursts::7 55202 # Per bank write bursts -system.physmem.perBankRdBursts::8 54549 # Per bank write bursts -system.physmem.perBankRdBursts::9 101006 # Per bank write bursts -system.physmem.perBankRdBursts::10 57136 # Per bank write bursts -system.physmem.perBankRdBursts::11 59250 # Per bank write bursts -system.physmem.perBankRdBursts::12 54470 # Per bank write bursts -system.physmem.perBankRdBursts::13 61564 # Per bank write bursts -system.physmem.perBankRdBursts::14 57688 # Per bank write bursts -system.physmem.perBankRdBursts::15 55438 # Per bank write bursts -system.physmem.perBankWrBursts::0 113578 # Per bank write bursts -system.physmem.perBankWrBursts::1 118177 # Per bank write bursts -system.physmem.perBankWrBursts::2 119014 # Per bank write bursts -system.physmem.perBankWrBursts::3 122732 # Per bank write bursts -system.physmem.perBankWrBursts::4 115108 # Per bank write bursts -system.physmem.perBankWrBursts::5 118421 # Per bank write bursts -system.physmem.perBankWrBursts::6 110433 # Per bank write bursts -system.physmem.perBankWrBursts::7 110649 # Per bank write bursts -system.physmem.perBankWrBursts::8 111009 # Per bank write bursts -system.physmem.perBankWrBursts::9 115530 # Per bank write bursts -system.physmem.perBankWrBursts::10 116272 # Per bank write bursts -system.physmem.perBankWrBursts::11 116171 # Per bank write bursts -system.physmem.perBankWrBursts::12 116950 # Per bank write bursts -system.physmem.perBankWrBursts::13 121923 # Per bank write bursts -system.physmem.perBankWrBursts::14 117171 # Per bank write bursts -system.physmem.perBankWrBursts::15 115525 # Per bank write bursts +system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 923811 # Number of read requests accepted +system.physmem.writeReqs 1833124 # Number of write requests accepted +system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue +system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 57129 # Per bank write bursts +system.physmem.perBankRdBursts::1 60965 # Per bank write bursts +system.physmem.perBankRdBursts::2 52485 # Per bank write bursts +system.physmem.perBankRdBursts::3 50413 # Per bank write bursts +system.physmem.perBankRdBursts::4 54002 # Per bank write bursts +system.physmem.perBankRdBursts::5 59718 # Per bank write bursts +system.physmem.perBankRdBursts::6 51713 # Per bank write bursts +system.physmem.perBankRdBursts::7 51669 # Per bank write bursts +system.physmem.perBankRdBursts::8 50247 # Per bank write bursts +system.physmem.perBankRdBursts::9 101235 # Per bank write bursts +system.physmem.perBankRdBursts::10 59848 # Per bank write bursts +system.physmem.perBankRdBursts::11 58323 # Per bank write bursts +system.physmem.perBankRdBursts::12 55369 # Per bank write bursts +system.physmem.perBankRdBursts::13 55988 # Per bank write bursts +system.physmem.perBankRdBursts::14 51743 # Per bank write bursts +system.physmem.perBankRdBursts::15 52477 # Per bank write bursts +system.physmem.perBankWrBursts::0 110630 # Per bank write bursts +system.physmem.perBankWrBursts::1 112240 # Per bank write bursts +system.physmem.perBankWrBursts::2 108805 # Per bank write bursts +system.physmem.perBankWrBursts::3 108103 # Per bank write bursts +system.physmem.perBankWrBursts::4 111102 # Per bank write bursts +system.physmem.perBankWrBursts::5 113339 # Per bank write bursts +system.physmem.perBankWrBursts::6 105567 # Per bank write bursts +system.physmem.perBankWrBursts::7 107723 # Per bank write bursts +system.physmem.perBankWrBursts::8 108849 # Per bank write bursts +system.physmem.perBankWrBursts::9 115780 # Per bank write bursts +system.physmem.perBankWrBursts::10 115663 # Per bank write bursts +system.physmem.perBankWrBursts::11 113049 # Per bank write bursts +system.physmem.perBankWrBursts::12 112494 # Per bank write bursts +system.physmem.perBankWrBursts::13 116984 # Per bank write bursts +system.physmem.perBankWrBursts::14 111502 # Per bank write bursts +system.physmem.perBankWrBursts::15 110389 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51821154615000 # Total gap between requests +system.physmem.numWrRetry 145 # Number of times write queue was full causing retry +system.physmem.totGap 51824459475500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 916792 # Read request sizes (log2) +system.physmem.readPktSize::6 880695 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1862882 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 923488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1830551 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,181 +159,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 58678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 72148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 102041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 108153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 122813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 113028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 114051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 111714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 103051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 101586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 95736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 95578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 94283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 618930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads -system.physmem.totQLat 12424177254 # Total ticks spent queuing -system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads +system.physmem.totQLat 12043609520 # Total ticks spent queuing +system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing -system.physmem.readRowHits 722238 # Number of row buffer hits during reads -system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes -system.physmem.avgGap 18341414.75 # Average gap between requests -system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.671195 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing +system.physmem.readRowHits 694872 # Number of row buffer hits during reads +system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes +system.physmem.avgGap 18797853.22 # Average gap between requests +system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.655841 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.683425 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.672178 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -387,73 +371,68 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 215397 # Table walker walks requested -system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walks 211321 # Table walker walks requested +system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168647599 # DTB read hits -system.cpu.dtb.read_misses 158984 # DTB read misses -system.cpu.dtb.write_hits 153347297 # DTB write hits -system.cpu.dtb.write_misses 56413 # DTB write misses +system.cpu.dtb.read_hits 167775531 # DTB read hits +system.cpu.dtb.read_misses 155743 # DTB read misses +system.cpu.dtb.write_hits 152648275 # DTB write hits +system.cpu.dtb.write_misses 55578 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168806583 # DTB read accesses -system.cpu.dtb.write_accesses 153403710 # DTB write accesses +system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 167931274 # DTB read accesses +system.cpu.dtb.write_accesses 152703853 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 321994896 # DTB hits -system.cpu.dtb.misses 215397 # DTB misses -system.cpu.dtb.accesses 322210293 # DTB accesses +system.cpu.dtb.hits 320423806 # DTB hits +system.cpu.dtb.misses 211321 # DTB misses +system.cpu.dtb.accesses 320635127 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,91 +462,97 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 123370 # Table walker walks requested -system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated +system.cpu.itb.walker.walks 122916 # Table walker walks requested +system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 898375907 # ITB inst hits -system.cpu.itb.inst_misses 123370 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 894030670 # ITB inst hits +system.cpu.itb.inst_misses 122916 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 898499277 # ITB inst accesses -system.cpu.itb.hits 898375907 # DTB hits -system.cpu.itb.misses 123370 # DTB misses -system.cpu.itb.accesses 898499277 # DTB accesses -system.cpu.numCycles 103642314342 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 894153586 # ITB inst accesses +system.cpu.itb.hits 894030670 # DTB hits +system.cpu.itb.misses 122916 # DTB misses +system.cpu.itb.accesses 894153586 # DTB accesses +system.cpu.numCycles 103648924201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 897823750 # Number of instructions committed -system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 968534129 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses -system.cpu.num_func_calls 53156799 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 137185420 # number of instructions that are conditional controls -system.cpu.num_int_insts 968534129 # number of integer instructions -system.cpu.num_fp_insts 900653 # number of float instructions -system.cpu.num_int_register_reads 1413400107 # number of times the integer registers were read -system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read -system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written -system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written -system.cpu.num_mem_refs 321978685 # number of memory refs -system.cpu.num_load_insts 168640749 # Number of load instructions -system.cpu.num_store_insts 153337936 # Number of store instructions -system.cpu.num_idle_cycles 100474351324.032059 # Number of idle cycles -system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969434 # Percentage of idle cycles -system.cpu.Branches 200551202 # Number of branches fetched +system.cpu.committedInsts 893481288 # Number of instructions committed +system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses +system.cpu.num_func_calls 52999943 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls +system.cpu.num_int_insts 963989017 # number of integer instructions +system.cpu.num_fp_insts 895873 # number of float instructions +system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read +system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written +system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read +system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written +system.cpu.num_mem_refs 320407593 # number of memory refs +system.cpu.num_load_insts 167768846 # Number of load instructions +system.cpu.num_store_insts 152638747 # Number of store instructions +system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles +system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969376 # Percentage of idle cycles +system.cpu.Branches 199584978 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -590,126 +575,126 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Cl system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 168640749 15.98% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 153337936 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1055583241 # Class of executed instruction +system.cpu.op_class::total 1050473844 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10281150 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.969700 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 311526777 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10281662 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.969700 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10213653 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1297920552 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1297920552 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 157560037 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 157560037 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145486469 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145486469 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 397138 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 397138 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335387 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 335387 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3699332 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3699332 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4002690 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4002690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 303046506 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 303046506 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 303443644 # number of overall hits -system.cpu.dcache.overall_hits::total 303443644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5342305 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5342305 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2238545 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238545 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1309963 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1309963 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232790 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1232790 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 305057 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 305057 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits +system.cpu.dcache.overall_hits::total 301988446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7580850 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7580850 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8890813 # number of overall misses -system.cpu.dcache.overall_misses::total 8890813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83595802503 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83595802503 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64185055523 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64185055523 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27578524507 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27578524507 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4441396750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4441396750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 147780858026 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 147780858026 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 147780858026 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 147780858026 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162902342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162902342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147725014 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147725014 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707101 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707101 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568177 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1568177 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004389 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4004389 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4002692 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4002692 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 310627356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 310627356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 312334457 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 312334457 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032795 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032795 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015153 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015153 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767361 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.767361 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786129 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786129 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028466 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028466 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15647.890284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15647.890284 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28672.667077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28672.667077 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22370.821070 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22370.821070 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14559.235651 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14559.235651 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19493.969413 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19493.969413 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16621.748543 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16621.748543 # average overall miss latency +system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses +system.cpu.dcache.overall_misses::total 8832117 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -718,88 +703,88 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7913457 # number of writebacks -system.cpu.dcache.writebacks::total 7913457 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7211 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21165 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 71123 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 71123 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 28376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 28376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 28376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 28376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5335094 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5335094 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2217380 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2217380 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1308216 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1308216 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232790 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232790 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233934 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 233934 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks +system.cpu.dcache.writebacks::total 7878976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7552474 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7552474 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8860690 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8860690 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72364530247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 72364530247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58930269477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58930269477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19541293498 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19541293498 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25112944493 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25112944493 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2872283000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2872283000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131294799724 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 131294799724 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150836093222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 150836093222 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727964499 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727964499 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573385250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573385250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301349749 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301349749 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015010 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015010 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766338 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766338 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786129 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786129 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024314 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024314 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028369 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028369 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13563.871648 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13563.871648 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26576.531527 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26576.531527 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14937.360113 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14937.360113 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20370.821059 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20370.821059 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12278.176751 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12278.176751 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17384.343160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17384.343160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17023.064030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17023.064030 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -807,59 +792,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13791662 # number of replacements -system.cpu.icache.tags.tagsinuse 511.892960 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 884583728 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13792174 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.136642 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31822438250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.892960 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999791 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999791 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13753173 # number of replacements +system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 912168086 # Number of tag accesses -system.cpu.icache.tags.data_accesses 912168086 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 884583728 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 884583728 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 884583728 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 884583728 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 884583728 # number of overall hits -system.cpu.icache.overall_hits::total 884583728 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13792179 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13792179 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13792179 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13792179 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13792179 # number of overall misses -system.cpu.icache.overall_misses::total 13792179 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 184446403226 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 184446403226 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 184446403226 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 184446403226 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 184446403226 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 184446403226 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 898375907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 898375907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 898375907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 898375907 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 898375907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 898375907 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13373.260543 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13373.260543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13373.260543 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13373.260543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13373.260543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13373.260543 # average overall miss latency +system.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses +system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits +system.cpu.icache.overall_hits::total 880276980 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13753690 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses +system.cpu.icache.overall_misses::total 13753690 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 184520052183 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 184520052183 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 184520052183 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 184520052183 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 184520052183 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 894030670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 894030670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 894030670 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 894030670 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 894030670 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 894030670 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015384 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015384 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015384 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015384 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015384 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015384 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13416.039782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13416.039782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -868,208 +853,209 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13792179 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13792179 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13792179 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13792179 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13792179 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13792179 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 156833610274 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 156833610274 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 156833610274 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 156833610274 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 156833610274 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 156833610274 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2831639000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2831639000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2831639000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 2831639000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015352 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015352 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015352 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.198871 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.198871 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.198871 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.198871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.198871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.198871 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1330655 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65236.148872 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27755474 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1393687 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 19.915142 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6373825000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 38814.158351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 314.572055 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 427.557921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6384.961919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19294.898626 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.592257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004800 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006524 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.097427 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.294417 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62787 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 411 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2448 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5435 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54454 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958054 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 265729281 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 265729281 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 380608 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 251172 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 13712819 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6587464 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 20932063 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7913457 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7913457 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 720904 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 720904 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 10014 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 10014 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1637190 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1637190 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 380608 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 251172 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13712819 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8224654 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 22569253 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 380608 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 251172 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13712819 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8224654 # number of overall hits -system.cpu.l2cache.overall_hits::total 22569253 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4179 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4227 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 79360 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 289780 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 377546 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 511886 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 511886 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 35708 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 35708 # number of UpgradeReq misses +system.cpu.l2cache.tags.replacements 1292250 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.773838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6468.758735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.585064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004703 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006420 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.301380 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 297 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62733 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2458 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54401 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004532 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.957230 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 264471216 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 264471216 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 371629 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250715 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 13674158 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6553954 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 20850456 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7878976 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7878976 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 723057 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 723057 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9863 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9863 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1639498 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1639498 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 371629 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 250715 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 13674158 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8193452 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 22489954 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 371629 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 250715 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 13674158 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8193452 # number of overall hits +system.cpu.l2cache.overall_hits::total 22489954 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4157 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4054 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 79532 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 275030 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362773 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509738 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 509738 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 35651 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 35651 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 534468 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 534468 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4179 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 4227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 79360 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 824248 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 912014 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4179 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 4227 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 79360 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 824248 # number of overall misses -system.cpu.l2cache.overall_misses::total 912014 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 326739750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 334789750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5912719487 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22025051995 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28599300982 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 117495 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 117495 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 415763234 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 415763234 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 39424784684 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 39424784684 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 326739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 334789750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 5912719487 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 61449836679 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 68024085666 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 326739750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 334789750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 5912719487 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 61449836679 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 68024085666 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 384787 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 255399 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 13792179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 6877244 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 21309609 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7913457 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7913457 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232790 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1232790 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45722 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 45722 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 512916 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 512916 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 4157 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 4054 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 79532 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 787946 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 875689 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 4157 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 4054 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 79532 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 787946 # number of overall misses +system.cpu.l2cache.overall_misses::total 875689 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 357827500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 356872250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6528298780 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22994549799 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30237548329 # number of ReadReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 123996 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 554901623 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 554901623 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41601774937 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41601774937 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 357827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 356872250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6528298780 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 64596324736 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 71839323266 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 357827500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 356872250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6528298780 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 64596324736 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 71839323266 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 375786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254769 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 13753690 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 6828984 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 21213229 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7878976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7878976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232795 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1232795 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45514 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 45514 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2171658 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2171658 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 384787 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 255399 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 13792179 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9048902 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 23481267 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 384787 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 255399 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 13792179 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9048902 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 23481267 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010861 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016551 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005754 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.017717 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.415226 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.415226 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780981 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780981 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2152414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2152414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 375786 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 254769 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 13753690 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8981398 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 23365643 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 375786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 254769 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 13753690 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8981398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 23365643 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011062 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005783 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.040274 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.017101 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413482 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413482 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783297 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783297 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.246111 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.246111 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010861 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016551 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005754 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.091088 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.038840 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010861 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016551 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005754 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.091088 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.038840 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78186.109117 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79202.685119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74505.033858 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76006.114967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75750.507175 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.229534 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.229534 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11643.419794 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11643.419794 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73764.537230 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73764.537230 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78186.109117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79202.685119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74505.033858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74552.606350 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74586.668259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78186.109117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79202.685119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74505.033858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74552.606350 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74586.668259 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238298 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.238298 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011062 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087731 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.037478 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011062 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005783 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087731 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.037478 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383 # average ReadReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.243254 # average WriteInvalidateReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.243254 # average WriteInvalidateReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82037.485073 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82037.485073 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1078,108 +1064,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1137707 # number of writebacks -system.cpu.l2cache.writebacks::total 1137707 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4179 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4227 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79360 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 289780 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 377546 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 511886 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 511886 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35708 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35708 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1107523 # number of writebacks +system.cpu.l2cache.writebacks::total 1107523 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4157 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4054 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 275030 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 362773 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509738 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 509738 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35651 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 35651 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 534468 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 534468 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4179 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 79360 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 824248 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 912014 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4179 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 79360 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 824248 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 912014 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 274533250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281888250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 4919274513 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18395024005 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23870720018 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 11039301007 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 11039301007 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 357176707 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 357176707 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32752998316 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32752998316 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 274533250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281888250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 4919274513 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51148022321 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 56623718334 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 274533250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281888250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 4919274513 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51148022321 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 56623718334 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2248902500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5288010501 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7536913001 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5166015500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5166015500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2248902500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454026001 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12702928501 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.042136 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017717 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.415226 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.415226 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780981 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780981 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 512916 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 512916 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4054 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 625079648 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35188398563 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35188398563 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 305614500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 305848750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5531016720 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54736808264 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 60879288234 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 305614500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 305848750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5531016720 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54736808264 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 60879288234 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2585776000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279091500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.038840 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.038840 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1189,62 +1175,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 473368 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 470306 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40403 # Transaction distribution -system.iobus.trans_dist::ReadResp 40403 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40333 # Transaction distribution +system.iobus.trans_dist::ReadResp 40333 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1259,13 +1243,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1280,13 +1264,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1314,71 +1298,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115482 # number of replacements -system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use +system.iocache.tags.replacements 115493 # number of replacements +system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039866 # Number of tag accesses -system.iocache.tags.data_accesses 1039866 # Number of data accesses +system.iocache.tags.tag_accesses 1039965 # Number of tag accesses +system.iocache.tags.data_accesses 1039965 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses -system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses +system.iocache.demand_misses::total 8888 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8837 # number of overall misses -system.iocache.overall_misses::total 8877 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8848 # number of overall misses +system.iocache.overall_misses::total 8888 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1392,55 +1376,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1454,71 +1438,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 463332 # Transaction distribution -system.membus.trans_dist::ReadResp 463332 # Transaction distribution -system.membus.trans_dist::WriteReq 33872 # Transaction distribution -system.membus.trans_dist::WriteResp 33872 # Transaction distribution -system.membus.trans_dist::Writeback 1244337 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution +system.membus.trans_dist::ReadReq 448489 # Transaction distribution +system.membus.trans_dist::ReadResp 448489 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::Writeback 1214153 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution -system.membus.trans_dist::ReadExReq 533903 # Transaction distribution -system.membus.trans_dist::ReadExResp 533903 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution +system.membus.trans_dist::ReadExReq 512353 # Transaction distribution +system.membus.trans_dist::ReadExResp 512353 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3539 # Total snoops (count) -system.membus.snoop_fanout::samples 2819489 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3324 # Total snoops (count) +system.membus.snoop_fanout::samples 2750930 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2819489 # Request fanout histogram -system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2750930 # Request fanout histogram +system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 5213927ce..f36b7859c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111151 # Number of seconds simulated -sim_ticks 51111150553500 # Number of ticks simulated -final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111153 # Number of seconds simulated +sim_ticks 51111152682000 # Number of ticks simulated +final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151312 # Simulator instruction rate (inst/s) -host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59753764865 # Simulator tick rate (ticks/s) -host_mem_usage 728116 # Number of bytes of host memory used -host_seconds 855.36 # Real time elapsed on the host -sim_insts 984789519 # Number of instructions simulated -sim_ops 1157289961 # Number of ops (including micro ops) simulated +host_inst_rate 1095499 # Simulator instruction rate (inst/s) +host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56869697369 # Simulator tick rate (ticks/s) +host_mem_usage 728040 # Number of bytes of host memory used +host_seconds 898.74 # Real time elapsed on the host +sim_insts 984570519 # Number of instructions simulated +sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 200576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 185152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3380276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 37995016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 209984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 187968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2175808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 37325312 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 82097788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3380276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2175808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5556084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298276 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3134 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2893 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 93224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 593685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 33997 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 583208 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1323198 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613714 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616287 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 66136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 743380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 730277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1606260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 66136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42570 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108706 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020649 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 66136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 743783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 730277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3627311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -121,45 +121,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 144982 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 144734 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91965302 # DTB read hits -system.cpu0.dtb.read_misses 107321 # DTB read misses -system.cpu0.dtb.write_hits 84365950 # DTB write hits -system.cpu0.dtb.write_misses 37661 # DTB write misses +system.cpu0.dtb.read_hits 91873100 # DTB read hits +system.cpu0.dtb.read_misses 107254 # DTB read misses +system.cpu0.dtb.write_hits 84300346 # DTB write hits +system.cpu0.dtb.write_misses 37480 # DTB write misses system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56687 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4951 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11060 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92072623 # DTB read accesses -system.cpu0.dtb.write_accesses 84403611 # DTB write accesses +system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91980354 # DTB read accesses +system.cpu0.dtb.write_accesses 84337826 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176331252 # DTB hits -system.cpu0.dtb.misses 144982 # DTB misses -system.cpu0.dtb.accesses 176476234 # DTB accesses +system.cpu0.dtb.hits 176173446 # DTB hits +system.cpu0.dtb.misses 144734 # DTB misses +system.cpu0.dtb.accesses 176318180 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -189,219 +189,219 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 70785 # Table walker walks requested -system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 70623 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493804573 # ITB inst hits -system.cpu0.itb.inst_misses 70785 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 493558289 # ITB inst hits +system.cpu0.itb.inst_misses 70623 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40296 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493875358 # ITB inst accesses -system.cpu0.itb.hits 493804573 # DTB hits -system.cpu0.itb.misses 70785 # DTB misses -system.cpu0.itb.accesses 493875358 # DTB accesses -system.cpu0.numCycles 98036815347 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses +system.cpu0.itb.hits 493558289 # DTB hits +system.cpu0.itb.misses 70623 # DTB misses +system.cpu0.itb.accesses 493628912 # DTB accesses +system.cpu0.numCycles 98036732821 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 493589418 # Number of instructions committed -system.cpu0.committedOps 579610206 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 531010156 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 454321 # Number of float alu accesses -system.cpu0.num_func_calls 28538505 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76169999 # number of instructions that are conditional controls -system.cpu0.num_int_insts 531010156 # number of integer instructions -system.cpu0.num_fp_insts 454321 # number of float instructions -system.cpu0.num_int_register_reads 784912346 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421695474 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 742936 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 362460 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132983142 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132661017 # number of times the CC registers were written -system.cpu0.num_mem_refs 176454648 # number of memory refs -system.cpu0.num_load_insts 92059270 # Number of load instructions -system.cpu0.num_store_insts 84395378 # Number of store instructions -system.cpu0.num_idle_cycles 96925999292.039536 # Number of idle cycles -system.cpu0.num_busy_cycles 1110816054.960464 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011331 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988669 # Percentage of idle cycles -system.cpu0.Branches 110347037 # Number of branches fetched +system.cpu0.committedInsts 493343054 # Number of instructions committed +system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses +system.cpu0.num_func_calls 28504103 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls +system.cpu0.num_int_insts 530703417 # number of integer instructions +system.cpu0.num_fp_insts 453665 # number of float instructions +system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read +system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written +system.cpu0.num_mem_refs 176296730 # number of memory refs +system.cpu0.num_load_insts 91967123 # Number of load instructions +system.cpu0.num_store_insts 84329607 # Number of store instructions +system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles +system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles +system.cpu0.Branches 110281342 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 402205176 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1169973 0.20% 69.56% # Class of executed instruction -system.cpu0.op_class::IntDiv 50634 0.01% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 52759 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 92059270 15.87% 85.45% # Class of executed instruction -system.cpu0.op_class::MemWrite 84395378 14.55% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction +system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction +system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 579933190 # Class of executed instruction +system.cpu0.op_class::total 579643698 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 11615783 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 340859093 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.343185 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 11612141 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.345192 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 265.932740 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 246.066978 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.519400 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.480600 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 264.268132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 247.731587 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.516149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.483851 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1421517922 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1421517922 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 85766676 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 85839710 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171606386 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79896763 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79669373 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159566136 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208546 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215430 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 423976 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146337 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191461 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2132895 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2177393 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4310288 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2256573 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2306673 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165663439 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165509083 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 331172522 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165871985 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165724513 # number of overall hits -system.cpu0.dcache.overall_hits::total 331596498 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3019403 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2994182 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6013585 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1302154 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1267314 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2569468 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789306 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 795194 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1584500 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766302 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 478957 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 124586 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 130174 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 254760 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1421165468 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1421165468 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85681160 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 85885886 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 171567046 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79835128 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 79687740 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 159522868 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208530 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215328 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 423858 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146037 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191672 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2127418 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2183031 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 4310449 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2250403 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2312061 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165516288 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 165573626 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 331089914 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165724818 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 165788954 # number of overall hits +system.cpu0.dcache.overall_hits::total 331513772 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3015225 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2995068 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6010293 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1305618 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1264641 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2570259 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 792908 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 791180 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1584088 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 765143 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 480206 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 123898 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129919 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 253817 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4321557 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 4261496 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 8583053 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5110863 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 5056690 # number of overall misses -system.cpu0.dcache.overall_misses::total 10167553 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88786079 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88833892 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81198917 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 80936687 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 997852 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1010624 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 2008476 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 912639 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 670418 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2257481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2307567 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2256573 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2306674 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169984996 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 169770579 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170982848 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 170781203 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 341764051 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033705 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033856 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016037 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015658 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791005 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786835 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788907 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839655 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714415 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055188 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056412 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055807 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 4320843 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 4259709 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 8580552 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5113751 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 5050889 # number of overall misses +system.cpu0.dcache.overall_misses::total 10164640 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88696385 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 88880954 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81140746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 80952381 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1001438 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1006508 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 2007946 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 911180 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 671878 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2251316 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2312950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2250403 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2312062 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169837131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 169833335 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170838569 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 170839843 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 341678412 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033995 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033698 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033846 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016091 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015622 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025423 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025101 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029891 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029609 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025441 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025082 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029933 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029565 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,63 +410,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8923646 # number of writebacks -system.cpu0.dcache.writebacks::total 8923646 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 8921315 # number of writebacks +system.cpu0.dcache.writebacks::total 8921315 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14287218 # number of replacements +system.cpu0.icache.tags.replacements 14295641 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 971093500 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 970865862 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 267.813987 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 244.170612 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523074 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476896 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523927 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476043 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 999668970 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 999668970 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 486710504 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 484382996 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 971093500 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 486710504 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 484382996 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 971093500 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 486710504 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 484382996 # number of overall hits -system.cpu0.icache.overall_hits::total 971093500 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7158773 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 7128962 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14287735 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7158773 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 7128962 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14287735 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7158773 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 7128962 # number of overall misses -system.cpu0.icache.overall_misses::total 14287735 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 493869277 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 491511958 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 493869277 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 491511958 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 493869277 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 491511958 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014495 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014504 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014495 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014504 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014495 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014504 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 999458178 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 999458178 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 486466334 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 484399528 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 970865862 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 486466334 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 484399528 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 970865862 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 486466334 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 484399528 # number of overall hits +system.cpu0.icache.overall_hits::total 970865862 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7156510 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7139648 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14296158 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7156510 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7139648 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14296158 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7156510 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7139648 # number of overall misses +system.cpu0.icache.overall_misses::total 14296158 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 493622844 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 491539176 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 493622844 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 491539176 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 493622844 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 491539176 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014498 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014525 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014498 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014525 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014498 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014525 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,45 +505,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 143312 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 143589 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 92072581 # DTB read hits -system.cpu1.dtb.read_misses 106555 # DTB read misses -system.cpu1.dtb.write_hits 83907281 # DTB write hits -system.cpu1.dtb.write_misses 36757 # DTB write misses +system.cpu1.dtb.read_hits 92120843 # DTB read hits +system.cpu1.dtb.read_misses 106565 # DTB read misses +system.cpu1.dtb.write_hits 83929435 # DTB write hits +system.cpu1.dtb.write_misses 37024 # DTB write misses system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56101 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4637 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10591 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92179136 # DTB read accesses -system.cpu1.dtb.write_accesses 83944038 # DTB write accesses +system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92227408 # DTB read accesses +system.cpu1.dtb.write_accesses 83966459 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175979862 # DTB hits -system.cpu1.dtb.misses 143312 # DTB misses -system.cpu1.dtb.accesses 176123174 # DTB accesses +system.cpu1.dtb.hits 176050278 # DTB hits +system.cpu1.dtb.misses 143589 # DTB misses +system.cpu1.dtb.accesses 176193867 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -573,113 +573,113 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 69790 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 69863 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 491448225 # ITB inst hits -system.cpu1.itb.inst_misses 69790 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 491475383 # ITB inst hits +system.cpu1.itb.inst_misses 69863 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40454 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 491518015 # ITB inst accesses -system.cpu1.itb.hits 491448225 # DTB hits -system.cpu1.itb.misses 69790 # DTB misses -system.cpu1.itb.accesses 491518015 # DTB accesses -system.cpu1.numCycles 97463256917 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses +system.cpu1.itb.hits 491475383 # DTB hits +system.cpu1.itb.misses 69863 # DTB misses +system.cpu1.itb.accesses 491545246 # DTB accesses +system.cpu1.numCycles 97463064529 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 491200101 # Number of instructions committed -system.cpu1.committedOps 577679755 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 529688376 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 426452 # Number of float alu accesses -system.cpu1.num_func_calls 28536988 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75796446 # number of instructions that are conditional controls -system.cpu1.num_int_insts 529688376 # number of integer instructions -system.cpu1.num_fp_insts 426452 # number of float instructions -system.cpu1.num_int_register_reads 779402047 # number of times the integer registers were read -system.cpu1.num_int_register_writes 420937852 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 676063 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 385332 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131460069 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 131204494 # number of times the CC registers were written -system.cpu1.num_mem_refs 176098133 # number of memory refs -system.cpu1.num_load_insts 92164972 # Number of load instructions -system.cpu1.num_store_insts 83933161 # Number of store instructions -system.cpu1.num_idle_cycles 96357264034.410416 # Number of idle cycles -system.cpu1.num_busy_cycles 1105992882.589586 # Number of busy cycles +system.cpu1.committedInsts 491227465 # Number of instructions committed +system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses +system.cpu1.num_func_calls 28552264 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls +system.cpu1.num_int_insts 529752049 # number of integer instructions +system.cpu1.num_fp_insts 427140 # number of float instructions +system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read +system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written +system.cpu1.num_mem_refs 176168876 # number of memory refs +system.cpu1.num_load_insts 92213308 # Number of load instructions +system.cpu1.num_store_insts 83955568 # Number of store instructions +system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles +system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles -system.cpu1.Branches 109788123 # Number of branches fetched +system.cpu1.Branches 109807220 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 400601727 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1185429 0.21% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 51217 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55063 0.01% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::MemRead 92164972 15.95% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 83933161 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction +system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction +system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 577991612 # Class of executed instruction +system.cpu1.op_class::total 578022895 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40296 # Transaction distribution -system.iobus.trans_dist::ReadResp 40296 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.iobus.trans_dist::ReadReq 40246 # Transaction distribution +system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.iobus.trans_dist::WriteReq 136515 # Transaction distribution +system.iobus.trans_dist::WriteResp 29851 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -694,13 +694,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -715,54 +715,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115460 # number of replacements +system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115463 # number of replacements system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses -system.iocache.demand_misses::total 8854 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8814 # number of overall misses -system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -787,198 +787,197 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1726938 # number of replacements -system.l2c.tags.tagsinuse 65261.456077 # Cycle average of tags in use -system.l2c.tags.total_refs 30061688 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1789677 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 16.797270 # Average number of references to valid blocks. +system.l2c.tags.replacements 1722682 # number of replacements +system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use +system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1785979 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 16.834178 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37843.446470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.851039 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 182.256334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3658.181664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9398.442867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 138.187628 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 187.456005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2615.769048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11103.865022 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.577445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.055819 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.143409 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002109 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.039913 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.169432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62493 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54021 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.953568 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 291022560 # Number of tag accesses -system.l2c.tags.data_accesses 291022560 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 283104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 147368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7108650 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3755195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 278245 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 144464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7094952 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3753176 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22565154 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8923646 # number of Writeback hits -system.l2c.Writeback_hits::total 8923646 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347701 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 349614 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 697315 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 5665 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11232 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 860452 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 824150 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1684602 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 283104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 147368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7108650 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4615647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 278245 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 144464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7094952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4577326 # number of demand (read+write) hits -system.l2c.demand_hits::total 24249756 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 283104 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 147368 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7108650 # number of overall hits -system.l2c.overall_hits::cpu0.data 4615647 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 278245 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 144464 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7094952 # number of overall hits -system.l2c.overall_hits::cpu1.data 4577326 # number of overall hits -system.l2c.overall_hits::total 24249756 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3134 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2893 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 50123 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 178100 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3281 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2937 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 34010 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 166374 # number of ReadReq misses -system.l2c.ReadReq_misses::total 440852 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 418601 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 129343 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 547944 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 19998 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20032 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 40030 # number of UpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 37141.097811 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.495240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3601.604762 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9619.799415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.654107 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240500 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2659.657984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11566.852019 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.566728 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.176496 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 63021 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54671 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.961624 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 290964090 # Number of tag accesses +system.l2c.tags.data_accesses 290964090 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7107195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3754972 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 142760 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7104726 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3749259 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22560458 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8921315 # number of Writeback hits +system.l2c.Writeback_hits::total 8921315 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 345123 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 349209 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 694332 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 5687 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11223 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 864873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 827736 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1692609 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 279435 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 145257 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7107195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4619845 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 276854 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 142760 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7104726 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4576995 # number of demand (read+write) hits +system.l2c.demand_hits::total 24253067 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 279435 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 145257 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7107195 # number of overall hits +system.l2c.overall_hits::cpu0.data 4619845 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 276854 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 142760 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7104726 # number of overall hits +system.l2c.overall_hits::cpu1.data 4576995 # number of overall hits +system.l2c.overall_hits::total 24253067 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3178 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2937 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 49315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 177059 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 34922 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 166908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 440517 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 420020 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 130997 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 551017 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 19994 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19925 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 39919 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 416039 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 417565 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 833604 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3134 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2893 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 50123 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 594139 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2937 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 34010 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 583939 # number of demand (read+write) misses -system.l2c.demand_misses::total 1274456 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3134 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2893 # number of overall misses -system.l2c.overall_misses::cpu0.inst 50123 # number of overall misses -system.l2c.overall_misses::cpu0.data 594139 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3281 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2937 # number of overall misses -system.l2c.overall_misses::cpu1.inst 34010 # number of overall misses -system.l2c.overall_misses::cpu1.data 583939 # number of overall misses -system.l2c.overall_misses::total 1274456 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 286238 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 150261 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 7158773 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3933295 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 281526 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 147401 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 7128962 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3919550 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 23006006 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 8923646 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 8923646 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 766302 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 478957 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1245259 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25663 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 25599 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51262 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 415064 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 411444 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 826508 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3178 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2937 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 49315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 592123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3256 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2942 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34922 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 578352 # number of demand (read+write) misses +system.l2c.demand_misses::total 1267025 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3178 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2937 # number of overall misses +system.l2c.overall_misses::cpu0.inst 49315 # number of overall misses +system.l2c.overall_misses::cpu0.data 592123 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2942 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34922 # number of overall misses +system.l2c.overall_misses::cpu1.data 578352 # number of overall misses +system.l2c.overall_misses::total 1267025 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 282613 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 148194 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 7156510 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 3932031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 280110 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 145702 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 7139648 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 3916167 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 23000975 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 765143 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 480206 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25681 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51142 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1276491 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1241715 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2518206 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 286238 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 150261 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 7158773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 5209786 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 281526 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 147401 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 7128962 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 5161265 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 25524212 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 286238 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 150261 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 7158773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 5209786 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 281526 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 147401 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7128962 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 5161265 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 25524212 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019253 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.007002 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.045280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019925 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004771 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.042447 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.019162 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.546261 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.270051 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.440024 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779254 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782531 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.780890 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 1279937 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1239180 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 282613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 148194 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7156510 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 5211968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 280110 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 145702 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7139648 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 5155347 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25520092 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 282613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 148194 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7156510 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 5211968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 280110 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 145702 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7139648 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 5155347 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25520092 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019819 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.006891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045030 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020192 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.042620 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.548943 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.272793 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.442460 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778552 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.325924 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.336281 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019253 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.007002 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.114043 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019925 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004771 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.113139 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049931 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019253 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.007002 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.114043 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019925 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004771 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.113139 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049931 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.324285 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.332029 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.113608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.020192 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049648 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.113608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.020192 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112185 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049648 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -987,49 +986,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1507083 # number of writebacks -system.l2c.writebacks::total 1507083 # number of writebacks +system.l2c.writebacks::writebacks 1503417 # number of writebacks +system.l2c.writebacks::total 1503417 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526435 # Transaction distribution -system.membus.trans_dist::ReadResp 526435 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1613714 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 654603 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 654603 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40598 # Transaction distribution +system.membus.trans_dist::ReadReq 526050 # Transaction distribution +system.membus.trans_dist::ReadResp 526050 # Transaction distribution +system.membus.trans_dist::WriteReq 33606 # Transaction distribution +system.membus.trans_dist::WriteResp 33606 # Transaction distribution +system.membus.trans_dist::Writeback 1610048 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 657676 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 657676 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40599 # Transaction distribution -system.membus.trans_dist::ReadExReq 833044 # Transaction distribution -system.membus.trans_dist::ReadExResp 833044 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution +system.membus.trans_dist::ReadExReq 825949 # Transaction distribution +system.membus.trans_dist::ReadExResp 825949 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5323323 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5452833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5790500 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5310719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5439911 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5777584 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 213243872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 213413240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227630584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212730400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 212899450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3591663 # Request fanout histogram +system.membus.snoop_fanout::samples 3583531 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3591663 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3591663 # Request fanout histogram +system.membus.snoop_fanout::total 3583531 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1072,43 +1071,41 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 23461417 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23461417 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51262 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51263 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28661720 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32393430 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 63543360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3330800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6622040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2239287552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 116335 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 36238577 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003188 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.056370 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 116338 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 36123059 99.68% 99.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 36238577 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b290fab5a..3b1b184c8 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,129 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.188464 # Number of seconds simulated -sim_ticks 5188464227000 # Number of ticks simulated -final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.184750 # Number of seconds simulated +sim_ticks 5184749789500 # Number of ticks simulated +final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671592 # Simulator instruction rate (inst/s) -host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27056983658 # Simulator tick rate (ticks/s) -host_mem_usage 641928 # Number of bytes of host memory used -host_seconds 191.76 # Real time elapsed on the host -sim_insts 128784844 # Number of instructions simulated -sim_ops 248241672 # Number of ops (including micro ops) simulated +host_inst_rate 858252 # Simulator instruction rate (inst/s) +host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34581252938 # Simulator tick rate (ticks/s) +host_mem_usage 653812 # Number of bytes of host memory used +host_seconds 149.93 # Real time elapsed on the host +sim_insts 128677191 # Number of instructions simulated +sim_ops 248045844 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory -system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9871616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 827904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 827904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8126080 # Number of bytes written to this memory +system.physmem.bytes_written::total 8126080 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141286 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140860 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126962 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 154244 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126970 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126970 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1742771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1908024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1566083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1566083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1566083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1903972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1567304 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1567304 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1567304 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1742771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3474107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154683 # Number of read requests accepted -system.physmem.writeReqs 173682 # Number of write requests accepted -system.physmem.readBursts 154683 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9893504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 10954816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9899712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11115648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2485 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1609 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10173 # Per bank write bursts -system.physmem.perBankRdBursts::1 9740 # Per bank write bursts -system.physmem.perBankRdBursts::2 9593 # Per bank write bursts -system.physmem.perBankRdBursts::3 9430 # Per bank write bursts -system.physmem.perBankRdBursts::4 10001 # Per bank write bursts -system.physmem.perBankRdBursts::5 9691 # Per bank write bursts -system.physmem.perBankRdBursts::6 9399 # Per bank write bursts -system.physmem.perBankRdBursts::7 9276 # Per bank write bursts -system.physmem.perBankRdBursts::8 9154 # Per bank write bursts -system.physmem.perBankRdBursts::9 9223 # Per bank write bursts -system.physmem.perBankRdBursts::10 9471 # Per bank write bursts -system.physmem.perBankRdBursts::11 9338 # Per bank write bursts -system.physmem.perBankRdBursts::12 9899 # Per bank write bursts -system.physmem.perBankRdBursts::13 10266 # Per bank write bursts -system.physmem.perBankRdBursts::14 9992 # Per bank write bursts -system.physmem.perBankRdBursts::15 9940 # Per bank write bursts -system.physmem.perBankWrBursts::0 11451 # Per bank write bursts -system.physmem.perBankWrBursts::1 10885 # Per bank write bursts -system.physmem.perBankWrBursts::2 11361 # Per bank write bursts -system.physmem.perBankWrBursts::3 10717 # Per bank write bursts -system.physmem.perBankWrBursts::4 11001 # Per bank write bursts -system.physmem.perBankWrBursts::5 10578 # Per bank write bursts -system.physmem.perBankWrBursts::6 10603 # Per bank write bursts -system.physmem.perBankWrBursts::7 9872 # Per bank write bursts -system.physmem.perBankWrBursts::8 10400 # Per bank write bursts -system.physmem.perBankWrBursts::9 10659 # Per bank write bursts -system.physmem.perBankWrBursts::10 10851 # Per bank write bursts -system.physmem.perBankWrBursts::11 10912 # Per bank write bursts -system.physmem.perBankWrBursts::12 10837 # Per bank write bursts -system.physmem.perBankWrBursts::13 10879 # Per bank write bursts -system.physmem.perBankWrBursts::14 9964 # Per bank write bursts -system.physmem.perBankWrBursts::15 10199 # Per bank write bursts +system.physmem.bw_total::cpu.inst 159681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3471276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154244 # Number of read requests accepted +system.physmem.writeReqs 173690 # Number of write requests accepted +system.physmem.readBursts 154244 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9927 # Per bank write bursts +system.physmem.perBankRdBursts::1 9220 # Per bank write bursts +system.physmem.perBankRdBursts::2 9906 # Per bank write bursts +system.physmem.perBankRdBursts::3 9744 # Per bank write bursts +system.physmem.perBankRdBursts::4 9716 # Per bank write bursts +system.physmem.perBankRdBursts::5 9338 # Per bank write bursts +system.physmem.perBankRdBursts::6 9475 # Per bank write bursts +system.physmem.perBankRdBursts::7 9515 # Per bank write bursts +system.physmem.perBankRdBursts::8 8926 # Per bank write bursts +system.physmem.perBankRdBursts::9 9405 # Per bank write bursts +system.physmem.perBankRdBursts::10 9702 # Per bank write bursts +system.physmem.perBankRdBursts::11 9402 # Per bank write bursts +system.physmem.perBankRdBursts::12 9788 # Per bank write bursts +system.physmem.perBankRdBursts::13 10193 # Per bank write bursts +system.physmem.perBankRdBursts::14 9798 # Per bank write bursts +system.physmem.perBankRdBursts::15 10094 # Per bank write bursts +system.physmem.perBankWrBursts::0 9407 # Per bank write bursts +system.physmem.perBankWrBursts::1 8748 # Per bank write bursts +system.physmem.perBankWrBursts::2 9677 # Per bank write bursts +system.physmem.perBankWrBursts::3 9718 # Per bank write bursts +system.physmem.perBankWrBursts::4 9428 # Per bank write bursts +system.physmem.perBankWrBursts::5 9072 # Per bank write bursts +system.physmem.perBankWrBursts::6 8868 # Per bank write bursts +system.physmem.perBankWrBursts::7 9192 # Per bank write bursts +system.physmem.perBankWrBursts::8 8615 # Per bank write bursts +system.physmem.perBankWrBursts::9 8711 # Per bank write bursts +system.physmem.perBankWrBursts::10 9601 # Per bank write bursts +system.physmem.perBankWrBursts::11 9113 # Per bank write bursts +system.physmem.perBankWrBursts::12 9702 # Per bank write bursts +system.physmem.perBankWrBursts::13 9421 # Per bank write bursts +system.physmem.perBankWrBursts::14 9363 # Per bank write bursts +system.physmem.perBankWrBursts::15 8959 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5188464163500 # Total gap between requests +system.physmem.numWrRetry 68 # Number of times write queue was full causing retry +system.physmem.totGap 5184749726000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154683 # Read request sizes (log2) +system.physmem.readPktSize::6 154244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173690 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see @@ -156,209 +152,194 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 356.003142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.252442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.966719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19491 33.28% 33.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13719 23.43% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5713 9.76% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3485 5.95% 72.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2346 4.01% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1652 2.82% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1138 1.94% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1007 1.72% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10011 17.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58562 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.303774 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 600.449814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6359 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 338.502226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.067588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.604467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19329 33.88% 33.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13844 24.27% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5928 10.39% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3298 5.78% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2346 4.11% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.76% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1245 2.18% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 971 1.70% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8513 14.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57050 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.117303 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 658.027323 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5293 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads -system.physmem.totQLat 1439298500 # Total ticks spent queuing -system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.879675 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.284410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 52.982511 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4909 92.73% 92.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 99 1.87% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 16 0.30% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 5 0.09% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 10 0.19% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 12 0.23% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 21 0.40% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.30% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 28 0.53% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.11% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 43 0.81% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.62% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 9 0.17% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 9 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.13% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.06% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 17 0.32% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.28% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads +system.physmem.totQLat 1425327951 # Total ticks spent queuing +system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 127137 # Number of row buffer hits during reads -system.physmem.writeRowHits 140055 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes -system.physmem.avgGap 15800904.98 # Average gap between requests -system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.773100 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states -system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states +system.physmem.avgWrQLen 22.98 # Average write queue length when enqueuing +system.physmem.readRowHits 126892 # Number of row buffer hits during reads +system.physmem.writeRowHits 117801 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes +system.physmem.avgGap 15810345.15 # Average gap between requests +system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.758961 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states +system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.787680 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states -system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states +system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3467467313340 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.782314 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4978313509331 # Time in different power states +system.physmem_1.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33303731919 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10376928454 # number of cpu cycles simulated +system.cpu.numCycles 10369499579 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128784844 # Number of instructions committed -system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses +system.cpu.committedInsts 128677191 # Number of instructions committed +system.cpu.committedOps 248045844 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232619140 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2318021 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls -system.cpu.num_int_insts 232811079 # number of integer instructions +system.cpu.num_func_calls 2317433 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23196735 # number of instructions that are conditional controls +system.cpu.num_int_insts 232619140 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read -system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written +system.cpu.num_int_register_reads 435790308 # number of times the integer registers were read +system.cpu.num_int_register_writes 198379629 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written -system.cpu.num_mem_refs 22376754 # number of memory refs -system.cpu.num_load_insts 13962110 # Number of load instructions -system.cpu.num_store_insts 8414644 # Number of store instructions -system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles -system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942354 # Percentage of idle cycles -system.cpu.Branches 26395735 # Number of branches fetched -system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133146964 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95675934 # number of times the CC registers were written +system.cpu.num_mem_refs 22361713 # number of memory refs +system.cpu.num_load_insts 13951833 # Number of load instructions +system.cpu.num_store_insts 8409880 # Number of store instructions +system.cpu.num_idle_cycles 9769324889.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600174689.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057879 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942121 # Percentage of idle cycles +system.cpu.Branches 26373024 # Number of branches fetched +system.cpu.op_class::No_OpClass 172503 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225254349 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140413 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123366 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -385,150 +366,149 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13946864 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8409880 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248243229 # Class of executed instruction +system.cpu.op_class::total 248047391 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1624253 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1622522 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996992 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20153045 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623034 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.416896 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54942250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996992 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88800329 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88800329 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12017170 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12017170 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8080876 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8080876 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59251 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59251 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20098046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20098046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20157297 # number of overall hits -system.cpu.dcache.overall_hits::total 20157297 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 908286 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 908286 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325792 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325792 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402501 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402501 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1234078 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1234078 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636579 # number of overall misses -system.cpu.dcache.overall_misses::total 1636579 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12749281750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12749281750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11335230829 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11335230829 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24084512579 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24084512579 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24084512579 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24084512579 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12925456 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12925456 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461752 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461752 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21332124 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21332124 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21793876 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21793876 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070271 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070271 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038754 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871682 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871682 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057851 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057851 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075094 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075094 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14036.637964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14036.637964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34792.845831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34792.845831 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19516.199607 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19516.199607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14716.376404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14716.376404 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9103 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88765477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88765477 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12014873 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12014873 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077139 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077139 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58853 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58853 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20092012 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20092012 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20150865 # number of overall hits +system.cpu.dcache.overall_hits::total 20150865 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906821 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906821 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 324755 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 324755 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses +system.cpu.dcache.overall_misses::total 1634737 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21785602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21785602 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070178 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070178 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038653 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038653 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 96 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.822917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540563 # number of writebacks -system.cpu.dcache.writebacks::total 1540563 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1539491 # number of writebacks +system.cpu.dcache.writebacks::total 1539491 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9246 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9536 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9536 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316546 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316546 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402467 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402467 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1224542 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1224542 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1627009 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1627009 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10925755250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10925755250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10200095361 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10200095361 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5340766250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5340766250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21125850611 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21125850611 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26466616861 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26466616861 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568413500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568413500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070249 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070249 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037654 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037654 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871609 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871609 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074654 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074654 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.823107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.823107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32223.106155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32223.106155 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.072453 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.072453 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17252.042487 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17252.042487 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16267.037774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16267.037774 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9162 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9162 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9452 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9452 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906531 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906531 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -536,58 +516,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7518 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.053105 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13360 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7533 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.773530 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5157758038000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053105 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315819 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315819 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315350 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315350 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52972 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52972 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13370 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13370 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13370 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13370 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13370 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13370 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8744 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8744 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8744 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8744 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8744 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8744 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92278000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92278000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92278000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 92278000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92278000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 92278000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22114 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22114 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22114 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22114 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22114 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22114 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395406 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395406 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395406 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395406 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395406 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395406 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.293687 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.293687 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 54641 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 54641 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12184 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12184 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12184 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12184 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12184 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12184 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 10091 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 10091 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 10091 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 10091 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 10091 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 10091 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 104642000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 104642000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 104642000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 104642000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 104642000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 104642000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22275 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22275 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22275 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22275 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22275 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22275 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.453019 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.453019 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.453019 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.453019 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.453019 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.453019 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10369.834506 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10369.834506 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10369.834506 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,86 +576,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2885 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2885 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8744 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8744 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8744 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8744 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8744 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8744 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74789500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74789500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74789500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74789500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395406 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395406 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395406 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.236505 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3116 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3116 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 10091 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 10091 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 10091 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 10091 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 10091 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 10091 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 89505500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 89505500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 89505500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 89505500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 89505500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 89505500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.453019 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.453019 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.453019 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8869.834506 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 794079 # number of replacements -system.cpu.icache.tags.tagsinuse 510.347189 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145115978 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 794591 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.629778 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.347189 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 794465 # number of replacements +system.cpu.icache.tags.tagsinuse 510.329327 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144962865 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 794977 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.348502 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161575846250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.329327 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996737 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146705174 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146705174 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145115978 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145115978 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145115978 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145115978 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145115978 # number of overall hits -system.cpu.icache.overall_hits::total 145115978 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 794598 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 794598 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 794598 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 794598 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 794598 # number of overall misses -system.cpu.icache.overall_misses::total 794598 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11149966366 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11149966366 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11149966366 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11149966366 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11149966366 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11149966366 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145910576 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145910576 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145910576 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145910576 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145910576 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145910576 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005446 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005446 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005446 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005446 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005446 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005446 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14032.210459 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14032.210459 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14032.210459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14032.210459 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146552833 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146552833 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144962865 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144962865 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144962865 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144962865 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits +system.cpu.icache.overall_hits::total 144962865 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses +system.cpu.icache.overall_misses::total 794984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -684,88 +664,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794598 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 794598 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 794598 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 794598 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 794598 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 794598 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9555900634 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9555900634 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9555900634 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9555900634 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9555900634 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9555900634 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005446 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005446 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005446 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.081911 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.081911 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.069566 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7987 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.291165 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161163241000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069566 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191848 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191848 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28991 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28991 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7985 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7985 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29974 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29974 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7029 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7029 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7987 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7987 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7987 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7987 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4339 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4339 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4339 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4339 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4339 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4339 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42562750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42562750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42562750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 42562750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42562750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 42562750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12324 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7031 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7031 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7031 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7031 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 5304 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 5304 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 5304 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 5304 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 5304 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 5304 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51550250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51550250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51550250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 51550250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51550250 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 51550250 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12326 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12326 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12326 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12326 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352077 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352077 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352020 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.352020 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352020 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.352020 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9809.345471 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9809.345471 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12335 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12335 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12335 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12335 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.430066 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.430066 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.429996 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.429996 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.429996 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.429996 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9719.127074 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9719.127074 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9719.127074 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,177 +754,163 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 618 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 618 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4339 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4339 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4339 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4339 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4339 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4339 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33883250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33883250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33883250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33883250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33883250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33883250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352077 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352077 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352020 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352020 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7808.999770 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 759 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 759 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 5304 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 5304 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 5304 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 5304 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 5304 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 5304 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 43592750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 43592750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 43592750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 43592750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 43592750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 43592750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.430066 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.430066 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.429996 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.429996 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8218.844268 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87360 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64748.911122 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3495788 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152066 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.988623 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87146 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64741.188816 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3494549 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151845 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.013922 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50325.123938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006393 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141290 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.854795 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11198.784706 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.767900 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50454.801369 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141667 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3260.512095 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11025.733685 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.769879 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049207 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170880 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987990 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64706 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2949 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5093 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56562 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987335 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32257665 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32257665 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6357 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2756 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 781636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1281044 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2071793 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1544066 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1544066 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200764 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200764 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6357 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2756 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 781636 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481808 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2272557 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6357 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2756 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 781636 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481808 # number of overall hits -system.cpu.l2cache.overall_hits::total 2272557 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.168239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64699 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2964 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5133 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56510 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987228 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32250710 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32250710 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7142 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3328 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 782034 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3328 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 782034 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1480489 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2272993 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7142 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3328 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 782034 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1480489 # number of overall hits +system.cpu.l2cache.overall_hits::total 2272993 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12949 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41579 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1347 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1347 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113593 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113593 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12949 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142217 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155172 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12937 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141790 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154732 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12949 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142217 # number of overall misses -system.cpu.l2cache.overall_misses::total 155172 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 405750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 944829500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2144751500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3090076000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16383859 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16383859 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7839721470 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7839721470 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 405750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 944829500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9984472970 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10929797470 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 405750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 944829500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9984472970 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10929797470 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6358 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2761 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 794585 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1309668 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2113372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1544066 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1544066 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1668 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1668 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314357 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314357 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6358 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2761 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 794585 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1624025 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2427729 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6358 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2761 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 794585 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1624025 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2427729 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001811 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021856 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019674 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807554 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807554 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361350 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.361350 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001811 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087571 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063917 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001811 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087571 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063917 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81150 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72965.441347 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74928.434181 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74318.189471 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12163.221232 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12163.221232 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69015.885398 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69015.885398 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70436.660416 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70436.660416 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12937 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses +system.cpu.l2cache.overall_misses::total 154732 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1308871 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2114317 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1543366 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1543366 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1674 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313408 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313408 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3333 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 794971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1622279 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2427725 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3333 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 794971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1622279 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2427725 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016274 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087402 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063735 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -953,90 +919,78 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80295 # number of writebacks -system.cpu.l2cache.writebacks::total 80295 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks +system.cpu.l2cache.writebacks::total 80303 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12949 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41579 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1347 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1347 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113593 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113593 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142217 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155172 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12937 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154732 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12949 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142217 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 155172 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 342750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 782620000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1786397500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2569436500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14401829 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14401829 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6419846030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6419846030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 342750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 782620000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8206243530 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8989282530 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 342750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 782620000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8206243530 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8989282530 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088095000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088095000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021856 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019674 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807554 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807554 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361350 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361350 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063917 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063917 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60438.643911 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62409.079793 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61796.495827 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.780995 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.780995 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56516.211650 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56516.211650 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88554571000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88554571000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063735 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1044,59 +998,59 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2700583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1544066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314362 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53190 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 54167 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230298 # Transaction distribution -system.iobus.trans_dist::ReadResp 230298 # Transaction distribution +system.iobus.trans_dist::ReadReq 228399 # Transaction distribution +system.iobus.trans_dist::ReadResp 228399 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 11006 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1653 # Transaction distribution -system.iobus.trans_dist::MessageResp 1653 # Transaction distribution +system.iobus.trans_dist::MessageReq 1652 # Transaction distribution +system.iobus.trans_dist::MessageResp 1652 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1105,7 +1059,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 432904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1115,12 +1069,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 477136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95114 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 575554 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1129,7 +1083,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 216452 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1139,13 +1093,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 244848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3278696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3940536 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1163,7 +1117,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 216453000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1181,54 +1135,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 257203754 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 466130000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50194752 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47511 # number of replacements -system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use +system.iocache.tags.replacements 47502 # number of replacements +system.iocache.tags.tagsinuse 0.095966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47518 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5046161981000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005998 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428094 # Number of tag accesses -system.iocache.tags.data_accesses 428094 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses -system.iocache.ReadReq_misses::total 846 # number of ReadReq misses +system.iocache.tags.tag_accesses 428013 # Number of tag accesses +system.iocache.tags.data_accesses 428013 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 837 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses -system.iocache.demand_misses::total 846 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses -system.iocache.overall_misses::total 846 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 837 # number of demand (read+write) misses +system.iocache.demand_misses::total 837 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 837 # number of overall misses +system.iocache.overall_misses::total 837 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132288440 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 132288440 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8590965562 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8590965562 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 132288440 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 132288440 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 132288440 # number of overall miss cycles +system.iocache.overall_miss_latency::total 132288440 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 837 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 837 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1237,40 +1191,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158050.704898 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158050.704898 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158050.704898 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4442 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.674246 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 837 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88419930 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6161511576 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6161511576 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 88419930 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 88419930 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1279,71 +1233,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624018 # Transaction distribution -system.membus.trans_dist::ReadResp 624018 # Transaction distribution -system.membus.trans_dist::WriteReq 13918 # Transaction distribution -system.membus.trans_dist::WriteResp 13918 # Transaction distribution -system.membus.trans_dist::Writeback 126962 # Transaction distribution +system.membus.trans_dist::ReadReq 617109 # Transaction distribution +system.membus.trans_dist::ReadResp 617109 # Transaction distribution +system.membus.trans_dist::WriteReq 13916 # Transaction distribution +system.membus.trans_dist::WriteResp 13916 # Transaction distribution +system.membus.trans_dist::Writeback 126970 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution -system.membus.trans_dist::ReadExReq 113313 # Transaction distribution -system.membus.trans_dist::ReadExResp 113313 # Transaction distribution -system.membus.trans_dist::MessageReq 1653 # Transaction distribution -system.membus.trans_dist::MessageResp 1653 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution +system.membus.trans_dist::ReadExReq 112993 # Transaction distribution +system.membus.trans_dist::ReadExResp 112993 # Transaction distribution +system.membus.trans_dist::MessageReq 1652 # Transaction distribution +system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1602 # Total snoops (count) -system.membus.snoop_fanout::samples 331576 # Request fanout histogram +system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1583 # Total snoops (count) +system.membus.snoop_fanout::samples 331203 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331576 # Request fanout histogram -system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331203 # Request fanout histogram +system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |