diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
| commit | bbcbe028fe904ec3f48b39e02c4a8fbc6f438699 (patch) | |
| tree | 2e3c780f3c56f844d4fb36b438c3691af198a02b /tests/quick/fs/10.linux-boot | |
| parent | 78275c9d2f918d245902c3c00a9486b4af8e8099 (diff) | |
| download | gem5-bbcbe028fe904ec3f48b39e02c4a8fbc6f438699.tar.xz | |
stats: Update to reflect changes to PCI handling
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
41 files changed, 6571 insertions, 6747 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 147022c3d..26263fe30 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -28,8 +28,8 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -357,7 +357,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -380,7 +380,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -403,10 +403,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -433,7 +432,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[29] +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -541,7 +540,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -577,7 +576,7 @@ system=system [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -690,12 +689,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -705,9 +704,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1140,14 +1138,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1167,25 +1164,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 9712abdc1..267d74a00 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 15 2015 14:28:00 -gem5 started Nov 15 2015 14:28:25 -gem5 executing on ribera.cs.wisc.edu, pid 29050 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 11:07:13 +gem5 executing on e104799-lin, pid 25873 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /work/gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 6db4bbedf..7d1787c51 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.869358 # Nu sim_ticks 1869358498000 # Number of ticks simulated final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1547194 # Simulator instruction rate (inst/s) -host_op_rate 1547193 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44495947902 # Simulator tick rate (ticks/s) -host_mem_usage 371328 # Number of bytes of host memory used -host_seconds 42.01 # Real time elapsed on the host +host_inst_rate 1636822 # Simulator instruction rate (inst/s) +host_op_rate 1636821 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47073565091 # Simulator tick rate (ticks/s) +host_mem_usage 332968 # Number of bytes of host memory used +host_seconds 39.71 # Real time elapsed on the host sim_insts 65000470 # Number of instructions simulated sim_ops 65000470 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -661,33 +661,27 @@ system.iobus.trans_dist::ReadResp 7628 # Tr system.iobus.trans_dist::WriteReq 56140 # Transaction distribution system.iobus.trans_dist::WriteResp 56140 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1014 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2749 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 399564d33..fdc1c18f8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -28,8 +28,8 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -283,7 +283,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -306,7 +306,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -329,10 +329,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -359,7 +358,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[29] +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -430,7 +429,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -443,7 +442,7 @@ port=3456 [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -556,12 +555,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -571,9 +570,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1006,14 +1004,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1033,25 +1030,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 2fef53741..f5d0532f3 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 15 2015 14:28:00 -gem5 started Nov 15 2015 14:28:58 -gem5 executing on ribera.cs.wisc.edu, pid 29091 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 10:35:24 +gem5 executing on e104799-lin, pid 22025 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /work/gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332273500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 22bb41ee4..cb5e09d0f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332273500 # Number of ticks simulated final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1568783 # Simulator instruction rate (inst/s) -host_op_rate 1568783 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47799849374 # Simulator tick rate (ticks/s) -host_mem_usage 368252 # Number of bytes of host memory used -host_seconds 38.27 # Real time elapsed on the host +host_inst_rate 1702079 # Simulator instruction rate (inst/s) +host_op_rate 1702079 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51861293564 # Simulator tick rate (ticks/s) +host_mem_usage 329640 # Number of bytes of host memory used +host_seconds 35.27 # Real time elapsed on the host sim_insts 60038341 # Number of instructions simulated sim_ops 60038341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -489,33 +489,27 @@ system.iobus.trans_dist::ReadResp 7358 # Tr system.iobus.trans_dist::WriteReq 51390 # Transaction distribution system.iobus.trans_dist::WriteResp 51390 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 20ac6fa35..419a63341 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -28,8 +28,8 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -349,7 +349,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -372,7 +372,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -395,10 +395,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -425,7 +424,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[29] +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -597,7 +596,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -633,7 +632,7 @@ system=system [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -746,12 +745,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -761,9 +760,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1196,14 +1194,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1223,25 +1220,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 0661a98ef..19ef21baf 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,16 +1,14 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 15 2015 14:28:00 -gem5 started Nov 15 2015 14:28:24 -gem5 executing on ribera.cs.wisc.edu, pid 29049 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 10:53:21 +gem5 executing on e104799-lin, pid 24287 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /work/gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 881785000 -Exiting @ tick 1977709274000 because m5_exit instruction encountered +Exiting @ tick 1982594146000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index feaac6b8f..faf036214 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.977709 # Number of seconds simulated -sim_ticks 1977709274000 # Number of ticks simulated -final_tick 1977709274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.982594 # Number of seconds simulated +sim_ticks 1982594146000 # Number of ticks simulated +final_tick 1982594146000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 813213 # Simulator instruction rate (inst/s) -host_op_rate 813212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27059617080 # Simulator tick rate (ticks/s) -host_mem_usage 371328 # Number of bytes of host memory used -host_seconds 73.09 # Real time elapsed on the host -sim_insts 59435338 # Number of instructions simulated -sim_ops 59435338 # Number of ops (including micro ops) simulated +host_inst_rate 876674 # Simulator instruction rate (inst/s) +host_op_rate 876674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28498337600 # Simulator tick rate (ticks/s) +host_mem_usage 332972 # Number of bytes of host memory used +host_seconds 69.57 # Real time elapsed on the host +sim_insts 60989111 # Number of instructions simulated +sim_ops 60989111 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 694336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 23907392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 165888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1310592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 800320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24686528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 60096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 523456 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26079168 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 694336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 165888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 860224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7747712 # Number of bytes written to this memory -system.physmem.bytes_written::total 7747712 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 10849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 373553 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2592 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20478 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26071360 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 800320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 60096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 860416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7740160 # Number of bytes written to this memory +system.physmem.bytes_written::total 7740160 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 12505 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 939 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8179 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407487 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121058 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121058 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 351081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12088426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 83879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 662682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13186553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 351081 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 83879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434960 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3917518 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3917518 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3917518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 351081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12088426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 83879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 662682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17104071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 407487 # Number of read requests accepted -system.physmem.writeReqs 121058 # Number of write requests accepted -system.physmem.readBursts 407487 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121058 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26071296 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue -system.physmem.bytesWritten 7746112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26079168 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7747712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 407365 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120940 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120940 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 403673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12451630 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 264026 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13150125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 403673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30312 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 433985 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3904057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3904057 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3904057 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 403673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12451630 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 264026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17054181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407365 # Number of read requests accepted +system.physmem.writeReqs 120940 # Number of write requests accepted +system.physmem.readBursts 407365 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120940 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26063552 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7808 # Total number of bytes read from write queue +system.physmem.bytesWritten 7739008 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26071360 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7740160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 122 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 306935 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25840 # Per bank write bursts -system.physmem.perBankRdBursts::1 26009 # Per bank write bursts -system.physmem.perBankRdBursts::2 26271 # Per bank write bursts -system.physmem.perBankRdBursts::3 25739 # Per bank write bursts -system.physmem.perBankRdBursts::4 24904 # Per bank write bursts -system.physmem.perBankRdBursts::5 25588 # Per bank write bursts -system.physmem.perBankRdBursts::6 25282 # Per bank write bursts -system.physmem.perBankRdBursts::7 25179 # Per bank write bursts -system.physmem.perBankRdBursts::8 24919 # Per bank write bursts -system.physmem.perBankRdBursts::9 24911 # Per bank write bursts -system.physmem.perBankRdBursts::10 25224 # Per bank write bursts -system.physmem.perBankRdBursts::11 25266 # Per bank write bursts -system.physmem.perBankRdBursts::12 25817 # Per bank write bursts -system.physmem.perBankRdBursts::13 25627 # Per bank write bursts -system.physmem.perBankRdBursts::14 25517 # Per bank write bursts -system.physmem.perBankRdBursts::15 25271 # Per bank write bursts -system.physmem.perBankWrBursts::0 8076 # Per bank write bursts -system.physmem.perBankWrBursts::1 7966 # Per bank write bursts -system.physmem.perBankWrBursts::2 8289 # Per bank write bursts -system.physmem.perBankWrBursts::3 8035 # Per bank write bursts -system.physmem.perBankWrBursts::4 7145 # Per bank write bursts -system.physmem.perBankWrBursts::5 7755 # Per bank write bursts -system.physmem.perBankWrBursts::6 7349 # Per bank write bursts -system.physmem.perBankWrBursts::7 7181 # Per bank write bursts -system.physmem.perBankWrBursts::8 6971 # Per bank write bursts -system.physmem.perBankWrBursts::9 7004 # Per bank write bursts -system.physmem.perBankWrBursts::10 7220 # Per bank write bursts -system.physmem.perBankWrBursts::11 7086 # Per bank write bursts -system.physmem.perBankWrBursts::12 7863 # Per bank write bursts -system.physmem.perBankWrBursts::13 7891 # Per bank write bursts -system.physmem.perBankWrBursts::14 7798 # Per bank write bursts -system.physmem.perBankWrBursts::15 7404 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 310700 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25226 # Per bank write bursts +system.physmem.perBankRdBursts::1 25379 # Per bank write bursts +system.physmem.perBankRdBursts::2 25426 # Per bank write bursts +system.physmem.perBankRdBursts::3 24856 # Per bank write bursts +system.physmem.perBankRdBursts::4 25157 # Per bank write bursts +system.physmem.perBankRdBursts::5 25423 # Per bank write bursts +system.physmem.perBankRdBursts::6 25497 # Per bank write bursts +system.physmem.perBankRdBursts::7 25344 # Per bank write bursts +system.physmem.perBankRdBursts::8 25239 # Per bank write bursts +system.physmem.perBankRdBursts::9 25589 # Per bank write bursts +system.physmem.perBankRdBursts::10 25746 # Per bank write bursts +system.physmem.perBankRdBursts::11 25918 # Per bank write bursts +system.physmem.perBankRdBursts::12 25947 # Per bank write bursts +system.physmem.perBankRdBursts::13 25572 # Per bank write bursts +system.physmem.perBankRdBursts::14 25277 # Per bank write bursts +system.physmem.perBankRdBursts::15 25647 # Per bank write bursts +system.physmem.perBankWrBursts::0 7851 # Per bank write bursts +system.physmem.perBankWrBursts::1 7778 # Per bank write bursts +system.physmem.perBankWrBursts::2 7471 # Per bank write bursts +system.physmem.perBankWrBursts::3 6887 # Per bank write bursts +system.physmem.perBankWrBursts::4 7104 # Per bank write bursts +system.physmem.perBankWrBursts::5 7345 # Per bank write bursts +system.physmem.perBankWrBursts::6 7441 # Per bank write bursts +system.physmem.perBankWrBursts::7 7150 # Per bank write bursts +system.physmem.perBankWrBursts::8 7161 # Per bank write bursts +system.physmem.perBankWrBursts::9 7315 # Per bank write bursts +system.physmem.perBankWrBursts::10 7729 # Per bank write bursts +system.physmem.perBankWrBursts::11 8151 # Per bank write bursts +system.physmem.perBankWrBursts::12 8256 # Per bank write bursts +system.physmem.perBankWrBursts::13 7924 # Per bank write bursts +system.physmem.perBankWrBursts::14 7541 # Per bank write bursts +system.physmem.perBankWrBursts::15 7818 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 1977655892500 # Total gap between requests +system.physmem.totGap 1982586778500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 407487 # Read request sizes (log2) +system.physmem.readPktSize::6 407365 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121058 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 71 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120940 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,187 +158,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 65 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 68003 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 497.292884 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 300.084252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.105473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16504 24.27% 24.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12590 18.51% 42.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5294 7.78% 50.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3182 4.68% 55.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2479 3.65% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4294 6.31% 65.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1483 2.18% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2078 3.06% 70.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20099 29.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 68003 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 75.144069 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2865.262786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5418 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 76 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67594 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 500.082256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 302.770491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 404.772373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16306 24.12% 24.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12315 18.22% 42.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5219 7.72% 50.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3345 4.95% 55.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2482 3.67% 58.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4236 6.27% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1519 2.25% 67.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2145 3.17% 70.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20027 29.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67594 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5426 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.053815 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2863.944316 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5423 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5421 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5421 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.326692 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.006479 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.134399 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4779 88.16% 88.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 22 0.41% 88.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 23 0.42% 88.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 175 3.23% 92.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 9 0.17% 92.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.46% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 50 0.92% 93.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.04% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.24% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.35% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 6 0.11% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 8 0.15% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 22 0.41% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 20 0.37% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.07% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 34 0.63% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 96.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.04% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 161 2.97% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.06% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.11% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 5 0.09% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.06% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 16 0.30% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5421 # Writes before turning the bus around for reads -system.physmem.totQLat 2796894000 # Total ticks spent queuing -system.physmem.totMemAccLat 10434969000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2036820000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6865.83 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5426 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5426 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.285662 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.994987 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.002081 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4792 88.32% 88.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 23 0.42% 88.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 16 0.29% 89.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 184 3.39% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1 0.02% 92.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 19 0.35% 92.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 45 0.83% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.06% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.13% 93.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 30 0.55% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 7 0.13% 94.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.07% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 5 0.09% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.07% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 20 0.37% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.48% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 28 0.52% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.07% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 168 3.10% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 1 0.02% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.04% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.09% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 5 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 10 0.18% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::204-207 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5426 # Writes before turning the bus around for reads +system.physmem.totQLat 2787487250 # Total ticks spent queuing +system.physmem.totMemAccLat 10423293500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2036215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6844.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25615.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 25594.78 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.15 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.90 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.15 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 363824 # Number of row buffer hits during reads -system.physmem.writeRowHits 96570 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.31 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.77 # Row buffer hit rate for writes -system.physmem.avgGap 3741698.23 # Average gap between requests -system.physmem.pageHitRate 87.13 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 262483200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 143220000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1597533600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 400438080 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 73962048600 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1121745657750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1327285621230 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.123235 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1865834845500 # Time in different power states -system.physmem_0.memoryStateTime::REF 66040000000 # Time in different power states +system.physmem.avgWrQLen 23.89 # Average write queue length when enqueuing +system.physmem.readRowHits 363847 # Number of row buffer hits during reads +system.physmem.writeRowHits 96724 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.34 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.98 # Row buffer hit rate for writes +system.physmem.avgGap 3752731.43 # Average gap between requests +system.physmem.pageHitRate 87.20 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 243930960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 133097250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1578002400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 382494960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72912858435 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1125595195500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1330338686625 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.010578 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1872246434250 # Time in different power states +system.physmem_0.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 45832914500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 44140298250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 251619480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 137292375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579905600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 383855760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 129174240000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73584887580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1122076500750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1327188301545 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.074027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1866389529250 # Time in different power states -system.physmem_1.memoryStateTime::REF 66040000000 # Time in different power states +system.physmem_1.actEnergy 267079680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 145728000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598493000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 401079600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 129493107120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 73974222945 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1124664165750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1330543876095 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.114078 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1870697169250 # Time in different power states +system.physmem_1.memoryStateTime::REF 66203020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45278230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45689549500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 5727753 # DTB read hits +system.cpu0.dtb.read_hits 7416215 # DTB read hits system.cpu0.dtb.read_misses 7442 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 490672 # DTB read accesses -system.cpu0.dtb.write_hits 3981122 # DTB write hits +system.cpu0.dtb.write_hits 5004240 # DTB write hits system.cpu0.dtb.write_misses 812 # DTB write misses system.cpu0.dtb.write_acv 134 # DTB write access violations system.cpu0.dtb.write_accesses 187451 # DTB write accesses -system.cpu0.dtb.data_hits 9708875 # DTB hits +system.cpu0.dtb.data_hits 12420455 # DTB hits system.cpu0.dtb.data_misses 8254 # DTB misses system.cpu0.dtb.data_acv 344 # DTB access violations system.cpu0.dtb.data_accesses 678123 # DTB accesses -system.cpu0.itb.fetch_hits 3124468 # ITB hits +system.cpu0.itb.fetch_hits 3482237 # ITB hits system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3128339 # ITB accesses +system.cpu0.itb.fetch_accesses 3486108 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -351,36 +354,36 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3955086246 # number of cpu cycles simulated +system.cpu0.numCycles 3964851893 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4843 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 129735 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 41337 38.33% 38.33% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.12% 38.45% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1972 1.83% 40.28% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 64391 59.71% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 107848 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 40894 48.75% 48.75% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1972 2.35% 51.25% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 17 0.02% 51.27% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 40877 48.73% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 83891 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1907093255000 96.44% 96.44% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94033500 0.00% 96.44% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 783814000 0.04% 96.48% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 14262000 0.00% 96.48% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 69557728500 3.52% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1977543093000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.989283 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6804 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 162792 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 55926 40.12% 40.12% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.21% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1977 1.42% 41.63% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 435 0.31% 41.94% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 80934 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 139403 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 55417 49.07% 49.07% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.12% 49.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1977 1.75% 50.93% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 435 0.39% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 54982 48.68% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 112942 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1904792162000 96.08% 96.08% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 93245000 0.00% 96.09% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 790775500 0.04% 96.13% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 326471500 0.02% 96.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 76423262500 3.86% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1982425916500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990899 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.634825 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.777863 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.679344 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.810183 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed @@ -412,179 +415,179 @@ system.cpu0.kern.syscall::144 2 0.90% 99.10% # nu system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 93 0.08% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # number of callpals executed -system.cpu0.kern.callpal::swpctx 1998 1.74% 1.82% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.04% 1.87% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.87% # number of callpals executed -system.cpu0.kern.callpal::swpipl 101884 88.63% 90.50% # number of callpals executed -system.cpu0.kern.callpal::rdps 6548 5.70% 96.19% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.20% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.20% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.21% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.21% # number of callpals executed -system.cpu0.kern.callpal::rti 3843 3.34% 99.55% # number of callpals executed -system.cpu0.kern.callpal::callsys 381 0.33% 99.88% # number of callpals executed -system.cpu0.kern.callpal::imb 136 0.12% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 114960 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5413 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches +system.cpu0.kern.callpal::wripir 524 0.36% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3024 2.05% 2.41% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed +system.cpu0.kern.callpal::swpipl 132535 89.80% 92.24% # number of callpals executed +system.cpu0.kern.callpal::rdps 6593 4.47% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.72% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.72% # number of callpals executed +system.cpu0.kern.callpal::rti 4324 2.93% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 147594 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6862 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1281 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1282 -system.cpu0.kern.mode_good::user 1282 +system.cpu0.kern.mode_good::kernel 1281 +system.cpu0.kern.mode_good::user 1281 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.236837 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186680 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.382972 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1972827474000 99.80% 99.80% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3894173000 0.20% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.314626 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1977686351500 99.80% 99.80% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3896829000 0.20% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 1999 # number of times the context was actually changed -system.cpu0.committedInsts 36251265 # Number of instructions committed -system.cpu0.committedOps 36251265 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33727452 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 135758 # Number of float alu accesses -system.cpu0.num_func_calls 876834 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4248905 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33727452 # number of integer instructions -system.cpu0.num_fp_insts 135758 # number of float instructions -system.cpu0.num_int_register_reads 46333717 # number of times the integer registers were read -system.cpu0.num_int_register_writes 25193797 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 65701 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 66416 # number of times the floating registers were written -system.cpu0.num_mem_refs 9739707 # number of memory refs -system.cpu0.num_load_insts 5749561 # Number of load instructions -system.cpu0.num_store_insts 3990146 # Number of store instructions -system.cpu0.num_idle_cycles 3736968981.972937 # Number of idle cycles -system.cpu0.num_busy_cycles 218117264.027063 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055149 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944851 # Percentage of idle cycles -system.cpu0.Branches 5398761 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1979626 5.46% 5.46% # Class of executed instruction -system.cpu0.op_class::IntAlu 23753610 65.51% 70.97% # Class of executed instruction -system.cpu0.op_class::IntMult 36908 0.10% 71.07% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.07% # Class of executed instruction -system.cpu0.op_class::FloatAdd 22960 0.06% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1656 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.14% # Class of executed instruction -system.cpu0.op_class::MemRead 5882505 16.22% 87.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 3995282 11.02% 98.38% # Class of executed instruction -system.cpu0.op_class::IprAccess 587316 1.62% 100.00% # Class of executed instruction +system.cpu0.kern.swap_context 3025 # number of times the context was actually changed +system.cpu0.committedInsts 47311851 # Number of instructions committed +system.cpu0.committedOps 47311851 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 43882265 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 206939 # Number of float alu accesses +system.cpu0.num_func_calls 1185568 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5564719 # number of instructions that are conditional controls +system.cpu0.num_int_insts 43882265 # number of integer instructions +system.cpu0.num_fp_insts 206939 # number of float instructions +system.cpu0.num_int_register_reads 60327433 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32715156 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 100516 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 102286 # number of times the floating registers were written +system.cpu0.num_mem_refs 12460349 # number of memory refs +system.cpu0.num_load_insts 7443153 # Number of load instructions +system.cpu0.num_store_insts 5017196 # Number of store instructions +system.cpu0.num_idle_cycles 3699958327.970898 # Number of idle cycles +system.cpu0.num_busy_cycles 264893565.029101 # Number of busy cycles +system.cpu0.not_idle_fraction 0.066810 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.933190 # Percentage of idle cycles +system.cpu0.Branches 7132898 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2702955 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31171442 65.87% 71.59% # Class of executed instruction +system.cpu0.op_class::IntMult 51645 0.11% 71.69% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25566 0.05% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.75% # Class of executed instruction +system.cpu0.op_class::MemRead 7616230 16.10% 87.85% # Class of executed instruction +system.cpu0.op_class::MemWrite 5023298 10.62% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 727657 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36259863 # Class of executed instruction -system.cpu0.dcache.tags.replacements 822072 # number of replacements -system.cpu0.dcache.tags.tagsinuse 480.504845 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 8885001 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 822496 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.802485 # Average number of references to valid blocks. +system.cpu0.op_class::total 47320449 # Class of executed instruction +system.cpu0.dcache.tags.replacements 1172797 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.333348 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11236424 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1173216 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.577455 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 144706500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.504845 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938486 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.938486 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 39682070 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 39682070 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5000163 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5000163 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3644006 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3644006 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117543 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 117543 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123259 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 123259 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8644169 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8644169 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8644169 # number of overall hits -system.cpu0.dcache.overall_hits::total 8644169 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 612538 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 612538 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 209263 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 209263 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6851 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6851 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 636 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 636 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 821801 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 821801 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 821801 # number of overall misses -system.cpu0.dcache.overall_misses::total 821801 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38657814000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 38657814000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 14917066000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 14917066000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 93675500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 93675500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8969500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 8969500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 53574880000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 53574880000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 53574880000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 53574880000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5612701 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5612701 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3853269 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 3853269 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124394 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 124394 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123895 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 123895 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9465970 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9465970 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9465970 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9465970 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.109134 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.109134 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054308 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.054308 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055075 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055075 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.005133 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.005133 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086816 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086816 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086816 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086816 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 63110.882917 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 63110.882917 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 71283.819882 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 71283.819882 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13673.259378 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13673.259378 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14102.987421 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14102.987421 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 65192.035541 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 65192.035541 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 65192.035541 # average overall miss latency +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.333348 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986979 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986979 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 371 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.818359 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50906675 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50906675 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6342506 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6342506 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4600881 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4600881 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138108 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 138108 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145430 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 145430 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10943387 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10943387 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10943387 # number of overall hits +system.cpu0.dcache.overall_hits::total 10943387 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 934212 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 934212 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 249094 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 249094 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13595 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13595 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5739 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5739 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1183306 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1183306 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1183306 # number of overall misses +system.cpu0.dcache.overall_misses::total 1183306 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 42884699000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 42884699000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 16803448000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 16803448000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 151690000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 151690000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 97426500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 97426500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 59688147000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 59688147000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 59688147000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 59688147000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7276718 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7276718 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4849975 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4849975 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 151703 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 151703 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 151169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 151169 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12126693 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12126693 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12126693 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12126693 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.128384 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.128384 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051360 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051360 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089616 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089616 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037964 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.037964 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097579 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097579 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097579 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097579 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45904.675812 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 45904.675812 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67458.260737 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67458.260737 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11157.778595 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11157.778595 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16976.215369 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16976.215369 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 50441.852741 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 50441.852741 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 50441.852741 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 50441.852741 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -593,126 +596,126 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 366665 # number of writebacks -system.cpu0.dcache.writebacks::total 366665 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 612538 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 612538 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 209263 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 209263 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6851 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6851 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 636 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 821801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 821801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 821801 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 821801 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 4814 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 8193 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 13007 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38045276000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38045276000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 14707803000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 14707803000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 86824500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 86824500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 8333500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 8333500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 52753079000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 52753079000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 52753079000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 52753079000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1072338000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1072338000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1840159000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1840159000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2912497000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2912497000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.109134 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.109134 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054308 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054308 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055075 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055075 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.005133 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.005133 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086816 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086816 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086816 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 62110.882917 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 62110.882917 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 70283.819882 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 70283.819882 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12673.259378 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12673.259378 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13102.987421 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13102.987421 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 64192.035541 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 64192.035541 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222754.050686 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222754.050686 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 224601.367021 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 224601.367021 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 223917.659722 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 223917.659722 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 672822 # number of writebacks +system.cpu0.dcache.writebacks::total 672822 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 934212 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 934212 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249094 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249094 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13595 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13595 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5739 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1183306 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1183306 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1183306 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1183306 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7080 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7080 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10780 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10780 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17860 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41950487000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41950487000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 16554354000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 16554354000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 138095000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 138095000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 91687500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 91687500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 58504841000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 58504841000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 58504841000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 58504841000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1566158000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1566158000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2451078500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2451078500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4017236500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4017236500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.128384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.128384 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051360 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051360 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089616 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089616 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037964 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037964 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097579 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097579 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097579 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097579 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 44904.675812 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 44904.675812 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 66458.260737 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 66458.260737 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10157.778595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10157.778595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 15976.215369 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15976.215369 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49441.852741 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 49441.852741 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49441.852741 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 49441.852741 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 221208.757062 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 221208.757062 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 227372.773655 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 227372.773655 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 224929.255319 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 224929.255319 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 490042 # number of replacements -system.cpu0.icache.tags.tagsinuse 506.476572 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 35769214 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490554 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 72.915956 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 686460 # number of replacements +system.cpu0.icache.tags.tagsinuse 506.490701 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 46633355 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 686972 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.882468 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 58998281500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.476572 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989212 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.989212 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 506.490701 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.989240 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.989240 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 296 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 417 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 36750512 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 36750512 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 35769214 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 35769214 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 35769214 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 35769214 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 35769214 # number of overall hits -system.cpu0.icache.overall_hits::total 35769214 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490649 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490649 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490649 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490649 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490649 # number of overall misses -system.cpu0.icache.overall_misses::total 490649 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7808174000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7808174000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7808174000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7808174000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7808174000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7808174000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 36259863 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 36259863 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 36259863 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 36259863 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 36259863 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 36259863 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013531 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013531 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013531 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013531 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013531 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013531 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15913.971087 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15913.971087 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15913.971087 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15913.971087 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15913.971087 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48007543 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48007543 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 46633355 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 46633355 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 46633355 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 46633355 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 46633355 # number of overall hits +system.cpu0.icache.overall_hits::total 46633355 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 687094 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 687094 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 687094 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 687094 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 687094 # number of overall misses +system.cpu0.icache.overall_misses::total 687094 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10621840000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10621840000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10621840000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10621840000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10621840000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10621840000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47320449 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47320449 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47320449 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47320449 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47320449 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47320449 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014520 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014520 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014520 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014520 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014520 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014520 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15459.078379 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15459.078379 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15459.078379 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15459.078379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15459.078379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15459.078379 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -721,53 +724,53 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 490042 # number of writebacks -system.cpu0.icache.writebacks::total 490042 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490649 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490649 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490649 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490649 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490649 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490649 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 7317525000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 7317525000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 7317525000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 7317525000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 7317525000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 7317525000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013531 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013531 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013531 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013531 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14913.971087 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14913.971087 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 14913.971087 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 686460 # number of writebacks +system.cpu0.icache.writebacks::total 686460 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 687094 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 687094 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 687094 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 687094 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 687094 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 687094 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9934746000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9934746000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9934746000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9934746000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9934746000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9934746000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014520 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014520 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014520 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014520 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 14459.078379 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 14459.078379 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 14459.078379 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 14459.078379 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3965416 # DTB read hits +system.cpu1.dtb.read_hits 2510685 # DTB read hits system.cpu1.dtb.read_misses 2993 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 239364 # DTB read accesses -system.cpu1.dtb.write_hits 2725894 # DTB write hits +system.cpu1.dtb.write_hits 1829711 # DTB write hits system.cpu1.dtb.write_misses 342 # DTB write misses system.cpu1.dtb.write_acv 29 # DTB write access violations system.cpu1.dtb.write_accesses 105248 # DTB write accesses -system.cpu1.dtb.data_hits 6691310 # DTB hits +system.cpu1.dtb.data_hits 4340396 # DTB hits system.cpu1.dtb.data_misses 3335 # DTB misses system.cpu1.dtb.data_acv 29 # DTB access violations system.cpu1.dtb.data_accesses 344612 # DTB accesses -system.cpu1.itb.fetch_hits 2218092 # ITB hits +system.cpu1.itb.fetch_hits 1990327 # ITB hits system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 2219308 # ITB accesses +system.cpu1.itb.fetch_accesses 1991543 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -780,32 +783,32 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3955418548 # number of cpu cycles simulated +system.cpu1.numCycles 3965188292 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3977 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 108865 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 40405 40.60% 40.60% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1966 1.98% 42.57% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 93 0.09% 42.67% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 57058 57.33% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 99522 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 39471 48.79% 48.79% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1966 2.43% 51.21% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 93 0.11% 51.33% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 39378 48.67% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 80908 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1902956585000 96.22% 96.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 734079500 0.04% 96.26% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 70449000 0.00% 96.26% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 73947425500 3.74% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1977708539000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.976884 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2870 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 81053 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 27549 38.53% 38.53% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1971 2.76% 41.28% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 524 0.73% 42.01% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 41464 57.99% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 71508 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 26681 48.22% 48.22% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1971 3.56% 51.78% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 524 0.95% 52.73% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 26157 47.27% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 55333 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1912242644500 96.45% 96.45% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 731132000 0.04% 96.49% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 374834500 0.02% 96.51% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 69244798000 3.49% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1982593409000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968493 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.690140 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.812966 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.630836 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.773802 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed @@ -821,179 +824,179 @@ system.cpu1.kern.syscall::74 10 9.62% 97.12% # nu system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 17 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2247 2.20% 2.22% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.22% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.23% # number of callpals executed -system.cpu1.kern.callpal::swpipl 94014 91.97% 94.20% # number of callpals executed -system.cpu1.kern.callpal::rdps 2296 2.25% 96.44% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.44% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.00% 96.45% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.45% # number of callpals executed -system.cpu1.kern.callpal::rti 3448 3.37% 99.82% # number of callpals executed -system.cpu1.kern.callpal::callsys 136 0.13% 99.96% # number of callpals executed -system.cpu1.kern.callpal::imb 44 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 435 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2066 2.79% 3.38% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed +system.cpu1.kern.callpal::swpipl 65186 88.12% 91.52% # number of callpals executed +system.cpu1.kern.callpal::rdps 2261 3.06% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.57% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.58% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.58% # number of callpals executed +system.cpu1.kern.callpal::rti 3826 5.17% 99.76% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.18% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 102224 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2738 # number of protection mode switches -system.cpu1.kern.mode_switch::user 463 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2043 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 518 -system.cpu1.kern.mode_good::user 463 -system.cpu1.kern.mode_good::idle 55 -system.cpu1.kern.mode_switch_good::kernel 0.189189 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 73976 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2114 # number of protection mode switches +system.cpu1.kern.mode_switch::user 464 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2922 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 912 +system.cpu1.kern.mode_good::user 464 +system.cpu1.kern.mode_good::idle 448 +system.cpu1.kern.mode_switch_good::kernel 0.431410 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.026921 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.197559 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 70603027000 3.57% 3.57% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1708148000 0.09% 3.66% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1905397362000 96.34% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2248 # number of times the context was actually changed -system.cpu1.committedInsts 23184073 # Number of instructions committed -system.cpu1.committedOps 23184073 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 21342235 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 193178 # Number of float alu accesses -system.cpu1.num_func_calls 708348 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2510657 # number of instructions that are conditional controls -system.cpu1.num_int_insts 21342235 # number of integer instructions -system.cpu1.num_fp_insts 193178 # number of float instructions -system.cpu1.num_int_register_reads 29195011 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15673593 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 100176 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 102374 # number of times the floating registers were written -system.cpu1.num_mem_refs 6716060 # number of memory refs -system.cpu1.num_load_insts 3980976 # Number of load instructions -system.cpu1.num_store_insts 2735084 # Number of store instructions -system.cpu1.num_idle_cycles 3859200221.998049 # Number of idle cycles -system.cpu1.num_busy_cycles 96218326.001951 # Number of busy cycles -system.cpu1.not_idle_fraction 0.024326 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.975674 # Percentage of idle cycles -system.cpu1.Branches 3468812 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1369332 5.91% 5.91% # Class of executed instruction -system.cpu1.op_class::IntAlu 14462485 62.37% 68.28% # Class of executed instruction -system.cpu1.op_class::IntMult 32790 0.14% 68.42% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.42% # Class of executed instruction -system.cpu1.op_class::FloatAdd 15288 0.07% 68.48% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.48% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.48% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.48% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1986 0.01% 68.49% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.49% # Class of executed instruction -system.cpu1.op_class::MemRead 4085109 17.62% 86.11% # Class of executed instruction -system.cpu1.op_class::MemWrite 2736216 11.80% 97.91% # Class of executed instruction -system.cpu1.op_class::IprAccess 484231 2.09% 100.00% # Class of executed instruction +system.cpu1.kern.mode_switch_good::idle 0.153320 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.331636 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 19465916000 0.98% 0.98% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1729420000 0.09% 1.07% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1961398071000 98.93% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2067 # number of times the context was actually changed +system.cpu1.committedInsts 13677260 # Number of instructions committed +system.cpu1.committedOps 13677260 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12615003 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 178612 # Number of float alu accesses +system.cpu1.num_func_calls 430048 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1358006 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12615003 # number of integer instructions +system.cpu1.num_fp_insts 178612 # number of float instructions +system.cpu1.num_int_register_reads 17367613 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9253143 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 93246 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 95234 # number of times the floating registers were written +system.cpu1.num_mem_refs 4364552 # number of memory refs +system.cpu1.num_load_insts 2525340 # Number of load instructions +system.cpu1.num_store_insts 1839212 # Number of store instructions +system.cpu1.num_idle_cycles 3912229588.998027 # Number of idle cycles +system.cpu1.num_busy_cycles 52958703.001973 # Number of busy cycles +system.cpu1.not_idle_fraction 0.013356 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.986644 # Percentage of idle cycles +system.cpu1.Branches 1948315 # Number of branches fetched +system.cpu1.op_class::No_OpClass 733682 5.36% 5.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 8093046 59.16% 64.52% # Class of executed instruction +system.cpu1.op_class::IntMult 23046 0.17% 64.69% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.69% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14372 0.11% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.01% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::MemRead 2600021 19.01% 83.81% # Class of executed instruction +system.cpu1.op_class::MemWrite 1840236 13.45% 97.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 374235 2.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 23187437 # Class of executed instruction -system.cpu1.dcache.tags.replacements 637928 # number of replacements -system.cpu1.dcache.tags.tagsinuse 487.645459 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6059697 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 638440 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 9.491412 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 77414441500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 487.645459 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.952433 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.952433 # Average percentage of cache occupancy +system.cpu1.op_class::total 13680624 # Class of executed instruction +system.cpu1.dcache.tags.replacements 173715 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.481115 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4164110 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 174227 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.900486 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90323581500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.481115 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940393 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940393 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 27453473 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 27453473 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3383453 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3383453 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2527183 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2527183 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 67642 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 67642 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79428 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79428 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5910636 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5910636 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5910636 # number of overall hits -system.cpu1.dcache.overall_hits::total 5910636 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 511536 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 511536 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 119772 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 119772 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 12967 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12967 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 653 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 653 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 631308 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 631308 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 631308 # number of overall misses -system.cpu1.dcache.overall_misses::total 631308 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6625803500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6625803500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3933748500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3933748500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 167428500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 167428500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 10386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 10386500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 10559552000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 10559552000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 10559552000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 10559552000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3894989 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3894989 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2646955 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2646955 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 80609 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 80609 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 80081 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 80081 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6541944 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6541944 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6541944 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6541944 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.131332 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.131332 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045249 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.045249 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160863 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160863 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.008154 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.008154 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.096502 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.096502 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.096502 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.096502 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12952.760901 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12952.760901 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32843.640417 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 32843.640417 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12911.891725 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12911.891725 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15905.819296 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 15905.819296 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16726.466321 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16726.466321 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16726.466321 # average overall miss latency +system.cpu1.dcache.tags.tag_accesses 17605365 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17605365 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2339052 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2339052 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1706902 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1706902 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 50404 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 50404 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 53074 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 53074 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4045954 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4045954 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4045954 # number of overall hits +system.cpu1.dcache.overall_hits::total 4045954 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 123499 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 123499 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 65580 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 65580 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9274 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9274 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 6110 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 6110 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 189079 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 189079 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 189079 # number of overall misses +system.cpu1.dcache.overall_misses::total 189079 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1557395000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1557395000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1879104500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1879104500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 85318500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 85318500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 99555000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 99555000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3436499500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3436499500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3436499500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3436499500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2462551 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2462551 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1772482 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1772482 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 59678 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 59678 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 59184 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 59184 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4235033 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4235033 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4235033 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4235033 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050151 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050151 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036999 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036999 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155401 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155401 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103237 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103237 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044646 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044646 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044646 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044646 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12610.587940 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12610.587940 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28653.621531 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 28653.621531 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9199.751995 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9199.751995 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16293.780687 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 16293.780687 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18174.940104 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18174.940104 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18174.940104 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18174.940104 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1002,128 +1005,128 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 496006 # number of writebacks -system.cpu1.dcache.writebacks::total 496006 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 511536 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 511536 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 119772 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 119772 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12967 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12967 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 653 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 653 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 631308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 631308 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 631308 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 631308 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2385 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4228 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 6613 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 6114267500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 6114267500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3813976500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3813976500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 154461500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 154461500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 9733500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 9733500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9928244000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9928244000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9928244000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9928244000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520029500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520029500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 992921500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 992921500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1512951000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1512951000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.131332 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.131332 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045249 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045249 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160863 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160863 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.008154 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.008154 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.096502 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.096502 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.096502 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.760901 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11952.760901 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31843.640417 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31843.640417 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11911.891725 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11911.891725 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14905.819296 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 14905.819296 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15726.466321 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15726.466321 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 218041.719078 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 218041.719078 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 234844.252602 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 234844.252602 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 228784.364131 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 228784.364131 # average overall mshr uncacheable latency +system.cpu1.dcache.writebacks::writebacks 119750 # number of writebacks +system.cpu1.dcache.writebacks::total 119750 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 123499 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 123499 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65580 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 65580 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9274 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9274 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6110 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 6110 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 189079 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 189079 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 189079 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 189079 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 118 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3348 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3466 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1433896000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1433896000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1813524500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1813524500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 76044500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 76044500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 93445000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 93445000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3247420500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3247420500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3247420500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3247420500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 25051000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 25051000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 789483500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 789483500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 814534500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 814534500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.050151 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.050151 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036999 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036999 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155401 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155401 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103237 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103237 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044646 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044646 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044646 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044646 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11610.587940 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11610.587940 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27653.621531 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27653.621531 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.751995 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8199.751995 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15293.780687 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 15293.780687 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17174.940104 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17174.940104 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17174.940104 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17174.940104 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 212296.610169 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 212296.610169 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 235807.497013 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 235807.497013 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 235007.068667 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 235007.068667 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 510167 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.053321 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 22676720 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 510679 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 44.405037 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 117353975500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.053321 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.968854 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.968854 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 331421 # number of replacements +system.cpu1.icache.tags.tagsinuse 442.918144 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13348652 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 331933 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.214899 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1976561020500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 442.918144 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.865074 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.865074 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 409 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 405 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 23698156 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 23698156 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 22676720 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22676720 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22676720 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22676720 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22676720 # number of overall hits -system.cpu1.icache.overall_hits::total 22676720 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 510718 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 510718 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 510718 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 510718 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 510718 # number of overall misses -system.cpu1.icache.overall_misses::total 510718 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7116614500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7116614500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7116614500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7116614500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7116614500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7116614500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 23187438 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 23187438 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 23187438 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 23187438 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 23187438 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 23187438 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022026 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022026 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022026 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022026 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022026 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022026 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13934.528448 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13934.528448 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13934.528448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13934.528448 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13934.528448 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 14012598 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14012598 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13348652 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13348652 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13348652 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13348652 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13348652 # number of overall hits +system.cpu1.icache.overall_hits::total 13348652 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 331973 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 331973 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 331973 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 331973 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 331973 # number of overall misses +system.cpu1.icache.overall_misses::total 331973 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4541836000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4541836000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4541836000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4541836000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4541836000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4541836000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13680625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13680625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13680625 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13680625 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13680625 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13680625 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024266 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024266 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024266 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024266 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024266 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024266 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13681.341555 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13681.341555 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13681.341555 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13681.341555 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13681.341555 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13681.341555 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1132,32 +1135,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 510167 # number of writebacks -system.cpu1.icache.writebacks::total 510167 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 510718 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 510718 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 510718 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 510718 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 510718 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 510718 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6605896500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6605896500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6605896500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6605896500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6605896500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6605896500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022026 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.022026 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022026 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.022026 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12934.528448 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12934.528448 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12934.528448 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 331421 # number of writebacks +system.cpu1.icache.writebacks::total 331421 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 331973 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 331973 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 331973 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 331973 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 331973 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 331973 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4209863000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4209863000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4209863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4209863000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4209863000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4209863000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024266 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024266 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024266 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024266 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.341555 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.341555 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.341555 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.341555 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1171,110 +1174,98 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 53973 # Transaction distribution -system.iobus.trans_dist::WriteResp 53973 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55680 # Transaction distribution +system.iobus.trans_dist::WriteResp 55680 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2476 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39240 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122698 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 42528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 126106 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56192 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9884 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 68786 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2730426 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11275500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 82434 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2744058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 15110500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 391000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 174500 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 175000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 15842500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2460000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6042000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 6039500 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 211500 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 83000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215050235 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 130500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215040242 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26819000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28524000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 41954000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 41950000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41699 # number of replacements -system.iocache.tags.tagsinuse 0.491123 # Cycle average of tags in use +system.iocache.tags.replacements 41695 # number of replacements +system.iocache.tags.tagsinuse 0.566864 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1769281205000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.491123 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.030695 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.030695 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1775104150000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.566864 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035429 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035429 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375561 # Number of tag accesses -system.iocache.tags.data_accesses 375561 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 177 # number of ReadReq misses -system.iocache.ReadReq_misses::total 177 # number of ReadReq misses +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses +system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses -system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses -system.iocache.demand_misses::total 177 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 177 # number of overall misses -system.iocache.overall_misses::total 177 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22195883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22195883 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::tsunami.ide 5429420359 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5429420359 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22195883 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22195883 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22195883 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22195883 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses +system.iocache.demand_misses::total 175 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 175 # number of overall misses +system.iocache.overall_misses::total 175 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21956883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21956883 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::tsunami.ide 5428160352 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5428160352 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21956883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21956883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21956883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21956883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses @@ -1283,40 +1274,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125400.468927 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 125400.468927 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130665.680569 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130665.680569 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125400.468927 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 125400.468927 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125400.468927 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 74 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125467.902857 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125467.902857 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 130635.356950 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130635.356950 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125467.902857 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125467.902857 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125467.902857 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 8 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.250000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41522 # number of writebacks -system.iocache.writebacks::total 41522 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13345883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 13345883 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3351820359 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 3351820359 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 13345883 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 13345883 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 13345883 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 13345883 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13206883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 13206883 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 3350560352 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 3350560352 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 13206883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 13206883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 13206883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 13206883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1325,199 +1316,199 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 75400.468927 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80665.680569 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80665.680569 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75400.468927 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75400.468927 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75467.902857 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 80635.356950 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80635.356950 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 75467.902857 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75467.902857 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342255 # number of replacements -system.l2c.tags.tagsinuse 65190.453062 # Cycle average of tags in use -system.l2c.tags.total_refs 3793407 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407257 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 9.314529 # Average number of references to valid blocks. +system.l2c.tags.replacements 342160 # number of replacements +system.l2c.tags.tagsinuse 65166.105156 # Cycle average of tags in use +system.l2c.tags.total_refs 3684821 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407166 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 9.049923 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 12928623000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54971.310995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3771.999936 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4805.186829 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1123.175084 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 518.780218 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.838796 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057556 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.073321 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017138 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007916 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994727 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65002 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1065 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 4849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6325 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52587 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.991852 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 36989627 # Number of tag accesses -system.l2c.tags.data_accesses 36989627 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 862671 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 862671 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 732220 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 732220 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 141 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 87 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 26 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 51 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 102038 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 98486 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200524 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 479778 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 508114 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 987892 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 344131 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 495524 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 839655 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.inst 479778 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 446169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 508114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 594010 # number of demand (read+write) hits -system.l2c.demand_hits::total 2028071 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 479778 # number of overall hits -system.l2c.overall_hits::cpu0.data 446169 # number of overall hits -system.l2c.overall_hits::cpu1.inst 508114 # number of overall hits -system.l2c.overall_hits::cpu1.data 594010 # number of overall hits -system.l2c.overall_hits::total 2028071 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 2602 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3085 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 77 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 94 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 171 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 103258 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 19364 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122622 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 10849 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 2603 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 13452 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 270704 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1159 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 271863 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.inst 10849 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 373962 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2603 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20523 # number of demand (read+write) misses -system.l2c.demand_misses::total 407937 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 10849 # number of overall misses -system.l2c.overall_misses::cpu0.data 373962 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2603 # number of overall misses -system.l2c.overall_misses::cpu1.data 20523 # number of overall misses -system.l2c.overall_misses::total 407937 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 3090000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2769500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5859500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 569500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 892000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1461500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 13105172500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2555486000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 15660658500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1419877000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 342190500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 1762067500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 33554759000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 151782000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 33706541000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1419877000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 46659931500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 342190500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2707268000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 51129267000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1419877000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 46659931500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 342190500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2707268000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 51129267000 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 862671 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 862671 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 732220 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 732220 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2743 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 570 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3313 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 102 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 120 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 222 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 205296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 117850 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 323146 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 490627 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 510717 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1001344 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 614835 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 496683 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 1111518 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 490627 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 820131 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 510717 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 614533 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2436008 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 490627 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 820131 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 510717 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 614533 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2436008 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948596 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.847368 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.931180 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.754902 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.783333 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.770270 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.502971 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.164311 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.379463 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.022113 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005097 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.013434 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.440287 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.244587 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.022113 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.455978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005097 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.033396 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.167461 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.022113 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.455978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005097 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.033396 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.167461 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1187.548040 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5733.954451 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1899.351702 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7396.103896 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9489.361702 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 8546.783626 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126916.776424 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131970.977071 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127714.916573 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130876.301963 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 131460.046101 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 130989.258103 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123953.687422 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 130959.447800 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 123983.554217 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 125336.184264 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 130876.301963 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 124771.852488 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 131460.046101 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 131913.852751 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 125336.184264 # average overall miss latency +system.l2c.tags.occ_blocks::writebacks 54852.926968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4798.887710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5355.521606 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 119.450047 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 39.318825 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.836989 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073225 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.081719 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000600 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994356 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65006 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5372 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6320 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52699 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991913 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 35902652 # Number of tag accesses +system.l2c.tags.data_accesses 35902652 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 792572 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 792572 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 746399 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 746399 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 546 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 730 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 39 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 63 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 124130 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 48550 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 172680 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 674563 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 331022 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1005585 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 659479 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 113775 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 773254 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.inst 674563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 783609 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 331022 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 162325 # number of demand (read+write) hits +system.l2c.demand_hits::total 1951519 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 674563 # number of overall hits +system.l2c.overall_hits::cpu0.data 783609 # number of overall hits +system.l2c.overall_hits::cpu1.inst 331022 # number of overall hits +system.l2c.overall_hits::cpu1.data 162325 # number of overall hits +system.l2c.overall_hits::total 1951519 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 2975 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1806 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4781 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 926 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 932 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1858 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 114977 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7880 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122857 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 12505 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 950 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 13455 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 271539 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 337 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 271876 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.inst 12505 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 386516 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 950 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8217 # number of demand (read+write) misses +system.l2c.demand_misses::total 408188 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 12505 # number of overall misses +system.l2c.overall_misses::cpu0.data 386516 # number of overall misses +system.l2c.overall_misses::cpu1.inst 950 # number of overall misses +system.l2c.overall_misses::cpu1.data 8217 # number of overall misses +system.l2c.overall_misses::total 408188 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 3844000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 36525000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 40369000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3483500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 976000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 4459500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 14619274000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1040489500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 15659763500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1640042500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 125494500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 1765537000 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 33667193000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 43268500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 33710461500 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1640042500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 48286467000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 125494500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1083758000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 51135762000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1640042500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 48286467000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 125494500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1083758000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 51135762000 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 792572 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 792572 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 746399 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 746399 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3159 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5511 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 965 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 956 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1921 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 239107 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 56430 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295537 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 687068 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 331972 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1019040 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 931018 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 114112 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 1045130 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 687068 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1170125 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 331972 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 170542 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2359707 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 687068 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1170125 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 331972 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 170542 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2359707 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941754 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.767857 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.867538 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.959585 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974895 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.967205 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.480860 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.139642 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.415708 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.018201 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.002862 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.013204 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.291658 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.002953 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.260136 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018201 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.330320 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.002862 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.048182 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172982 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018201 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.330320 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.002862 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.048182 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172982 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1292.100840 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 20224.252492 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 8443.631040 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3761.879050 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1047.210300 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 2400.161464 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 127149.551649 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 132041.814721 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 127463.339492 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 131150.939624 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 132099.473684 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 131217.911557 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 123986.583879 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 128393.175074 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 123992.046006 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 131150.939624 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 124927.472601 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 132099.473684 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 131892.174760 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 125275.025233 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 131150.939624 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 124927.472601 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 132099.473684 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 131892.174760 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 125275.025233 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1526,248 +1517,248 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79536 # number of writebacks -system.l2c.writebacks::total 79536 # number of writebacks +system.l2c.writebacks::writebacks 79420 # number of writebacks +system.l2c.writebacks::total 79420 # number of writebacks system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 11 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 9 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 9 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2602 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3085 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 77 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 94 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 171 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 103258 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 19364 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 122622 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 10849 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 2592 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 13441 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 270704 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1159 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 271863 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 10849 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 373962 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2592 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 20523 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 407926 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 10849 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 373962 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2592 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 20523 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 407926 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 4814 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 2385 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 7199 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 8193 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4228 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 12421 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 13007 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 6613 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 19620 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 186370500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 34557500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 220928000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 5513500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6719500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 12233000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 12072592500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2361846000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 14434438500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1311387000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 314915500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 1626302500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30847719000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 140192000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 30987911000 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1311387000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 42920311500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 314915500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2502038000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 47048652000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1311387000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 42920311500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 314915500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2502038000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 47048652000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1012133000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 490208000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1502341000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1745847000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 944283500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2690130500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2757980000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1434491500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4192471500 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2975 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1806 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4781 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 926 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 932 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1858 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 114977 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7880 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122857 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 12505 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 939 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 13444 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 271539 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 337 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 271876 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 12505 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 386516 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 939 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8217 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408177 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 12505 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 386516 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 939 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8217 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408177 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7080 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 118 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 7198 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10780 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3348 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 14128 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17860 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3466 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 21326 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 213181000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 129464500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 342645500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 66045000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 66671000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 132716000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13469504000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 961689500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 14431193500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1514992500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 114749500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 1629742000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 30951803000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 39898500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 30991701500 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1514992500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 44421307000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 114749500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1001588000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 47052637000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1514992500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 44421307000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 114749500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1001588000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 47052637000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1477620500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23575500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1501196000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2327025500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 750968500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 3077994000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3804646000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 774544000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4579190000 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.948596 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.847368 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.931180 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.754902 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.783333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770270 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.502971 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.164311 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.379463 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013423 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.440287 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002333 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.244587 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.167457 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022113 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.455978 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005075 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.033396 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.167457 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71625.864719 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71547.619048 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71613.614263 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71603.896104 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71484.042553 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71538.011696 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116916.776424 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121970.977071 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117714.916573 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120995.647645 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113953.687422 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 120959.447800 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113983.554217 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120876.301963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114771.852488 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 121495.177469 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121913.852751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 115336.242358 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210247.818862 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 205537.945493 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208687.456591 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 213090.076895 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 223340.468307 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 216579.220675 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 212038.133313 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 216919.930440 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 213683.562691 # average overall mshr uncacheable latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941754 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.767857 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.867538 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.959585 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.974895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967205 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.480860 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.139642 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415708 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.018201 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002829 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013193 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.291658 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.002953 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260136 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.330320 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002829 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.048182 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172978 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.330320 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002829 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.048182 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172978 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 71657.478992 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 71685.769657 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 71668.165656 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71322.894168 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 71535.407725 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 71429.494080 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 117149.551649 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122041.814721 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117463.339492 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 121224.486760 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 113986.583879 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 118393.175074 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 113992.046006 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 114927.472601 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121892.174760 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 115275.081644 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121150.939624 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 114927.472601 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122203.940362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121892.174760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 115275.081644 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208703.460452 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 199792.372881 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 208557.377049 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 215865.074212 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 224303.614098 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 217864.807475 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 213026.091825 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 223469.128679 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 214723.342399 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 7199 # Transaction distribution -system.membus.trans_dist::ReadResp 292680 # Transaction distribution -system.membus.trans_dist::WriteReq 12421 # Transaction distribution -system.membus.trans_dist::WriteResp 12421 # Transaction distribution -system.membus.trans_dist::WritebackDirty 121058 # Transaction distribution -system.membus.trans_dist::CleanEvict 261934 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4921 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1238 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3449 # Transaction distribution -system.membus.trans_dist::ReadExReq 122558 # Transaction distribution -system.membus.trans_dist::ReadExResp 122429 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 285481 # Transaction distribution +system.membus.trans_dist::ReadReq 7198 # Transaction distribution +system.membus.trans_dist::ReadResp 292693 # Transaction distribution +system.membus.trans_dist::WriteReq 14128 # Transaction distribution +system.membus.trans_dist::WriteResp 14128 # Transaction distribution +system.membus.trans_dist::WritebackDirty 120940 # Transaction distribution +system.membus.trans_dist::CleanEvict 261948 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16888 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11786 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7203 # Transaction distribution +system.membus.trans_dist::ReadExReq 123166 # Transaction distribution +system.membus.trans_dist::ReadExResp 122293 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285495 # Transaction distribution system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39240 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1166399 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1205639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124831 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124831 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1330470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 68786 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31168512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31237298 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2658368 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33895666 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3262 # Total snoops (count) -system.membus.snoop_fanout::samples 858545 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42652 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1193065 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1235717 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1360544 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82434 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31153280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31235714 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33893954 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 22770 # Total snoops (count) +system.membus.snoop_fanout::samples 883282 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 858545 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 883282 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 858545 # Request fanout histogram -system.membus.reqLayer0.occupancy 36672500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 883282 # Request fanout histogram +system.membus.reqLayer0.occupancy 40488000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1323961648 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1327709899 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2184136804 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2192713302 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 69798217 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 69791959 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4935792 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2467069 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 374533 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 1240 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 1179 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 7199 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2152619 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12421 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12421 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 983748 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 732220 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 760785 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4956 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1289 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6245 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 324079 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 324079 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1001367 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 1144069 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 4790563 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2395444 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 362000 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 1241 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 1181 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 60 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2107005 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14128 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14128 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 913531 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 746399 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 756600 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 17054 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11849 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28903 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297620 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297620 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1019067 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 1080755 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 41552 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1377223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478366 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1357708 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1834010 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7047307 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56740736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 76009449 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 54207360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 71099081 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 258056626 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 461903 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2920905 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.131024 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.337667 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1917007 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3544626 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 867499 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 539645 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6868777 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 78714432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118015028 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34273664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 18604942 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 249608066 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 484792 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2873097 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.137110 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.344206 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2538432 86.91% 86.91% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 382238 13.09% 99.99% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2479406 86.30% 86.30% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 393455 13.69% 99.99% # Request fanout histogram system.toL2Bus.snoop_fanout::2 234 0.01% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 2 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2920905 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4346798496 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2873097 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4223463995 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 299383 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 297883 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 736191563 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1248608962 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1030900979 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1802313287 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 767009132 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 499097220 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 969915969 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 293862892 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 0f3bcf1b2..7dba6063a 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -15,10 +15,10 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/work/gem5/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/work/gem5/dist/binaries/vmlinux kernel_addr_check=true load_addr_mask=1099511627775 load_offset=0 @@ -28,8 +28,8 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +pal=/work/gem5/dist/binaries/ts_osfpal +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh symbolfile= system_rev=1024 system_type=34 @@ -279,7 +279,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -302,7 +302,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.dvfs_handler] @@ -325,10 +325,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.tsunami.pciconfig.pio -master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side +master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma [system.iocache] @@ -355,7 +354,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[29] +cpu_side=system.iobus.master[27] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -490,7 +489,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/work/gem5/dist/disks/linux-latest.img read_only=true [system.terminal] @@ -503,7 +502,7 @@ port=3456 [system.tsunami] type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart +children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart eventq_index=0 intrctrl=system.intrctrl system=system @@ -616,12 +615,12 @@ dma_write_delay=0 dma_write_factor=0 eventq_index=0 hardware_address=00:90:00:00:00:01 +host=system.tsunami.pchip intr_delay=10000000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.tsunami rss=false rx_delay=1000000 rx_fifo_size=524288 @@ -631,9 +630,8 @@ system=system tx_delay=1000000 tx_fifo_size=524288 tx_thread=false -config=system.iobus.master[28] dma=system.iobus.slave[2] -pio=system.iobus.master[27] +pio=system.iobus.master[26] [system.tsunami.fake_OROM] type=IsaFake @@ -1066,14 +1064,13 @@ config_latency=20000 ctrl_offset=0 disks=system.disk0 system.disk2 eventq_index=0 +host=system.tsunami.pchip io_shift=0 pci_bus=0 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.tsunami system=system -config=system.iobus.master[26] dma=system.iobus.slave[1] pio=system.iobus.master[25] @@ -1093,25 +1090,20 @@ pio=system.iobus.master[22] [system.tsunami.pchip] type=TsunamiPChip clk_domain=system.clk_domain +conf_base=8804649402368 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 +pci_dma_base=0 +pci_mem_base=8796093022208 +pci_pio_base=8804615847936 pio_addr=8802535473152 pio_latency=100000 +platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.master[1] -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -clk_domain=system.clk_domain -eventq_index=0 -pio_addr=0 -pio_latency=30000 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - [system.tsunami.uart] type=Uart8250 clk_domain=system.clk_domain diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index a1d7247d8..d6487ca92 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 15 2015 14:28:00 -gem5 started Nov 15 2015 14:29:48 -gem5 executing on ribera.cs.wisc.edu, pid 29118 -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing +gem5 compiled Dec 4 2015 10:28:58 +gem5 started Dec 4 2015 10:54:46 +gem5 executing on e104799-lin, pid 24468 +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux +info: kernel located at: /work/gem5/dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1941275996000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index df40ca5c9..aff568203 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.941276 # Nu sim_ticks 1941275996000 # Number of ticks simulated final_tick 1941275996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 815122 # Simulator instruction rate (inst/s) -host_op_rate 815122 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28164805778 # Simulator tick rate (ticks/s) -host_mem_usage 368252 # Number of bytes of host memory used -host_seconds 68.93 # Real time elapsed on the host +host_inst_rate 921196 # Simulator instruction rate (inst/s) +host_op_rate 921196 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31829968739 # Simulator tick rate (ticks/s) +host_mem_usage 330408 # Number of bytes of host memory used +host_seconds 60.99 # Real time elapsed on the host sim_insts 56182743 # Number of instructions simulated sim_ops 56182743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -197,23 +197,23 @@ system.physmem.wrQLenPdf::60 62 # Wh system.physmem.wrQLenPdf::61 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 51 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64941 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 509.747124 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 310.189706 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 406.049901 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15359 23.65% 23.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11448 17.63% 41.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4958 7.63% 48.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3153 4.86% 53.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 64945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.715729 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 310.174215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 406.042967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15358 23.65% 23.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11454 17.64% 41.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4958 7.63% 48.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3153 4.85% 53.77% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 2453 3.78% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4206 6.48% 64.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1429 2.20% 66.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4205 6.47% 64.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1430 2.20% 66.23% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2063 3.18% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19872 30.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64941 # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19871 30.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64945 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5113 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 78.517700 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2951.127642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2951.127633 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-8191 5110 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes @@ -259,12 +259,12 @@ system.physmem.wrPerTurnAround::200-203 1 0.02% 99.96% # Wr system.physmem.wrPerTurnAround::212-215 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5113 # Writes before turning the bus around for reads -system.physmem.totQLat 2717940750 # Total ticks spent queuing -system.physmem.totMemAccLat 10245709500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2718840250 # Total ticks spent queuing +system.physmem.totMemAccLat 10246609000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2007405000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6769.79 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6772.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25519.79 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25522.03 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.24 # Average system read bandwidth in MiByte/s @@ -276,38 +276,38 @@ system.physmem.busUtilWrite 0.03 # Da system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 22.09 # Average write queue length when enqueuing system.physmem.readRowHits 358828 # Number of row buffer hits during reads -system.physmem.writeRowHits 93473 # Number of row buffer hits during writes +system.physmem.writeRowHits 93469 # Number of row buffer hits during writes system.physmem.readRowHitRate 89.38 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.72 # Row buffer hit rate for writes system.physmem.avgGap 3752025.30 # Average gap between requests system.physmem.pageHitRate 87.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 240362640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 131150250 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 240377760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131158500 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 1565912400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 373358160 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 71531321220 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1102018756500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1302655548930 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.030615 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1833026995250 # Time in different power states +system.physmem_0.actBackEnergy 71534855790 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1102015656000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1302656006370 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.030850 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1833021874000 # Time in different power states system.physmem_0.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 43425441000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 43430562250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 250591320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 136731375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 250606440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136739625 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1565639400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 376773120 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 126794687760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 72715172175 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1100980290750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1302819885900 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.115269 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1831298493250 # Time in different power states +system.physmem_1.actBackEnergy 72705843270 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1100988474000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1302818763615 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.114691 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1831312114000 # Time in different power states system.physmem_1.memoryStateTime::REF 64823460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 45153943000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 45140322250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -358,10 +358,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1935 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73545 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149156 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1860509644500 95.84% 95.84% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1860509805500 95.84% 95.84% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 94040000 0.00% 95.84% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 770515500 0.04% 95.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 79901062000 4.12% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 79900901000 4.12% 100.00% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::total 1941275262000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl @@ -523,16 +523,16 @@ system.cpu.dcache.demand_misses::cpu.data 1373670 # n system.cpu.dcache.demand_misses::total 1373670 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1373670 # number of overall misses system.cpu.dcache.overall_misses::total 1373670 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 44770870500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 44770870500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634139000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17634139000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232897500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 232897500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 62405009500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 62405009500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 62405009500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 62405009500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 44771016500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 44771016500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17634519000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17634519000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 232810500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 232810500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 62405535500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 62405535500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 62405535500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 62405535500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8883757 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8883757 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6156599 # number of WriteReq accesses(hits+misses) @@ -555,16 +555,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.091332 system.cpu.dcache.demand_miss_rate::total 0.091332 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091332 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091332 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.681715 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.681715 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57944.517100 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 57944.517100 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13503.652809 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13503.652809 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45429.404078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.404078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45429.404078 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41867.818247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41867.818247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 57945.765753 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 57945.765753 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13498.608454 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13498.608454 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45429.786994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45429.786994 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45429.786994 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,22 +591,22 @@ system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 9653 system.cpu.dcache.WriteReq_mshr_uncacheable::total 9653 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 16583 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701528500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701528500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17329811000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17329811000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215650500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215650500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031339500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 61031339500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031339500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 61031339500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1527878500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1527878500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43701674500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43701674500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17330191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17330191000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 215563500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 215563500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 61031865500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 61031865500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 61031865500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 61031865500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1526978500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1526978500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2172467000 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2172467000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3700345500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3700345500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3699445500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3699445500 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120370 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120370 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049431 # mshr miss rate for WriteReq accesses @@ -617,22 +617,22 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091332 system.cpu.dcache.demand_mshr_miss_rate::total 0.091332 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091332 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091332 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.681715 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.681715 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56944.517100 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56944.517100 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12503.652809 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12503.652809 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.404078 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.404078 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220473.088023 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220473.088023 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40867.818247 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40867.818247 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56945.765753 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56945.765753 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12498.608454 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12498.608454 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44429.786994 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44429.786994 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 220343.217893 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220343.217893 # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 225056.148348 # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 225056.148348 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223140.897304 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223140.897304 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 223086.624857 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 223086.624857 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 928920 # number of replacements system.cpu.icache.tags.tagsinuse 506.355618 # Cycle average of tags in use @@ -663,12 +663,12 @@ system.cpu.icache.demand_misses::cpu.inst 929591 # n system.cpu.icache.demand_misses::total 929591 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 929591 # number of overall misses system.cpu.icache.overall_misses::total 929591 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686380500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13686380500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13686380500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13686380500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13686380500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13686380500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13686841500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13686841500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13686841500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13686841500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13686841500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13686841500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56194577 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56194577 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56194577 # number of demand (read+write) accesses @@ -681,12 +681,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016542 system.cpu.icache.demand_miss_rate::total 0.016542 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016542 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016542 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.013132 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14723.013132 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.013132 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14723.013132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.013132 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14723.013132 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14723.509049 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14723.509049 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14723.509049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14723.509049 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14723.509049 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -703,34 +703,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 929591 system.cpu.icache.demand_mshr_misses::total 929591 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 929591 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 929591 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12756789500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12756789500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12756789500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12756789500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12756789500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12756789500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12757250500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12757250500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12757250500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12757250500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12757250500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12757250500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016542 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016542 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016542 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016542 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.013132 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.013132 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.013132 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.013132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.013132 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.013132 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13723.509049 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13723.509049 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13723.509049 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13723.509049 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 336393 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65234.360025 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 65234.360010 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3930350 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 401556 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.787800 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 10619817000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.115204 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418504 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 55072.826279 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4686.115262 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5475.418469 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.840345 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071504 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.083548 # Average percentage of cache occupancy @@ -778,18 +778,18 @@ system.cpu.l2cache.overall_misses::cpu.data 388791 # system.cpu.l2cache.overall_misses::total 401991 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 320500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 320500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900273000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14900273000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727207500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727207500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719775000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719775000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1727207500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 48620048000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 50347255500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1727207500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 48620048000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 50347255500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14900653000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14900653000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1727668500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1727668500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 33719834000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 33719834000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1727668500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 48620487000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 50348155500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1727668500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 48620487000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 50348155500 # number of overall miss cycles system.cpu.l2cache.WritebackDirty_accesses::writebacks 834936 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackDirty_accesses::total 834936 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 928699 # number of WritebackClean accesses(hits+misses) @@ -824,18 +824,18 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.279525 system.cpu.l2cache.overall_miss_rate::total 0.173237 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 24653.846154 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 24653.846154 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127548.989899 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127548.989899 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130849.053030 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130849.053030 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123982.979803 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123982.979803 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130849.053030 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125054.458565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 125244.733091 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130849.053030 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125054.458565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 125244.733091 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127552.242767 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127552.242767 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130883.977273 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130883.977273 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123983.196738 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123983.196738 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 125246.971947 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130883.977273 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 125055.587707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 125246.971947 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -868,24 +868,24 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 16583 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16583 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 924500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 924500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732073000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732073000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595207500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595207500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000065000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000065000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595207500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732138000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46327345500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595207500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732138000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46327345500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1441222500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1441222500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13732453000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13732453000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1595668500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1595668500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31000124000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31000124000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1595668500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 44732577000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46328245500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1595668500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 44732577000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46328245500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1440322500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1440322500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2061377000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2061377000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3502599500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3502599500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3501699500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3501699500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383884 # mshr miss rate for ReadExReq accesses @@ -902,24 +902,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279525 system.cpu.l2cache.overall_mshr_miss_rate::total 0.173237 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71115.384615 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71115.384615 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117548.989899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117548.989899 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120849.053030 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120849.053030 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113982.979803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113982.979803 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120849.053030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115054.458565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115244.733091 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207968.614719 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207968.614719 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117552.242767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117552.242767 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120883.977273 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120883.977273 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 113983.196738 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 113983.196738 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120883.977273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 115055.587707 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 115246.971947 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 207838.744589 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 207838.744589 # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 213547.808971 # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 213547.808971 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211216.275704 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211216.275704 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 211162.003256 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 211162.003256 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.snoop_filter.tot_requests 4639815 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 2319473 # Number of requests hitting in the snoop filter with a single holder of the requested data. @@ -984,40 +984,34 @@ system.iobus.trans_dist::ReadResp 7103 # Tr system.iobus.trans_dist::WriteReq 51205 # Transaction distribution system.iobus.trans_dist::WriteResp 51205 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5162 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 33166 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116616 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2717 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 44588 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2706196 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 5340500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 371000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 759000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1031,16 +1025,10 @@ system.iobus.reqLayer24.occupancy 1891500 # La system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 212000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 82500 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 215014002 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 131000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 215014002 # Layer occupancy (ticks) -system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer30.occupancy 45000 # Layer occupancy (ticks) -system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23513000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 41946000 # Layer occupancy (ticks) @@ -1183,7 +1171,7 @@ system.membus.reqLayer0.occupancy 30116000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 1287207146 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2143288852 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2143289352 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 69814679 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini index 2db2ddc0e..ec0c9ed73 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -419,10 +419,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -449,7 +448,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -512,12 +511,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -610,16 +606,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -635,7 +630,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -798,13 +793,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -814,9 +809,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -858,7 +852,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -939,14 +933,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -963,7 +956,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -978,7 +971,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1101,17 +1094,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1163,7 +1158,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1178,7 +1173,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json index 8406c4bfc..ecb1a29da 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/config.json @@ -19,10 +19,6 @@ "role": "SLAVE" }, "name": "iobus", - "default": { - "peer": "system.realview.pciconfig.pio", - "role": "MASTER" - }, "forward_latency": 1, "clk_domain": "system.clk_domain", "width": 16, @@ -31,6 +27,7 @@ "peer": [ "system.realview.uart.pio", "system.realview.realview_io.pio", + "system.realview.pci_host.pio", "system.realview.timer0.pio", "system.realview.timer1.pio", "system.realview.clcd.pio", @@ -38,7 +35,6 @@ "system.realview.kmi0.pio", "system.realview.kmi1.pio", "system.realview.cf_ctrl.pio", - "system.realview.cf_ctrl.config", "system.realview.rtc.pio", "system.realview.vram.port", "system.realview.l2x0_fake.pio", @@ -53,9 +49,7 @@ "system.realview.mmc_fake.pio", "system.realview.energy_ctrl.pio", "system.realview.ide.pio", - "system.realview.ide.config", "system.realview.ethernet.pio", - "system.realview.ethernet.config", "system.iocache.cpu_side" ], "role": "MASTER" @@ -64,11 +58,11 @@ "cxx_class": "NoncoherentXBar", "path": "system.iobus", "type": "NoncoherentXBar", - "use_default_range": true, + "use_default_range": false, "frontend_latency": 2 }, "symbolfile": "", - "readfile": "/work/gem5/outgoing/gem5/tests/halt.sh", + "readfile": "/work/gem5/outgoing/gem5_2/tests/halt.sh", "have_large_asid_64": false, "phys_addr_range_64": 40, "have_lpae": false, @@ -115,7 +109,7 @@ "workaround_dma_line_count": true, "amba_id": 1314816, "pio": { - "peer": "system.iobus.master[5]", + "peer": "system.iobus.master[6]", "role": "SLAVE" }, "pio_latency": 10000, @@ -174,7 +168,23 @@ "pio_addr": 471269376, "type": "PL031" }, - "pci_cfg_gen_offsets": false, + "watchdog_fake": { + "name": "watchdog_fake", + "pio": { + "peer": "system.iobus.master[17]", + "role": "SLAVE" + }, + "amba_id": 0, + "ignore_access": false, + "pio_latency": 100000, + "clk_domain": "system.clk_domain", + "system": "system", + "eventq_index": 0, + "cxx_class": "AmbaFake", + "path": "system.realview.watchdog_fake", + "pio_addr": 470745088, + "type": "AmbaFake" + }, "vgic": { "system": "system", "name": "vgic", @@ -348,7 +358,7 @@ "timer1": { "name": "timer1", "pio": { - "peer": "system.iobus.master[3]", + "peer": "system.iobus.master[4]", "role": "SLAVE" }, "amba_id": 1316868, @@ -369,7 +379,7 @@ "timer0": { "name": "timer0", "pio": { - "peer": "system.iobus.master[2]", + "peer": "system.iobus.master[3]", "role": "SLAVE" }, "amba_id": 1316868, @@ -422,6 +432,26 @@ "pio_addr": 470286336 }, "type": "RealView", + "pci_host": { + "conf_size": 268435456, + "name": "pci_host", + "conf_device_bits": 16, + "pio": { + "peer": "system.iobus.master[2]", + "role": "SLAVE" + }, + "conf_base": 805306368, + "clk_domain": "system.clk_domain", + "system": "system", + "pci_dma_base": 0, + "platform": "system.realview", + "eventq_index": 0, + "cxx_class": "GenericPciHost", + "path": "system.realview.pci_host", + "pci_pio_base": 0, + "type": "GenericPciHost", + "pci_mem_base": 0 + }, "lan_fake": { "system": "system", "ret_data8": 255, @@ -617,25 +647,6 @@ "type": "RealViewOsc" } }, - "pciconfig": { - "name": "pciconfig", - "pio": { - "peer": "system.iobus.default", - "role": "SLAVE" - }, - "bus": 0, - "pio_latency": 30000, - "clk_domain": "system.clk_domain", - "system": "system", - "platform": "system.realview", - "eventq_index": 0, - "cxx_class": "PciConfigAll", - "path": "system.realview.pciconfig", - "pio_addr": 0, - "type": "PciConfigAll", - "size": 268435456 - }, - "pci_cfg_base": 805306368, "path": "system.realview", "vram": { "range": "402653184:436207615", @@ -656,7 +667,6 @@ }, "in_addr_map": true }, - "pci_io_base": 0, "nvmem": { "range": "0:67108863", "latency": 30000, @@ -685,7 +695,7 @@ "vnc": "system.vncserver", "name": "clcd", "pio": { - "peer": "system.iobus.master[4]", + "peer": "system.iobus.master[5]", "role": "SLAVE" }, "amba_id": 1315089, @@ -723,30 +733,13 @@ "pio_addr": 470351872, "type": "Pl011" }, - "watchdog_fake": { - "name": "watchdog_fake", - "pio": { - "peer": "system.iobus.master[17]", - "role": "SLAVE" - }, - "amba_id": 0, - "ignore_access": false, - "pio_latency": 100000, - "clk_domain": "system.clk_domain", - "system": "system", - "eventq_index": 0, - "cxx_class": "AmbaFake", - "path": "system.realview.watchdog_fake", - "pio_addr": 470745088, - "type": "AmbaFake" - }, "intrctrl": "system.intrctrl", "kmi1": { "vnc": "system.vncserver", "name": "kmi1", "int_delay": 1000000, "pio": { - "peer": "system.iobus.master[7]", + "peer": "system.iobus.master[8]", "role": "SLAVE" }, "amba_id": 1314896, @@ -767,7 +760,7 @@ "name": "kmi0", "int_delay": 1000000, "pio": { - "peer": "system.iobus.master[6]", + "peer": "system.iobus.master[7]", "role": "SLAVE" }, "amba_id": 1314896, @@ -794,7 +787,6 @@ "Revision": 0, "LegacyIOBase": 0, "pio_latency": 30000, - "platform": "system.realview", "PXCAPLinkCap": 0, "CapabilityPtr": 0, "MSIXCAPBaseOffset": 0, @@ -828,6 +820,7 @@ "PXCAPDevCap2": 0, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, + "host": "system.realview.pci_host", "Command": 1, "SubClassCode": 1, "pci_func": 0, @@ -862,7 +855,7 @@ "config_latency": 20000, "BAR1Size": 4096, "pio": { - "peer": "system.iobus.master[8]", + "peer": "system.iobus.master[9]", "role": "SLAVE" }, "pci_dev": 0, @@ -871,10 +864,6 @@ "clk_domain": "system.clk_domain", "SubsystemVendorID": 0, "PMCAPBaseOffset": 0, - "config": { - "peer": "system.iobus.master[9]", - "role": "SLAVE" - }, "MSICAPPendingBits": 0, "MSIXTableOffset": 0, "MSICAPMsgUpperAddr": 0, @@ -914,7 +903,6 @@ "hardware_address": "00:90:00:00:00:01", "LegacyIOBase": 0, "pio_latency": 30000, - "platform": "system.realview", "PXCAPLinkCap": 0, "CapabilityPtr": 0, "MSIXCAPBaseOffset": 0, @@ -949,6 +937,7 @@ "PXCAPDevCap2": 0, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, + "host": "system.realview.pci_host", "Command": 0, "SubClassCode": 0, "pci_func": 0, @@ -986,7 +975,7 @@ "config_latency": 20000, "BAR1Size": 0, "pio": { - "peer": "system.iobus.master[25]", + "peer": "system.iobus.master[24]", "role": "SLAVE" }, "pci_dev": 0, @@ -997,10 +986,6 @@ "clk_domain": "system.clk_domain", "SubsystemVendorID": 32902, "PMCAPBaseOffset": 0, - "config": { - "peer": "system.iobus.master[26]", - "role": "SLAVE" - }, "MSICAPPendingBits": 0, "MSIXTableOffset": 0, "MSICAPMsgUpperAddr": 0, @@ -1025,7 +1010,6 @@ "Revision": 0, "LegacyIOBase": 0, "pio_latency": 30000, - "platform": "system.realview", "PXCAPLinkCap": 0, "CapabilityPtr": 0, "MSIXCAPBaseOffset": 0, @@ -1061,6 +1045,7 @@ "PXCAPDevCap2": 0, "PXCAPDevCtrl": 0, "MSICAPMaskBits": 0, + "host": "system.realview.pci_host", "Command": 0, "SubClassCode": 1, "pci_func": 0, @@ -1104,10 +1089,6 @@ "clk_domain": "system.clk_domain", "SubsystemVendorID": 0, "PMCAPBaseOffset": 0, - "config": { - "peer": "system.iobus.master[24]", - "role": "SLAVE" - }, "MSICAPPendingBits": 0, "MSIXTableOffset": 0, "MSICAPMsgUpperAddr": 0, @@ -1187,7 +1168,7 @@ "eventq_index": 0, "iocache": { "cpu_side": { - "peer": "system.iobus.master[27]", + "peer": "system.iobus.master[25]", "role": "SLAVE" }, "clusivity": "mostly_incl", diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt index 4f7058700..5b276d871 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-checkpoint/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 648383 # Simulator instruction rate (inst/s) -host_op_rate 789303 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12642549042 # Simulator tick rate (ticks/s) -host_mem_usage 580896 # Number of bytes of host memory used -host_seconds 220.20 # Real time elapsed on the host +host_inst_rate 948377 # Simulator instruction rate (inst/s) +host_op_rate 1154497 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18491991143 # Simulator tick rate (ticks/s) +host_mem_usage 582460 # Number of bytes of host memory used +host_seconds 150.54 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -589,6 +589,7 @@ system.iobus.trans_dist::WriteReq 59002 # Tr system.iobus.trans_dist::WriteResp 59002 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) @@ -604,16 +605,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) @@ -629,10 +628,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index 540fdcdef..6a7585bd4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -763,10 +763,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -793,7 +792,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -893,12 +892,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -991,16 +987,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -1016,7 +1011,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -1179,13 +1174,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1195,9 +1190,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -1239,7 +1233,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -1320,14 +1314,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1344,7 +1337,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -1359,7 +1352,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1482,17 +1475,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1544,7 +1539,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1559,7 +1554,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index d22933e16..581036fd9 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 15:54:29 -gem5 executing on e104799-lin, pid 1782 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 11:24:30 +gem5 executing on e104799-lin, pid 30065 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 5ccc65a5c..583c12b60 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.802895 # Nu sim_ticks 2802894699500 # Number of ticks simulated final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 515393 # Simulator instruction rate (inst/s) -host_op_rate 627998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9838648327 # Simulator tick rate (ticks/s) -host_mem_usage 594196 # Number of bytes of host memory used -host_seconds 284.89 # Real time elapsed on the host +host_inst_rate 917511 # Simulator instruction rate (inst/s) +host_op_rate 1117974 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17514936450 # Simulator tick rate (ticks/s) +host_mem_usage 594132 # Number of bytes of host memory used +host_seconds 160.03 # Real time elapsed on the host sim_insts 146828240 # Number of instructions simulated sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -1116,6 +1116,7 @@ system.iobus.trans_dist::WriteReq 59419 # Tr system.iobus.trans_dist::WriteResp 59419 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) @@ -1131,16 +1132,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) @@ -1156,10 +1155,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 2db2ddc0e..ec0c9ed73 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -419,10 +419,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -449,7 +448,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -512,12 +511,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -610,16 +606,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -635,7 +630,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -798,13 +793,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -814,9 +809,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -858,7 +852,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -939,14 +933,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -963,7 +956,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -978,7 +971,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1101,17 +1094,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1163,7 +1158,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1178,7 +1173,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 7352915d9..e8d7b453f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 15:54:29 -gem5 executing on e104799-lin, pid 1776 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 11:39:25 +gem5 executing on e104799-lin, pid 31608 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index ed7366920..58a48feae 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 528399 # Simulator instruction rate (inst/s) -host_op_rate 643241 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10303020007 # Simulator tick rate (ticks/s) -host_mem_usage 581016 # Number of bytes of host memory used -host_seconds 270.20 # Real time elapsed on the host +host_inst_rate 960961 # Simulator instruction rate (inst/s) +host_op_rate 1169816 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18737357971 # Simulator tick rate (ticks/s) +host_mem_usage 579868 # Number of bytes of host memory used +host_seconds 148.57 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -589,6 +589,7 @@ system.iobus.trans_dist::WriteReq 59002 # Tr system.iobus.trans_dist::WriteResp 59002 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) @@ -604,16 +605,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) @@ -629,10 +628,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 58c91ec69..cfa7c7917 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -755,10 +755,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -785,7 +784,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -949,12 +948,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -1047,16 +1043,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -1072,7 +1067,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -1235,13 +1230,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1251,9 +1246,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -1295,7 +1289,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -1376,14 +1370,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1400,7 +1393,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -1415,7 +1408,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1538,17 +1531,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1600,7 +1595,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1615,7 +1610,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 4bb037bf9..c04c65778 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 15:54:29 -gem5 executing on e104799-lin, pid 1787 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 13:19:17 +gem5 executing on e104799-lin, pid 9442 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 @@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2871819744000 because m5_exit instruction encountered +Exiting @ tick 2871850306000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index c9db9f143..4d40e792f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.871820 # Number of seconds simulated -sim_ticks 2871819744000 # Number of ticks simulated -final_tick 2871819744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.871850 # Number of seconds simulated +sim_ticks 2871850306000 # Number of ticks simulated +final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 357244 # Simulator instruction rate (inst/s) -host_op_rate 432116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7805602288 # Simulator tick rate (ticks/s) -host_mem_usage 614840 # Number of bytes of host memory used -host_seconds 367.92 # Real time elapsed on the host -sim_insts 131436334 # Number of instructions simulated -sim_ops 158983282 # Number of ops (including micro ops) simulated +host_inst_rate 595194 # Simulator instruction rate (inst/s) +host_op_rate 719909 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12993896386 # Simulator tick rate (ticks/s) +host_mem_usage 612660 # Number of bytes of host memory used +host_seconds 221.02 # Real time elapsed on the host +sim_insts 131546959 # Number of instructions simulated +sim_ops 159110973 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1155428 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1268388 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8606976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1178404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1267556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8608576 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 151764 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 551380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 345088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 129300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 549908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 341632 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12080624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1155428 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 151764 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1307192 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8516928 # Number of bytes written to this memory +system.physmem.bytes_read::total 12076912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1178404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 129300 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1307704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8530240 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8534492 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8547804 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26507 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26866 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134509 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2526 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8636 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5392 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2175 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5338 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 133077 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197850 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 133285 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 137468 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 137676 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 402333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 441667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2997046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 410329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 441373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2997571 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 52846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 191997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 120164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 45023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 191482 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 118959 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4206609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 402333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 52846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 455179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2965690 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4205272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 410329 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 45023 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 455352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2970294 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2971806 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2965690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2976410 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2970294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 402333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 447769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2997046 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 410329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 447475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2997571 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 52846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 192011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 120164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 45023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 191496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 118959 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7178416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197908 # Number of read requests accepted -system.physmem.writeReqs 137468 # Number of write requests accepted -system.physmem.readBursts 197908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 137468 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12655744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10368 # Total number of bytes read from write queue -system.physmem.bytesWritten 8547392 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12080624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8534492 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7181682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197850 # Number of read requests accepted +system.physmem.writeReqs 137676 # Number of write requests accepted +system.physmem.readBursts 197850 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 137676 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12652352 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue +system.physmem.bytesWritten 8560960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12076912 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8547804 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 64406 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11744 # Per bank write bursts -system.physmem.perBankRdBursts::1 11857 # Per bank write bursts -system.physmem.perBankRdBursts::2 11924 # Per bank write bursts -system.physmem.perBankRdBursts::3 11590 # Per bank write bursts -system.physmem.perBankRdBursts::4 20227 # Per bank write bursts -system.physmem.perBankRdBursts::5 11881 # Per bank write bursts -system.physmem.perBankRdBursts::6 12481 # Per bank write bursts -system.physmem.perBankRdBursts::7 12857 # Per bank write bursts -system.physmem.perBankRdBursts::8 12335 # Per bank write bursts -system.physmem.perBankRdBursts::9 12711 # Per bank write bursts -system.physmem.perBankRdBursts::10 11891 # Per bank write bursts -system.physmem.perBankRdBursts::11 11251 # Per bank write bursts -system.physmem.perBankRdBursts::12 11484 # Per bank write bursts -system.physmem.perBankRdBursts::13 11698 # Per bank write bursts -system.physmem.perBankRdBursts::14 10879 # Per bank write bursts -system.physmem.perBankRdBursts::15 10936 # Per bank write bursts -system.physmem.perBankWrBursts::0 8367 # Per bank write bursts -system.physmem.perBankWrBursts::1 8665 # Per bank write bursts -system.physmem.perBankWrBursts::2 8799 # Per bank write bursts -system.physmem.perBankWrBursts::3 8189 # Per bank write bursts -system.physmem.perBankWrBursts::4 7964 # Per bank write bursts -system.physmem.perBankWrBursts::5 8309 # Per bank write bursts -system.physmem.perBankWrBursts::6 8959 # Per bank write bursts -system.physmem.perBankWrBursts::7 8936 # Per bank write bursts -system.physmem.perBankWrBursts::8 8719 # Per bank write bursts -system.physmem.perBankWrBursts::9 9048 # Per bank write bursts -system.physmem.perBankWrBursts::10 8437 # Per bank write bursts -system.physmem.perBankWrBursts::11 8181 # Per bank write bursts -system.physmem.perBankWrBursts::12 8223 # Per bank write bursts -system.physmem.perBankWrBursts::13 7876 # Per bank write bursts -system.physmem.perBankWrBursts::14 7572 # Per bank write bursts -system.physmem.perBankWrBursts::15 7309 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 64578 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11583 # Per bank write bursts +system.physmem.perBankRdBursts::1 11800 # Per bank write bursts +system.physmem.perBankRdBursts::2 11971 # Per bank write bursts +system.physmem.perBankRdBursts::3 11847 # Per bank write bursts +system.physmem.perBankRdBursts::4 20098 # Per bank write bursts +system.physmem.perBankRdBursts::5 11961 # Per bank write bursts +system.physmem.perBankRdBursts::6 12460 # Per bank write bursts +system.physmem.perBankRdBursts::7 12487 # Per bank write bursts +system.physmem.perBankRdBursts::8 11821 # Per bank write bursts +system.physmem.perBankRdBursts::9 12495 # Per bank write bursts +system.physmem.perBankRdBursts::10 11828 # Per bank write bursts +system.physmem.perBankRdBursts::11 11338 # Per bank write bursts +system.physmem.perBankRdBursts::12 11476 # Per bank write bursts +system.physmem.perBankRdBursts::13 11922 # Per bank write bursts +system.physmem.perBankRdBursts::14 11270 # Per bank write bursts +system.physmem.perBankRdBursts::15 11336 # Per bank write bursts +system.physmem.perBankWrBursts::0 8288 # Per bank write bursts +system.physmem.perBankWrBursts::1 8566 # Per bank write bursts +system.physmem.perBankWrBursts::2 8821 # Per bank write bursts +system.physmem.perBankWrBursts::3 8522 # Per bank write bursts +system.physmem.perBankWrBursts::4 7854 # Per bank write bursts +system.physmem.perBankWrBursts::5 8398 # Per bank write bursts +system.physmem.perBankWrBursts::6 8910 # Per bank write bursts +system.physmem.perBankWrBursts::7 8793 # Per bank write bursts +system.physmem.perBankWrBursts::8 8333 # Per bank write bursts +system.physmem.perBankWrBursts::9 8912 # Per bank write bursts +system.physmem.perBankWrBursts::10 8495 # Per bank write bursts +system.physmem.perBankWrBursts::11 8357 # Per bank write bursts +system.physmem.perBankWrBursts::12 8083 # Per bank write bursts +system.physmem.perBankWrBursts::13 7998 # Per bank write bursts +system.physmem.perBankWrBursts::14 7822 # Per bank write bursts +system.physmem.perBankWrBursts::15 7613 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 22 # Number of times write queue was full causing retry -system.physmem.totGap 2871819304000 # Total gap between requests +system.physmem.numWrRetry 27 # Number of times write queue was full causing retry +system.physmem.totGap 2871849883000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9732 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188148 # Read request sizes (log2) +system.physmem.readPktSize::6 188090 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 133077 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 139055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 15611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6945 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4517 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 87 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 133285 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 138613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 10206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5467 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,163 +184,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.362371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 136.946957 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.393854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46305 52.93% 52.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17523 20.03% 72.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6069 6.94% 79.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3389 3.87% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2483 2.84% 86.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1521 1.74% 88.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 858 0.98% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 952 1.09% 90.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8385 9.58% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87485 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6517 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.342949 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 586.244331 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6515 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 87676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.950454 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 136.764211 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.933653 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46396 52.92% 52.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17641 20.12% 73.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5908 6.74% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3515 4.01% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2504 2.86% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1565 1.78% 88.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 855 0.98% 89.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 945 1.08% 90.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8347 9.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 87676 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6535 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.251262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 585.438505 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6533 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6517 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6517 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.493018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.920871 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.293044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5326 81.72% 81.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 466 7.15% 88.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 68 1.04% 89.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 161 2.47% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 25 0.38% 92.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 129 1.98% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.48% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 20 0.31% 95.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 32 0.49% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.28% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.14% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.11% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 150 2.30% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.11% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.37% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 5 0.08% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 4 0.06% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.05% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.14% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6517 # Writes before turning the bus around for reads -system.physmem.totQLat 4471540489 # Total ticks spent queuing -system.physmem.totMemAccLat 8179277989 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 988730000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22612.55 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6535 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.469013 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.883832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.598321 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5330 81.56% 81.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 483 7.39% 88.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 73 1.12% 90.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 153 2.34% 92.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 0.50% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 123 1.88% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 36 0.55% 95.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 26 0.40% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 25 0.38% 96.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.23% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.09% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 152 2.33% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.09% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.40% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.11% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6535 # Writes before turning the bus around for reads +system.physmem.totQLat 4503336233 # Total ticks spent queuing +system.physmem.totMemAccLat 8210079983 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 988465000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22779.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41362.55 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41529.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.95 # Average write queue length when enqueuing -system.physmem.readRowHits 164996 # Number of row buffer hits during reads -system.physmem.writeRowHits 78817 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.01 # Row buffer hit rate for writes -system.physmem.avgGap 8562983.95 # Average gap between requests -system.physmem.pageHitRate 73.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341636400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186408750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 815575800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 441858240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85932696690 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1647711485250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1923002863050 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.611581 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2740967841659 # Time in different power states -system.physmem_0.memoryStateTime::REF 95896320000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 22.35 # Average write queue length when enqueuing +system.physmem.readRowHits 165103 # Number of row buffer hits during reads +system.physmem.writeRowHits 78678 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.81 # Row buffer hit rate for writes +system.physmem.avgGap 8559246.92 # Average gap between requests +system.physmem.pageHitRate 73.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 341250840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 186198375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 812814600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441624960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85820448015 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647828636000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1923006208950 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.605484 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2741162536487 # Time in different power states +system.physmem_0.memoryStateTime::REF 95897360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34954258341 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34789668513 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 319750200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 174466875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726835200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 423565200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187573201920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85000293540 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1648529382750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1922747495685 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.522659 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2742335596201 # Time in different power states -system.physmem_1.memoryStateTime::REF 95896320000 # Time in different power states +system.physmem_1.actEnergy 321579720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 175465125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 729183000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 425172240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84866434740 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648665489750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1922758560735 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.519251 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742561244982 # Time in different power states +system.physmem_1.memoryStateTime::REF 95897360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33587665799 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33391555518 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -396,57 +394,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 8797 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 8797 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1607 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7190 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 8797 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 8797 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 8797 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7279 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12032.971562 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11059.534367 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6527.254746 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7242 99.49% 99.49% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 32 0.44% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7279 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 8830 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 8830 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1617 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7213 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 8830 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 8830 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 8830 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7312 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6252.045789 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7284 99.62% 99.62% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 24 0.33% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7312 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5719 78.57% 78.57% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1560 21.43% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7279 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8797 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5742 78.53% 78.53% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1570 21.47% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7312 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8830 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8797 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7279 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8830 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7312 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7279 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 16076 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7312 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 16142 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25745693 # DTB read hits -system.cpu0.dtb.read_misses 7581 # DTB read misses -system.cpu0.dtb.write_hits 19246585 # DTB write hits -system.cpu0.dtb.write_misses 1216 # DTB write misses +system.cpu0.dtb.read_hits 25809403 # DTB read hits +system.cpu0.dtb.read_misses 7606 # DTB read misses +system.cpu0.dtb.write_hits 19327142 # DTB write hits +system.cpu0.dtb.write_misses 1224 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3751 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3761 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1856 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1861 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25753274 # DTB read accesses -system.cpu0.dtb.write_accesses 19247801 # DTB write accesses +system.cpu0.dtb.read_accesses 25817009 # DTB read accesses +system.cpu0.dtb.write_accesses 19328366 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 44992278 # DTB hits -system.cpu0.dtb.misses 8797 # DTB misses -system.cpu0.dtb.accesses 45001075 # DTB accesses +system.cpu0.dtb.hits 45136545 # DTB hits +system.cpu0.dtb.misses 8830 # DTB misses +system.cpu0.dtb.accesses 45145375 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -484,12 +481,12 @@ system.cpu0.itb.walker.walkWaitTime::samples 3674 system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12417.119565 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11509.653289 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6255.531301 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2268 88.04% 88.04% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 277 10.75% 98.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 28 1.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6240.244766 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2261 87.77% 87.77% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 282 10.95% 98.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 30 1.16% 99.88% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency @@ -507,7 +504,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 121573780 # ITB inst hits +system.cpu0.itb.inst_hits 121850168 # ITB inst hits system.cpu0.itb.inst_misses 3674 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -524,172 +521,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 121577454 # ITB inst accesses -system.cpu0.itb.hits 121573780 # DTB hits +system.cpu0.itb.inst_accesses 121853842 # ITB inst accesses +system.cpu0.itb.hits 121850168 # DTB hits system.cpu0.itb.misses 3674 # DTB misses -system.cpu0.itb.accesses 121577454 # DTB accesses -system.cpu0.numCycles 5743639488 # number of cpu cycles simulated +system.cpu0.itb.accesses 121853842 # DTB accesses +system.cpu0.numCycles 5743700612 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1907 # number of quiesce instructions executed -system.cpu0.committedInsts 117757184 # Number of instructions committed -system.cpu0.committedOps 142314769 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 125928094 # Number of integer alu accesses +system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed +system.cpu0.committedInsts 118029542 # Number of instructions committed +system.cpu0.committedOps 142673635 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 126253590 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses -system.cpu0.num_func_calls 12772213 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 16007583 # number of instructions that are conditional controls -system.cpu0.num_int_insts 125928094 # number of integer instructions +system.cpu0.num_func_calls 12792333 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 16043976 # number of instructions that are conditional controls +system.cpu0.num_int_insts 126253590 # number of integer instructions system.cpu0.num_fp_insts 11483 # number of float instructions -system.cpu0.num_int_register_reads 231704258 # number of times the integer registers were read -system.cpu0.num_int_register_writes 87445622 # number of times the integer registers were written +system.cpu0.num_int_register_reads 232324144 # number of times the integer registers were read +system.cpu0.num_int_register_writes 87654298 # number of times the integer registers were written system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 515435615 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 53492348 # number of times the CC registers were written -system.cpu0.num_mem_refs 46148278 # number of memory refs -system.cpu0.num_load_insts 26004695 # Number of load instructions -system.cpu0.num_store_insts 20143583 # Number of store instructions -system.cpu0.num_idle_cycles 5456012961.442100 # Number of idle cycles -system.cpu0.num_busy_cycles 287626526.557900 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050077 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949923 # Percentage of idle cycles -system.cpu0.Branches 29545337 # Number of branches fetched +system.cpu0.num_cc_register_reads 516734560 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 53610723 # number of times the CC registers were written +system.cpu0.num_mem_refs 46299073 # number of memory refs +system.cpu0.num_load_insts 26069844 # Number of load instructions +system.cpu0.num_store_insts 20229229 # Number of store instructions +system.cpu0.num_idle_cycles 5455076908.366100 # Number of idle cycles +system.cpu0.num_busy_cycles 288623703.633900 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050250 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949750 # Percentage of idle cycles +system.cpu0.Branches 29603215 # Number of branches fetched system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 99836654 68.33% 68.33% # Class of executed instruction -system.cpu0.op_class::IntMult 112117 0.08% 68.41% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8321 0.01% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.41% # Class of executed instruction -system.cpu0.op_class::MemRead 26004695 17.80% 86.21% # Class of executed instruction -system.cpu0.op_class::MemWrite 20143583 13.79% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 100054313 68.31% 68.31% # Class of executed instruction +system.cpu0.op_class::IntMult 112340 0.08% 68.39% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8369 0.01% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.39% # Class of executed instruction +system.cpu0.op_class::MemRead 26069844 17.80% 86.19% # Class of executed instruction +system.cpu0.op_class::MemWrite 20229229 13.81% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146107685 # Class of executed instruction -system.cpu0.dcache.tags.replacements 732170 # number of replacements -system.cpu0.dcache.tags.tagsinuse 488.694805 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 44080957 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 732682 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 60.163832 # Average number of references to valid blocks. +system.cpu0.op_class::total 146476410 # Class of executed instruction +system.cpu0.dcache.tags.replacements 740882 # number of replacements +system.cpu0.dcache.tags.tagsinuse 488.760528 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 44216040 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 741394 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 59.639058 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.694805 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954482 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.954482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.760528 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954610 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.954610 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90660887 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90660887 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 24440244 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 24440244 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 18493380 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18493380 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 326498 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 326498 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374202 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374202 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 371573 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 371573 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 42933624 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 42933624 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 43260122 # number of overall hits -system.cpu0.dcache.overall_hits::total 43260122 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 418073 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 418073 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 337261 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 337261 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133156 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 133156 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22252 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22252 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19918 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19918 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 755334 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 755334 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 888490 # number of overall misses -system.cpu0.dcache.overall_misses::total 888490 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5661692500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5661692500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6946372000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6946372000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344716000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 344716000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 507189500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 507189500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1629000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1629000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 12608064500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 12608064500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 12608064500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 12608064500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 24858317 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 24858317 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 18830641 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 18830641 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 459654 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 459654 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396454 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396454 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391491 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391491 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 43688958 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 43688958 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 44148612 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 44148612 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016818 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.016818 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017910 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017910 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.289687 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.289687 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056128 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056128 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050877 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050877 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017289 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.017289 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020125 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.020125 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13542.353847 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13542.353847 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20596.428286 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20596.428286 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15491.461442 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15491.461442 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25463.876895 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25463.876895 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 90957934 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90957934 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 24496228 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 24496228 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 18570022 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18570022 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 327271 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 327271 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374846 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374846 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 372508 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 372508 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 43066250 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 43066250 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 43393521 # number of overall hits +system.cpu0.dcache.overall_hits::total 43393521 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 423502 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 423502 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 340254 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 340254 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133712 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 133712 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22535 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22535 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19849 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19849 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 763756 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 763756 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 897468 # number of overall misses +system.cpu0.dcache.overall_misses::total 897468 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5717292500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5717292500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6989183500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6989183500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344979500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 344979500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 511150000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 511150000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1456500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1456500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 12706476000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 12706476000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 12706476000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 12706476000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24919730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24919730 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18910276 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18910276 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 460983 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 460983 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397381 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 397381 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 392357 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 392357 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 43830006 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 43830006 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 44290989 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 44290989 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016995 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016995 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017993 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017993 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290058 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290058 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056709 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056709 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050589 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050589 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017425 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.017425 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020263 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.020263 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13500.036600 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13500.036600 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20541.076666 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20541.076666 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15308.608831 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15308.608831 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25751.927049 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25751.927049 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16692.038886 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16692.038886 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14190.440523 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14190.440523 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16636.826421 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16636.826421 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14158.138229 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14158.138229 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -698,149 +695,147 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 732170 # number of writebacks -system.cpu0.dcache.writebacks::total 732170 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25278 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25278 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15552 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15552 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25279 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25279 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25279 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25279 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 392795 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 392795 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 337260 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 337260 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106103 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 106103 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6700 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6700 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19918 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19918 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 730055 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 730055 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 836158 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 836158 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31819 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60318 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4839458000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4839458000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6609064500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6609064500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1736821000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1736821000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104360500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104360500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 487321500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 487321500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1579000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1579000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11448522500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11448522500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13185343500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13185343500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629856000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629856000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5400865000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5400865000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12030721000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12030721000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015801 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015801 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017910 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017910 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230832 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230832 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016900 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016900 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050877 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050877 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016710 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016710 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018940 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12320.569254 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12320.569254 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19596.348514 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19596.348514 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16369.197855 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16369.197855 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15576.194030 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15576.194030 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24466.387187 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24466.387187 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 740882 # number of writebacks +system.cpu0.dcache.writebacks::total 740882 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25304 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25304 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15852 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15852 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25304 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25304 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25304 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25304 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 398198 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 398198 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 340254 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 340254 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106613 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 106613 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6683 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6683 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19849 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19849 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 738452 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 738452 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 845065 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 845065 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31860 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60413 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4887280000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4887280000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6648929500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6648929500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1745313500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1745313500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102495000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102495000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 491343000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 491343000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1414500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1414500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11536209500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11536209500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13281523000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13281523000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6641550500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6641550500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5414724500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5414724500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12056275000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12056275000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015979 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015979 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017993 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017993 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231273 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231273 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016818 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016818 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050589 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050589 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016848 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016848 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019080 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019080 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15681.726034 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15681.726034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15768.961727 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15768.961727 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208361.544989 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208361.544989 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189510.684585 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189510.684585 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199454.905667 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199454.905667 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1146899 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.321434 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 120426360 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1147411 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 104.954859 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1154605 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.321447 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 120695042 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1155117 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 104.487287 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321434 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321447 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 244294980 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 244294980 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 120426360 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 120426360 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 120426360 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 120426360 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 120426360 # number of overall hits -system.cpu0.icache.overall_hits::total 120426360 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1147420 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1147420 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1147420 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1147420 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1147420 # number of overall misses -system.cpu0.icache.overall_misses::total 1147420 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12257879000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12257879000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12257879000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12257879000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12257879000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12257879000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 121573780 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 121573780 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 121573780 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 121573780 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 121573780 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 121573780 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009438 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.009438 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009438 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.009438 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009438 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.009438 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10682.992278 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10682.992278 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10682.992278 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10682.992278 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10682.992278 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 244855462 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 244855462 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 120695042 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 120695042 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 120695042 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 120695042 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 120695042 # number of overall hits +system.cpu0.icache.overall_hits::total 120695042 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1155126 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1155126 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1155126 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1155126 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1155126 # number of overall misses +system.cpu0.icache.overall_misses::total 1155126 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12352499000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12352499000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12352499000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12352499000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12352499000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12352499000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 121850168 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 121850168 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 121850168 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 121850168 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 121850168 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 121850168 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009480 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009480 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009480 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10693.637750 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10693.637750 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,331 +844,330 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1146899 # number of writebacks -system.cpu0.icache.writebacks::total 1146899 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1147420 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1147420 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1147420 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1147420 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1147420 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1147420 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1154605 # number of writebacks +system.cpu0.icache.writebacks::total 1154605 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1155126 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1155126 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1155126 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1155126 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1155126 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1155126 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11684169000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11684169000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11684169000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11684169000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11684169000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11684169000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11774936000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11774936000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11774936000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11774936000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11774936000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11774936000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009438 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009438 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009438 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009438 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10182.992278 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10182.992278 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10182.992278 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009480 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009480 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009480 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10193.637750 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1935560 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1935650 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 78 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1946486 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1946511 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 245750 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 273082 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16075.027062 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3061877 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 289178 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 10.588209 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 246425 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 273842 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16083.519419 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3089138 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 289977 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 10.653045 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14584.410184 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.385544 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.137322 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1488.094013 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.890162 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14593.575431 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.644607 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.130850 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1489.168531 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.890721 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000039 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090826 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.981142 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1066 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15022 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 320 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 458 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3316 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7592 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3838 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065063 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.916870 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 62794753 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 62794753 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10867 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4767 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 15634 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 501313 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 501313 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1348863 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1348863 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 238469 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 238469 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1100555 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1100555 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 411293 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 411293 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10867 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4767 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1100555 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 649762 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1765951 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10867 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4767 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1100555 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 649762 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1765951 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 177 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 76 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 253 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55141 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55141 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19907 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19907 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43650 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 43650 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46865 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 46865 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94305 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 94305 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 177 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 76 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 46865 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 137955 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 185073 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 177 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 76 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 46865 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 137955 # number of overall misses -system.cpu0.l2cache.overall_misses::total 185073 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4896500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2045000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 6941500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 165758000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 165758000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 42773000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 42773000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1499992 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1499992 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2791235000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2791235000 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3308401000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3308401000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3237666000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3237666000 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4896500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2045000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3308401000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6028901000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 9344243500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4896500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2045000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3308401000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6028901000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 9344243500 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11044 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4843 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 15887 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 501313 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 501313 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 1348863 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 1348863 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55141 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55141 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19907 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19907 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 11 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 282119 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 282119 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1147420 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1147420 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 505598 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 505598 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11044 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4843 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1147420 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 787717 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1951024 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11044 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4843 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1147420 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 787717 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1951024 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015693 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.015925 # miss rate for ReadReq accesses +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090892 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.981660 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1031 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 325 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3285 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7655 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3857 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062927 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 63340451 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 63340451 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11537 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4979 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 16516 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 507696 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 507696 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1358751 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1358751 # number of WritebackClean hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 241135 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 241135 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1108628 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1108628 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 416937 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 416937 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 11537 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4979 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1108628 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 658072 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1783216 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11537 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4979 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1108628 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 658072 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1783216 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 155 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 252 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55316 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 55316 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19844 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19844 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43803 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 43803 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46498 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 46498 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94557 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 94557 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 155 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 46498 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 138360 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 185110 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 155 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 46498 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 138360 # number of overall misses +system.cpu0.l2cache.overall_misses::total 185110 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4266000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2540500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 6806500 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 172322000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 172322000 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 43306000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 43306000 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1349997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1349997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2802544000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2802544000 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3338173500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3338173500 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3246573500 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3246573500 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4266000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2540500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3338173500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 6049117500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 9394097500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4266000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2540500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3338173500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 6049117500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 9394097500 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11692 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5076 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 16768 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507696 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackDirty_accesses::total 507696 # number of WritebackDirty accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::writebacks 1358751 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.WritebackClean_accesses::total 1358751 # number of WritebackClean accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55316 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55316 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19844 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19844 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 284938 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 284938 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1155126 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1155126 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 511494 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 511494 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11692 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5076 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1155126 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 796432 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1968326 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11692 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5076 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1155126 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 796432 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1968326 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.019110 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154722 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154722 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040844 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040844 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.186522 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.186522 # miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.015693 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040844 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.175133 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.094859 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.016027 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.015693 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040844 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.175133 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.094859 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26907.894737 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27436.758893 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3006.075334 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3006.075334 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2148.641181 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2148.641181 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 136362.909091 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 136362.909091 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63945.819015 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63945.819015 # average ReadExReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 70594.281447 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 70594.281447 # average ReadCleanReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34331.859392 # average ReadSharedReq miss latency -system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34331.859392 # average ReadSharedReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26907.894737 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 70594.281447 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43701.939038 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 50489.501440 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27663.841808 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26907.894737 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 70594.281447 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43701.939038 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 50489.501440 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.153728 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.153728 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040254 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040254 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184864 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184864 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.019110 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040254 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.173725 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.094044 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.019110 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040254 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.173725 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.094044 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26190.721649 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27009.920635 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3115.228867 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3115.228867 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2182.322112 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2182.322112 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 269999.400000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 269999.400000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63980.640595 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63980.640595 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71791.765237 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71791.765237 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34334.565394 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34334.565394 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 50748.730485 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 50748.730485 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 231742 # number of writebacks -system.cpu0.l2cache.writebacks::total 231742 # number of writebacks -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1776 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1776 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 53 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 53 # number of ReadSharedReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1829 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1829 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1829 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1829 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 177 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 76 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 253 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 265136 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 265136 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55141 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55141 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19907 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19907 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 11 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41874 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 41874 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46865 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46865 # number of ReadCleanReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94252 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94252 # number of ReadSharedReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 177 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 76 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46865 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136126 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 183244 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 177 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 76 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46865 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136126 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 265136 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 448380 # number of overall MSHR misses +system.cpu0.l2cache.writebacks::writebacks 232272 # number of writebacks +system.cpu0.l2cache.writebacks::total 232272 # number of writebacks +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1851 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1851 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 57 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 57 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1908 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1908 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1908 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1908 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 155 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 97 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 264558 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55316 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55316 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19844 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19844 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41952 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 41952 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46498 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46498 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94500 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94500 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 155 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 97 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46498 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136452 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 183202 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 155 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 97 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46498 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136452 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 447760 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40841 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28499 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40882 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69340 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1589000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5423500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20369501795 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20369501795 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1428543500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1428543500 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 338252500 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 338252500 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1199992 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1199992 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2362760500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2362760500 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3027211000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3027211000 # number of ReadCleanReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2665459000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2665459000 # number of ReadSharedReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1589000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3027211000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5028219500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 8060854000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3834500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1589000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3027211000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5028219500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20369501795 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 28430355795 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69435 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1958500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5294500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20402670222 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1434169000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1434169000 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 342730000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 342730000 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2366849000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2366849000 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3059185500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3059185500 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2673492000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2673492000 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1958500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3059185500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5040341000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 8104821000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1958500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3059185500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5040341000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 28507491222 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6374890500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7561102000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5187001000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5187001000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6386259500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7572471000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5200454500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5200454500 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11561891500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12748103000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015925 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11586714000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12772925500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015029 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1182,117 +1176,117 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.148427 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.148427 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040844 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.186417 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.186417 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093922 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.016027 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015693 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040844 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.172811 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147232 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147232 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040254 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184753 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184753 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093075 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229818 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21436.758893 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 76826.616510 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25907.101794 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25907.101794 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16991.636108 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16991.636108 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109090.181818 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109090.181818 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56425.478817 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56425.478817 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64594.281447 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28280.131987 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28280.131987 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43989.729541 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21663.841808 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20907.894737 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 64594.281447 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36937.980254 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 76826.616510 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63406.833032 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227483 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200348.549609 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185135.084841 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182006.421278 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182006.421278 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191682.275606 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183849.192385 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 3903345 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1968246 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 28892 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 321222 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317069 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4153 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 63874 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1765403 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28499 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 733576 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1348863 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 190188 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 312390 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42077 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112758 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 301102 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 297729 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1147420 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 574776 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3316 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3438002 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2673168 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11871 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27031 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6150072 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 145478520 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 101119646 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 19372 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 44176 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 246661714 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 988213 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2981714 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.123543 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.333265 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 3935499 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1983981 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 29039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 320941 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317478 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 63971 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1779248 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28553 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28553 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 740475 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1358751 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 190136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 311790 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85728 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41989 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112642 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 304006 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 300714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1155126 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 580591 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3461069 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2699694 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12104 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27735 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6200602 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146461624 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 102248167 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46768 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 248776863 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 987005 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2997932 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.122336 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.331180 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2617497 87.78% 87.78% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 360064 12.08% 99.86% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4153 0.14% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2634639 87.88% 87.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 359830 12.00% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 3463 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2981714 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 3884130992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2997932 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 3917122496 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115184885 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115533329 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1730152000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1741711000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1265237983 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1278424980 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 15993487 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 16050485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1323,57 +1317,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 2355 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 2355 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 481 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1874 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 2355 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 2355 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 2355 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1709 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11678.466940 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11002.721261 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5695.537695 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1565 91.57% 91.57% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 135 7.90% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 2352 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 2352 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 487 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1865 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 2352 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 2352 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 2352 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1706 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5645.878722 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1558 91.32% 91.32% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 139 8.15% 99.47% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1709 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1706 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1228 71.85% 71.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 481 28.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1709 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2355 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1219 71.45% 71.45% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 487 28.55% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1706 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2352 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2355 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1709 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2352 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1706 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1709 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 4064 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 4058 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3323284 # DTB read hits -system.cpu1.dtb.read_misses 1962 # DTB read misses -system.cpu1.dtb.write_hits 2909831 # DTB write hits -system.cpu1.dtb.write_misses 393 # DTB write misses +system.cpu1.dtb.read_hits 3283088 # DTB read hits +system.cpu1.dtb.read_misses 1969 # DTB read misses +system.cpu1.dtb.write_hits 2849660 # DTB write hits +system.cpu1.dtb.write_misses 383 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1652 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1653 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 231 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 218 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3325246 # DTB read accesses -system.cpu1.dtb.write_accesses 2910224 # DTB write accesses +system.cpu1.dtb.read_accesses 3285057 # DTB read accesses +system.cpu1.dtb.write_accesses 2850043 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6233115 # DTB hits -system.cpu1.dtb.misses 2355 # DTB misses -system.cpu1.dtb.accesses 6235470 # DTB accesses +system.cpu1.dtb.hits 6132748 # DTB hits +system.cpu1.dtb.misses 2352 # DTB misses +system.cpu1.dtb.accesses 6135100 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1411,20 +1405,21 @@ system.cpu1.itb.walker.walkWaitTime::samples 1376 system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11895.604396 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11259.508648 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5169.477869 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 116 14.16% 14.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 583 71.18% 85.35% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 72 8.79% 94.14% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 8 0.98% 95.12% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.12% 95.24% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 22 2.69% 97.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.85% 98.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.61% 99.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 3 0.37% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5216.232861 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 112 13.68% 13.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 592 72.28% 85.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 66 8.06% 94.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 94.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 24 2.93% 98.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 5 0.61% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.73% 99.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution @@ -1439,7 +1434,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 13877832 # ITB inst hits +system.cpu1.itb.inst_hits 13713445 # ITB inst hits system.cpu1.itb.inst_misses 1376 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1456,171 +1451,171 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 13879208 # ITB inst accesses -system.cpu1.itb.hits 13877832 # DTB hits +system.cpu1.itb.inst_accesses 13714821 # ITB inst accesses +system.cpu1.itb.hits 13713445 # DTB hits system.cpu1.itb.misses 1376 # DTB misses -system.cpu1.itb.accesses 13879208 # DTB accesses -system.cpu1.numCycles 5742698802 # number of cpu cycles simulated +system.cpu1.itb.accesses 13714821 # DTB accesses +system.cpu1.numCycles 5742759797 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2717 # number of quiesce instructions executed -system.cpu1.committedInsts 13679150 # Number of instructions committed -system.cpu1.committedOps 16668513 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 15113644 # Number of integer alu accesses +system.cpu1.kern.inst.quiesce 2753 # number of quiesce instructions executed +system.cpu1.committedInsts 13517417 # Number of instructions committed +system.cpu1.committedOps 16437338 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14911378 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 913162 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1492467 # number of instructions that are conditional controls -system.cpu1.num_int_insts 15113644 # number of integer instructions +system.cpu1.num_func_calls 901174 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1468136 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14911378 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 27463830 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10666857 # number of times the integer registers were written +system.cpu1.num_int_register_reads 27063131 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10536793 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 61159895 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 5174219 # number of times the CC registers were written -system.cpu1.num_mem_refs 6447631 # number of memory refs -system.cpu1.num_load_insts 3428751 # Number of load instructions -system.cpu1.num_store_insts 3018880 # Number of store instructions -system.cpu1.num_idle_cycles 5696160545.959164 # Number of idle cycles -system.cpu1.num_busy_cycles 46538256.040836 # Number of busy cycles -system.cpu1.not_idle_fraction 0.008104 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.991896 # Percentage of idle cycles -system.cpu1.Branches 2456488 # Number of branches fetched +system.cpu1.num_cc_register_reads 60344215 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 5099594 # number of times the CC registers were written +system.cpu1.num_mem_refs 6349896 # number of memory refs +system.cpu1.num_load_insts 3389045 # Number of load instructions +system.cpu1.num_store_insts 2960851 # Number of store instructions +system.cpu1.num_idle_cycles 5696813538.222876 # Number of idle cycles +system.cpu1.num_busy_cycles 45946258.777124 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008001 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991999 # Percentage of idle cycles +system.cpu1.Branches 2418797 # Number of branches fetched system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 10511910 61.88% 61.88% # Class of executed instruction -system.cpu1.op_class::IntMult 24272 0.14% 62.03% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.03% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3188 0.02% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.04% # Class of executed instruction -system.cpu1.op_class::MemRead 3428751 20.18% 82.23% # Class of executed instruction -system.cpu1.op_class::MemWrite 3018880 17.77% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 10377527 61.94% 61.94% # Class of executed instruction +system.cpu1.op_class::IntMult 24492 0.15% 62.08% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.08% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3134 0.02% 62.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.10% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.10% # Class of executed instruction +system.cpu1.op_class::MemRead 3389045 20.23% 82.33% # Class of executed instruction +system.cpu1.op_class::MemWrite 2960851 17.67% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 16987025 # Class of executed instruction -system.cpu1.dcache.tags.replacements 147592 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.392474 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6004450 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 147942 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 40.586514 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106294932000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.392474 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914829 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.914829 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.683594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12646180 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12646180 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3055213 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3055213 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2743263 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2743263 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41902 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 41902 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69872 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 69872 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61606 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61606 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5798476 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5798476 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5840378 # number of overall hits -system.cpu1.dcache.overall_hits::total 5840378 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 112221 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 112221 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 79294 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 79294 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24421 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24421 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16601 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16601 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23085 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23085 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 191515 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 191515 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 215936 # number of overall misses -system.cpu1.dcache.overall_misses::total 215936 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1751790500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1751790500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2724343500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2724343500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320772500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320772500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 629240500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 629240500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3762500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3762500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4476134000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4476134000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4476134000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4476134000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3167434 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3167434 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2822557 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2822557 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66323 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 66323 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86473 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 86473 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84691 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 84691 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5989991 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5989991 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6056314 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6056314 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035430 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035430 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028093 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028093 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.368213 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.368213 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.191979 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.191979 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.272579 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.272579 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031973 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.031973 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035655 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035655 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15610.184368 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15610.184368 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34357.498676 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34357.498676 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19322.480573 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19322.480573 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27257.548191 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27257.548191 # average StoreCondReq miss latency +system.cpu1.op_class::total 16755073 # Class of executed instruction +system.cpu1.dcache.tags.replacements 144073 # number of replacements +system.cpu1.dcache.tags.tagsinuse 473.219627 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5912733 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 144418 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 40.941801 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106295131000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.219627 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924257 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.924257 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.673828 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12441829 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12441829 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3018165 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3018165 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2685196 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2685196 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41245 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 41245 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69563 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 69563 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61182 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61182 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5703361 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5703361 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5744606 # number of overall hits +system.cpu1.dcache.overall_hits::total 5744606 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 110713 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 110713 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 77621 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 77621 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23905 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 23905 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16417 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16417 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23076 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23076 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 188334 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 188334 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 212239 # number of overall misses +system.cpu1.dcache.overall_misses::total 212239 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1730591500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1730591500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2713528000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2713528000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316809000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 316809000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 632764000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 632764000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3307000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3307000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4444119500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4444119500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4444119500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4444119500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3128878 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3128878 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2762817 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2762817 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65150 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 65150 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85980 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 85980 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84258 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 84258 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5891695 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5891695 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5956845 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5956845 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035384 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035384 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028095 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028095 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366922 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366922 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190940 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190940 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273873 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273873 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031966 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031966 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035629 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035629 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15631.330557 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15631.330557 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34958.683861 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 34958.683861 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19297.618322 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19297.618322 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27420.870168 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27420.870168 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23372.237162 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 23372.237162 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20728.984514 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20728.984514 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1629,102 +1624,102 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 147592 # number of writebacks -system.cpu1.dcache.writebacks::total 147592 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 221 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11676 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11676 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 221 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 221 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 112000 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 112000 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79294 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 79294 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23950 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23950 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4925 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23085 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23085 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 191294 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 191294 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 215244 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 215244 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5504 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1626671000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1626671000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2645049500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2645049500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 437326000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 437326000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90573500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90573500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 606189500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 606189500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3728500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3728500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4271720500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4271720500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4709046500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4709046500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 439448500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 439448500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 303112500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 303112500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 742561000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 742561000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035360 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035360 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028093 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028093 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361112 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361112 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056954 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056954 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.272579 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.272579 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035540 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035540 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14523.848214 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14523.848214 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33357.498676 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33357.498676 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18259.958246 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18259.958246 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18390.558376 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18390.558376 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26259.021009 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26259.021009 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 144073 # number of writebacks +system.cpu1.dcache.writebacks::total 144073 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11530 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11530 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 168 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 168 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 168 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110545 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 110545 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77621 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 77621 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23508 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23508 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4887 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4887 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23076 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23076 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 188166 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 188166 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 211674 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 211674 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3107 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5537 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1611627000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1611627000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2635907000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2635907000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 421753500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 421753500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88480500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88480500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 609718000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 609718000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3277000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3277000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4247534000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4247534000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4669287500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4669287500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 430617000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 430617000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 292641500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 292641500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 723258500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 723258500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035331 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035331 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028095 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028095 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360829 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360829 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056839 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273873 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273873 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031937 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031937 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035535 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035535 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22330.655954 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22330.655954 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21877.713200 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21877.713200 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142631.775398 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142631.775398 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125098.018985 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125098.018985 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134912.972384 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134912.972384 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 463636 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.311121 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13413679 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 464148 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 28.899573 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 106195496500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311121 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 461792 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.311266 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13251136 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 462304 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 28.663252 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 106195905000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311266 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -1732,44 +1727,44 @@ system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 28219802 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 28219802 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13413679 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13413679 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13413679 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13413679 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13413679 # number of overall hits -system.cpu1.icache.overall_hits::total 13413679 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 464148 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 464148 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 464148 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 464148 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 464148 # number of overall misses -system.cpu1.icache.overall_misses::total 464148 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4215419500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4215419500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4215419500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4215419500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4215419500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4215419500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 13877827 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 13877827 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 13877827 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 13877827 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 13877827 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 13877827 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033445 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.033445 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033445 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.033445 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033445 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.033445 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9082.058955 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9082.058955 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9082.058955 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9082.058955 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9082.058955 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 27889184 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 27889184 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13251136 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13251136 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13251136 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13251136 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13251136 # number of overall hits +system.cpu1.icache.overall_hits::total 13251136 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 462304 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 462304 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 462304 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 462304 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 462304 # number of overall misses +system.cpu1.icache.overall_misses::total 462304 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4149723500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4149723500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4149723500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4149723500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4149723500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4149723500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13713440 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13713440 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13713440 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13713440 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13713440 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13713440 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033712 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033712 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033712 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033712 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033712 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033712 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8976.179094 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8976.179094 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8976.179094 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8976.179094 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1778,451 +1773,442 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 463636 # number of writebacks -system.cpu1.icache.writebacks::total 463636 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 464148 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 464148 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 464148 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 464148 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 464148 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 464148 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 461792 # number of writebacks +system.cpu1.icache.writebacks::total 461792 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 462304 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 462304 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 462304 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 462304 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 462304 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 462304 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3983345500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3983345500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3983345500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3983345500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3983345500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3983345500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3918571500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3918571500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3918571500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3918571500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3918571500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3918571500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033445 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.033445 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033445 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.033445 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8582.058955 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8582.058955 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8582.058955 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033712 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.033712 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.033712 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8476.179094 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 118070 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 118078 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.num_hwpf_issued 106104 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 106112 # number of prefetch candidates identified system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 50218 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 30957 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14956.632857 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1041724 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 46098 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 22.598030 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 50448 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 30131 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14949.290291 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1034569 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 45193 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 22.892240 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14500.509333 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.321768 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.084166 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 452.717591 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.885041 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000081 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000127 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027632 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.912880 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 931 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14173 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 891 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14514.476865 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.312401 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.041451 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 430.459574 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.885893 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000141 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026273 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.912432 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 971 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14059 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 54 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 913 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 396 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1648 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12129 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056824 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002258 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.865051 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21133576 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21133576 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2455 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1470 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 3925 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 91545 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 91545 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 509576 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 509576 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18096 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 18096 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 455478 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 455478 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 77072 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 77072 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2455 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1470 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 455478 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 95168 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 554571 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2455 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1470 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 455478 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 95168 # number of overall hits -system.cpu1.l2cache.overall_hits::total 554571 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 345 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 297 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 642 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28981 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28981 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23084 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23084 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32217 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32217 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8670 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 8670 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63803 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 63803 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 345 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 297 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 8670 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 96020 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 105332 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 345 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 297 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 8670 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 96020 # number of overall misses -system.cpu1.l2cache.overall_misses::total 105332 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7035000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5940500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 12975500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 66105500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 66105500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 54747500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 54747500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3677500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3677500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1649546500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1649546500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 528187000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 528187000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1437865000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1437865000 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7035000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5940500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 528187000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3087411500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3628574000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7035000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5940500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 528187000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3087411500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3628574000 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2800 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1767 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 4567 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 91545 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 91545 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 509576 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 509576 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28981 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28981 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23084 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23084 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50313 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 50313 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 464148 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 464148 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 140875 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 140875 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2800 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1767 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 464148 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 191188 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 659903 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2800 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1767 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 464148 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 191188 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 659903 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.168081 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.140574 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1365 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12304 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059265 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858093 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 20957142 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 20957142 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2443 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1453 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 3896 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 89055 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 89055 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 506752 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 506752 # number of WritebackClean hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16650 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 16650 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 453968 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 453968 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 75407 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 75407 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2443 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1453 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 453968 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 92057 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 549921 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2443 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1453 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 453968 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 92057 # number of overall hits +system.cpu1.l2cache.overall_hits::total 549921 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 301 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 650 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28928 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28928 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23076 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 23076 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32043 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32043 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8336 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 8336 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63533 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 63533 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 301 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 8336 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 95576 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 104562 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 301 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 8336 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 95576 # number of overall misses +system.cpu1.l2cache.overall_misses::total 104562 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7078500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6021500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 13100000 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 62132500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 62132500 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 59033500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 59033500 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3231500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3231500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1646554500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1646554500 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 475139500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 475139500 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1418811000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1418811000 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7078500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6021500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 475139500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3065365500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3553605000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7078500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6021500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 475139500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3065365500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3553605000 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2792 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1754 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 4546 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::writebacks 89055 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackDirty_accesses::total 89055 # number of WritebackDirty accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::writebacks 506752 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.WritebackClean_accesses::total 506752 # number of WritebackClean accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28928 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28928 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23076 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23076 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 48693 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 48693 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 462304 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 462304 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 138940 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 138940 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2792 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1754 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 462304 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 187633 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 654483 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2792 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1754 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 462304 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 187633 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 654483 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.171608 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.142983 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.640332 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.640332 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018679 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018679 # miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.452905 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.452905 # miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.168081 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018679 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.502228 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.159617 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.123214 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.168081 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018679 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.502228 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.159617 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20001.683502 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20211.059190 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2280.994445 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2280.994445 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2371.664356 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2371.664356 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3677500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3677500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51201.120526 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51201.120526 # average ReadExReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 60921.222607 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 60921.222607 # average ReadCleanReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22536.009279 # average ReadSharedReq miss latency -system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22536.009279 # average ReadSharedReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20001.683502 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 60921.222607 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32153.837742 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 34448.923404 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20391.304348 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20001.683502 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 60921.222607 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32153.837742 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 34448.923404 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.658062 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.658062 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018031 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018031 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.457269 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.457269 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.171608 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018031 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.509377 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.159763 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.171608 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018031 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.509377 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.159763 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20004.983389 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20153.846154 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2147.832550 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2147.832550 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2558.220662 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2558.220662 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51385.778485 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51385.778485 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.500480 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.500480 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22331.874774 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22331.874774 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 33985.625753 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 33985.625753 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 25761 # number of writebacks -system.cpu1.l2cache.writebacks::total 25761 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 70 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 70 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 70 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 70 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 345 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 297 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 642 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 20837 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 20837 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28981 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28981 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23084 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23084 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 32147 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 32147 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8670 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8670 # number of ReadCleanReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63803 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63803 # number of ReadSharedReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 345 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 297 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8670 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95950 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 105262 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 345 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 297 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8670 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95950 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 20837 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 126099 # number of overall MSHR misses +system.cpu1.l2cache.writebacks::writebacks 25259 # number of writebacks +system.cpu1.l2cache.writebacks::total 25259 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 80 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 80 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 80 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 80 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 349 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 301 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 650 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 18771 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28928 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28928 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23076 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23076 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31963 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 31963 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8336 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8336 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63533 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63533 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 349 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 301 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8336 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95496 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 104482 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 349 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 301 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8336 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95496 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 123253 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3258 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2423 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3284 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5504 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5681 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4158500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9123500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 915724625 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 582445000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 582445000 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 432971000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 432971000 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3473500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3473500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1449025500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1449025500 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 476167000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 476167000 # number of ReadCleanReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1055047000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1055047000 # number of ReadSharedReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4158500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 476167000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2504072500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2989363000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4965000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4158500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 476167000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2504072500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 915724625 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3905087625 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5714 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4215500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9200000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 917123117 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 588451500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 588451500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 436537000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 436537000 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1446140000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1446140000 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 425123500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 425123500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1037613000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1037613000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4215500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 425123500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483753000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2918076500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4215500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 425123500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483753000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3835199617 # number of overall MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 414452000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 436671000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 284931500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 284931500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 405408000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 427627000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 274409000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 274409000 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 699383500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 721602500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.140574 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 679817000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 702036000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.142983 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.638940 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.638940 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018679 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.452905 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452905 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159511 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.123214 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.168081 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018679 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.501862 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.656419 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.656419 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018031 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457269 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457269 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159641 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191087 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14211.059190 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43947.047320 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20097.477658 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20097.477658 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18756.324727 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18756.324727 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3473500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3473500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45074.983669 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45074.983669 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 54921.222607 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16536.009279 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16536.009279 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28399.260892 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14391.304348 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14001.683502 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 54921.222607 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26097.681084 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43947.047320 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30968.426593 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.188321 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134518.662772 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134030.386740 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117594.510937 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117594.510937 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127068.223110 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127020.330928 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1323663 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 668360 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10107 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 169443 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 166760 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2683 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 10105 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 652363 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2423 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2423 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 118404 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 509576 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 86260 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 25020 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 70278 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40907 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84739 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57602 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55059 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 464148 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 215012 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 32 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1383984 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 718041 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4385 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7029 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2113439 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58847556 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24276952 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7068 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 83142776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 355785 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 998697 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.187513 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.397146 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1312846 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 662941 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 166384 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164278 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 10119 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 648543 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2430 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2430 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 115438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 506752 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 85166 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 22864 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70245 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84598 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 55915 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 53326 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 462304 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 211564 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 31 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1378500 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707096 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4372 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7009 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2096977 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58614596 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 23813135 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 82445915 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 350196 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 987919 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.185835 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.394416 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 814111 81.52% 81.52% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 181903 18.21% 99.73% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2683 0.27% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 806435 81.63% 81.63% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 179378 18.16% 99.79% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2106 0.21% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 998697 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1278018500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 987919 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1267256999 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79432929 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79126203 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 696399000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 693633000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 317143500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 311803500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 4229000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 4217000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31021 # Transaction distribution -system.iobus.trans_dist::ReadResp 31021 # Transaction distribution +system.iobus.trans_dist::ReadReq 31009 # Transaction distribution +system.iobus.trans_dist::ReadResp 31009 # Transaction distribution system.iobus.trans_dist::WriteReq 59425 # Transaction distribution system.iobus.trans_dist::WriteResp 59425 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) @@ -2238,16 +2224,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) @@ -2263,26 +2247,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48741500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48738000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 32500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 93000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 609500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) @@ -2303,60 +2286,54 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6155500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6150500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 165000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 32044000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 186301036 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 119500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186329030 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 37500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.380003 # Cycle average of tags in use +system.iocache.tags.replacements 36433 # number of replacements +system.iocache.tags.tagsinuse 1.018273 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 290757542000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.380003 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.898750 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.898750 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 290654223000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.018273 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.063642 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.063642 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses -system.iocache.demand_misses::total 255 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 255 # number of overall misses -system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32882376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32882376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4738851654 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4738851654 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32882376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32882376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32882376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32882376 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31405376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31405376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4738596660 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4738596660 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31405376 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31405376 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31405376 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31405376 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2365,40 +2342,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128950.494118 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128950.494118 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130820.772250 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130820.772250 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128950.494118 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128950.494118 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128950.494118 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129240.230453 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129240.230453 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129240.230453 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 816 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 99 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.262626 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.329114 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36206 # number of writebacks -system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20132376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20132376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927651654 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2927651654 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20132376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20132376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20132376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20132376 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19255376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19255376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927396660 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2927396660 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19255376 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19255376 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19255376 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19255376 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2407,304 +2384,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78950.494118 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78950.494118 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80820.772250 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80820.772250 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78950.494118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78950.494118 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 123906 # number of replacements -system.l2c.tags.tagsinuse 62994.829806 # Cycle average of tags in use -system.l2c.tags.total_refs 421817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 187980 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.243946 # Average number of references to valid blocks. +system.l2c.tags.replacements 123618 # number of replacements +system.l2c.tags.tagsinuse 63093.840837 # Cycle average of tags in use +system.l2c.tags.total_refs 421259 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 187589 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.245649 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13459.681359 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.946988 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.042686 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7381.464495 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2783.395152 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35774.545550 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954481 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1451.828957 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 405.858901 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1734.111238 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205378 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.112632 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.545876 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13244.114990 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.878668 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.996497 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7731.277102 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2849.874177 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36272.088123 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954483 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1120.568935 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 367.321258 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1502.766604 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.202089 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.117970 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.553468 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.022153 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.006193 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026460 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.961225 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31889 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32181 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 315 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26438 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29385 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.486588 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.491043 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5837673 # Number of tag accesses -system.l2c.tags.data_accesses 5837673 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 257503 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 257503 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32214 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1943 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 34157 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2130 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 884 # number of SCUpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.017099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.005605 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022930 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.962736 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32107 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 31859 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4716 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2381 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29068 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.489914 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.486130 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5836461 # Number of tag accesses +system.l2c.tags.data_accesses 5836461 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 257531 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 257531 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 32441 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1723 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 34164 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2115 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 899 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1324 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5386 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 98 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 71 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 29368 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 46989 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47574 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 22 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 20 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 6299 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 4989 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3377 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 138807 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 98 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 29368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 51051 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 47574 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 22 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6299 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6313 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3377 # number of demand (read+write) hits -system.l2c.demand_hits::total 144193 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 98 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits -system.l2c.overall_hits::cpu0.inst 29368 # number of overall hits -system.l2c.overall_hits::cpu0.data 51051 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 47574 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 22 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6299 # number of overall hits -system.l2c.overall_hits::cpu1.data 6313 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3377 # number of overall hits -system.l2c.overall_hits::total 144193 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9379 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2248 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11627 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 589 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1277 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1866 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11187 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7836 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19023 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses +system.l2c.ReadExReq_hits::cpu0.data 4177 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5519 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 92 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 28642 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 47295 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47544 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 6315 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 4707 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3005 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 137714 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 92 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 28642 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 51472 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47544 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 15 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6315 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6049 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3005 # number of demand (read+write) hits +system.l2c.demand_hits::total 143233 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 92 # number of overall hits +system.l2c.overall_hits::cpu0.inst 28642 # number of overall hits +system.l2c.overall_hits::cpu0.data 51472 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47544 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 15 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6315 # number of overall hits +system.l2c.overall_hits::cpu1.data 6049 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 3005 # number of overall hits +system.l2c.overall_hits::total 143233 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 9610 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11910 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1322 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1977 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11124 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7851 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 18975 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 17497 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 8847 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134641 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17856 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8887 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 2371 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 788 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5392 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 169546 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu1.inst 2021 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 752 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 169545 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17497 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20034 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 134641 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17856 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8624 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5392 # number of demand (read+write) misses -system.l2c.demand_misses::total 188569 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses +system.l2c.demand_misses::cpu1.inst 2021 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8603 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) misses +system.l2c.demand_misses::total 188520 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17497 # number of overall misses -system.l2c.overall_misses::cpu0.data 20034 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 134641 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17856 # number of overall misses +system.l2c.overall_misses::cpu0.data 20011 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134682 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses -system.l2c.overall_misses::cpu1.data 8624 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5392 # number of overall misses -system.l2c.overall_misses::total 188569 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 29891000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 5943500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 35834500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4589000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1770500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 6359500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1626887000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1026108000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2652995000 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 948500 # number of ReadSharedReq miss cycles +system.l2c.overall_misses::cpu1.inst 2021 # number of overall misses +system.l2c.overall_misses::cpu1.data 8603 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5338 # number of overall misses +system.l2c.overall_misses::total 188520 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 34729000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5015500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 39744500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3979500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2518000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 6497500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1612676500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1029832500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 2642509000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 823500 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2300069500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 1205085500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2350559500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 1210448500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of ReadSharedReq miss cycles system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.inst 317997500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 116823500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 24316117308 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 948500 # number of demand (read+write) miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 268405000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 104648000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 24352402389 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 823500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2300069500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 2831972500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 2350559500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 2823125000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 317997500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1142931500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 26969112308 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 948500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 268405000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1134480500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 26994911389 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 823500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2300069500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 2831972500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19535280293 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 2350559500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 2823125000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 317997500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1142931500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 839508015 # number of overall miss cycles -system.l2c.overall_miss_latency::total 26969112308 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 257503 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 257503 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 41593 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4191 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45784 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2719 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 2161 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4880 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9160 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24409 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 105 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 73 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.inst 46865 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 55836 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182215 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 23 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 20 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.inst 8670 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 5777 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8769 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 308353 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 105 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 46865 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 71085 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182215 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8670 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 14937 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8769 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 332762 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 105 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 46865 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 71085 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182215 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8670 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 14937 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8769 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 332762 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.225495 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.536387 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.253953 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.216624 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590930 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.382377 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.733622 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.855459 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.779344 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027397 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.373349 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158446 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.273472 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.136403 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.549844 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.027397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.373349 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.281832 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.273472 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.577358 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.566678 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.066667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.027397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.373349 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.281832 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.738913 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.043478 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.273472 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.577358 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.614893 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.566678 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3187.013541 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2643.905694 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3082.007397 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 7791.171477 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1386.452623 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3408.092176 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 145426.566550 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 130947.932619 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 139462.492772 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 135500 # average ReadSharedReq miss latency +system.l2c.overall_miss_latency::cpu1.inst 268405000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1134480500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of overall miss cycles +system.l2c.overall_miss_latency::total 26994911389 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 257531 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 257531 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 42051 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4023 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 46074 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2770 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2221 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4991 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15301 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 9193 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 24494 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 87 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 94 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 46498 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 56182 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182226 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 8336 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 5459 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8343 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 307259 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 46498 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 71483 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182226 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 16 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8336 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 14652 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8343 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 331753 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 46498 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 71483 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182226 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 16 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8336 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 14652 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8343 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 331753 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.228532 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.571713 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.258497 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.236462 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.595227 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.396113 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.727011 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.854019 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.774680 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.021277 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.384017 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158182 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.242442 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.137754 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.551798 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.021277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.384017 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.279941 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.242442 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.587155 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.568254 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.021277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.384017 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.279941 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.242442 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.587155 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.568254 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3613.839750 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2180.652174 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3337.069689 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6075.572519 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1904.689864 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3286.545271 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144972.716649 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131172.143676 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 139262.661397 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137250 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131455.078013 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136214.027354 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131639.756944 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136204.399685 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average ReadSharedReq miss latency system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134119.569802 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 148253.172589 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 143418.997251 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 135500 # average overall miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132808.015834 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139159.574468 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 143633.857613 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 131455.078013 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 141358.315863 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 134119.569802 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 132529.162801 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 143019.861738 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 135500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 143193.886001 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 131455.078013 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 141358.315863 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145091.616172 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 134119.569802 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 132529.162801 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 155695.106639 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 143019.861738 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 143193.886001 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2713,271 +2690,274 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96871 # number of writebacks -system.l2c.writebacks::total 96871 # number of writebacks +system.l2c.writebacks::writebacks 97095 # number of writebacks +system.l2c.writebacks::total 97095 # number of writebacks system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 17 # number of ReadSharedReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 2791 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 2791 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 9379 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2248 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11627 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 589 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1277 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1866 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11187 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7836 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19023 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadSharedReq MSHR misses +system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 2818 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 2818 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 9610 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2300 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11910 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1322 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1977 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11124 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 7851 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 18975 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17492 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8847 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17851 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8886 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2361 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 788 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 169531 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2010 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 752 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 169528 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17492 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20034 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17851 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20010 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2361 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 8624 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 188554 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2010 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 8603 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 188503 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17492 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20034 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134641 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17851 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20010 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2361 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 8624 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5392 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 188554 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2010 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 8603 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 188503 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31819 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 44096 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28499 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2423 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 30922 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3104 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 44163 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 30983 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60318 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5501 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 75018 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 706950000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 168753500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 875703500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 45541000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 97962500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 143503500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1515017000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 947748000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2462765000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 878500 # number of ReadSharedReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5534 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 75146 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 725072500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172861000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 897933500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 50674000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 101405500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 152079500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1501436500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 951322500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2452759000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 763500 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2124790500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1116615500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2171508000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1121559000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of ReadSharedReq MSHR miss cycles system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 122500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 293429500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 108943500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 22619490308 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 878500 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 247283000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 97128000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 22655529389 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 763500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2124790500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2631632500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2171508000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2622995500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 293429500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1056691500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 25082255308 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 878500 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 247283000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1048450500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25108288389 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 763500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2124790500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2631632500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18188870293 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2171508000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2622995500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 293429500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1056691500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 785588015 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 25082255308 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 247283000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1048450500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25108288389 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5802133000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5812758500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 358998500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7203979000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4702508000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 243698500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4946206500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 349483000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7205089000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4715021500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 233050000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4948071500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10504641000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10527780000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 602697000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12150185500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 582533000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 12153160500 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.225495 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.536387 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.253953 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.216624 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590930 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.382377 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.733622 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.855459 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.779344 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158446 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.136403 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.549795 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.566633 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.066667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027397 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.373242 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.281832 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.738913 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.043478 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.272318 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.577358 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.614893 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.566633 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75375.839642 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75068.282918 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75316.375677 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77319.185059 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76712.999217 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76904.340836 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135426.566550 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 120947.932619 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 129462.492772 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.228532 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.571713 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.258497 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.236462 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.595227 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396113 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727011 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854019 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774680 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158165 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.137754 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.551743 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.568203 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.568203 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75449.791883 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75156.956522 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75393.240974 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77364.885496 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76706.127080 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76924.380374 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134972.716649 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121172.143676 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 129262.661397 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126214.027354 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126216.407833 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 138253.172589 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133423.918387 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129159.574468 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133638.864312 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 125500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121472.130117 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131358.315863 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135091.616172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124281.872088 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122529.162801 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 145695.106639 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 133024.254633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182348.062478 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116633.690708 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163370.351052 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165006.070388 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100577.177053 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159957.522153 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174154.332040 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109561.352481 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 161963.602069 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 44096 # Transaction distribution -system.membus.trans_dist::ReadResp 213882 # Transaction distribution -system.membus.trans_dist::WriteReq 30922 # Transaction distribution -system.membus.trans_dist::WriteResp 30922 # Transaction distribution -system.membus.trans_dist::WritebackDirty 133077 # Transaction distribution -system.membus.trans_dist::CleanEvict 14603 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73616 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39905 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13581 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 39514 # Transaction distribution -system.membus.trans_dist::ReadExResp 18935 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 169786 # Transaction distribution +system.membus.trans_dist::ReadReq 44163 # Transaction distribution +system.membus.trans_dist::ReadResp 213934 # Transaction distribution +system.membus.trans_dist::WriteReq 30983 # Transaction distribution +system.membus.trans_dist::WriteResp 30983 # Transaction distribution +system.membus.trans_dist::WritebackDirty 133285 # Transaction distribution +system.membus.trans_dist::CleanEvict 14406 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73490 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39839 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13966 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.membus.trans_dist::ReadExReq 39499 # Transaction distribution +system.membus.trans_dist::ReadExResp 18896 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 169771 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13766 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664049 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 785783 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108937 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108937 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 894720 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14022 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 786162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 895071 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27532 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18296972 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18487386 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20805530 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 121102 # Total snoops (count) -system.membus.snoop_fanout::samples 582015 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18307596 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18498522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20815642 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120564 # Total snoops (count) +system.membus.snoop_fanout::samples 581920 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 582015 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 581920 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 582015 # Request fanout histogram -system.membus.reqLayer0.occupancy 88274000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 581920 # Request fanout histogram +system.membus.reqLayer0.occupancy 88268000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11368000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11611500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 966740692 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 967762037 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1134075509 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1134685490 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64085297 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64105002 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3020,52 +3000,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 961177 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 518872 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 139554 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20662 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19793 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 869 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 44099 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 468456 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30922 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30922 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 390602 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 84323 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 107685 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42919 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 150604 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 84 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 84 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50476 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50476 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 424372 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 959770 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 518663 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 138023 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 20272 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 19432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 44166 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 467162 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30983 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30983 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 390842 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 84262 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107575 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 150428 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50605 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50605 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 423011 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1224412 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249093 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1473505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34296330 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3743120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38039450 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 438983 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 897187 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.337621 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.474943 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1226424 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 245800 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1472224 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34332563 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3643847 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 37976410 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 437847 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 895583 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.335708 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474219 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 595147 66.33% 66.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 301171 33.57% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 869 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 595769 66.52% 66.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 298974 33.38% 99.91% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 840 0.09% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 897187 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 864296758 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 895583 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 863469481 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 360622 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342622 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 647366860 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 647119226 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 201908331 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 200312901 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal index 263610058..03b467a01 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal @@ -158,8 +158,8 @@ ata1.00: 1048320 sectors, multi 0: LBA ata1.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: Attached scsi generic sg0 type 0
+sd 0:0:0:0: [sda] Write Protect is off
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sda: sda1
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 3ed11f6b1..535394f06 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -415,10 +415,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -445,7 +444,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -572,12 +571,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -670,16 +666,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -695,7 +690,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -858,13 +853,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -874,9 +869,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -918,7 +912,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -999,14 +993,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1023,7 +1016,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -1038,7 +1031,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1161,17 +1154,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1223,7 +1218,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1238,7 +1233,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index f435b44af..adf07f76b 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 15:54:29 -gem5 executing on e104799-lin, pid 1785 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 12:27:38 +gem5 executing on e104799-lin, pid 4347 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 @@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2909603958500 because m5_exit instruction encountered +Exiting @ tick 2909596171500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index ae445de86..e37d38e0e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909604 # Number of seconds simulated -sim_ticks 2909603958500 # Number of ticks simulated -final_tick 2909603958500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909596 # Number of seconds simulated +sim_ticks 2909596171500 # Number of ticks simulated +final_tick 2909596171500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 366627 # Simulator instruction rate (inst/s) -host_op_rate 442036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9485837068 # Simulator tick rate (ticks/s) -host_mem_usage 580620 # Number of bytes of host memory used -host_seconds 306.73 # Real time elapsed on the host -sim_insts 112455934 # Number of instructions simulated -sim_ops 135586369 # Number of ops (including micro ops) simulated +host_inst_rate 612420 # Simulator instruction rate (inst/s) +host_op_rate 738388 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15845377688 # Simulator tick rate (ticks/s) +host_mem_usage 579872 # Number of bytes of host memory used +host_seconds 183.62 # Real time elapsed on the host +sim_insts 112455206 # Number of instructions simulated +sim_ops 135585876 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1186596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8901732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1186404 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8901796 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1186596 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7512000 # Number of bytes written to this memory +system.physmem.bytes_read::total 10089736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1186404 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1186404 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7511872 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7529524 # Number of bytes written to this memory +system.physmem.bytes_written::total 7529396 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 139609 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26991 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 139610 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117375 # Number of write requests responded to by this memory +system.physmem.num_reads::total 166625 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117373 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121756 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121754 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 407820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3059431 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 407756 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3059461 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 407820 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407820 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581795 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 407756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407756 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581758 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6023 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587817 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581795 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587780 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581758 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 407820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3065454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 407756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3065484 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166627 # Number of read requests accepted -system.physmem.writeReqs 121756 # Number of write requests accepted -system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121756 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10656896 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 7542080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7529524 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6055525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166625 # Number of read requests accepted +system.physmem.writeReqs 121754 # Number of write requests accepted +system.physmem.readBursts 166625 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121754 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10656448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 7541952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10089736 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7529396 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 47113 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10077 # Per bank write bursts @@ -69,15 +69,15 @@ system.physmem.perBankRdBursts::2 10695 # Pe system.physmem.perBankRdBursts::3 10661 # Per bank write bursts system.physmem.perBankRdBursts::4 18797 # Per bank write bursts system.physmem.perBankRdBursts::5 9659 # Per bank write bursts -system.physmem.perBankRdBursts::6 9665 # Per bank write bursts -system.physmem.perBankRdBursts::7 10488 # Per bank write bursts +system.physmem.perBankRdBursts::6 9663 # Per bank write bursts +system.physmem.perBankRdBursts::7 10485 # Per bank write bursts system.physmem.perBankRdBursts::8 9276 # Per bank write bursts system.physmem.perBankRdBursts::9 9973 # Per bank write bursts -system.physmem.perBankRdBursts::10 9230 # Per bank write bursts +system.physmem.perBankRdBursts::10 9232 # Per bank write bursts system.physmem.perBankRdBursts::11 8679 # Per bank write bursts -system.physmem.perBankRdBursts::12 9820 # Per bank write bursts +system.physmem.perBankRdBursts::12 9817 # Per bank write bursts system.physmem.perBankRdBursts::13 10379 # Per bank write bursts -system.physmem.perBankRdBursts::14 9723 # Per bank write bursts +system.physmem.perBankRdBursts::14 9722 # Per bank write bursts system.physmem.perBankRdBursts::15 9413 # Per bank write bursts system.physmem.perBankWrBursts::0 7393 # Per bank write bursts system.physmem.perBankWrBursts::1 7263 # Per bank write bursts @@ -86,35 +86,35 @@ system.physmem.perBankWrBursts::3 8171 # Pe system.physmem.perBankWrBursts::4 7489 # Per bank write bursts system.physmem.perBankWrBursts::5 7265 # Per bank write bursts system.physmem.perBankWrBursts::6 7108 # Per bank write bursts -system.physmem.perBankWrBursts::7 7662 # Per bank write bursts +system.physmem.perBankWrBursts::7 7659 # Per bank write bursts system.physmem.perBankWrBursts::8 7080 # Per bank write bursts system.physmem.perBankWrBursts::9 7523 # Per bank write bursts -system.physmem.perBankWrBursts::10 6693 # Per bank write bursts +system.physmem.perBankWrBursts::10 6695 # Per bank write bursts system.physmem.perBankWrBursts::11 6470 # Per bank write bursts system.physmem.perBankWrBursts::12 7534 # Per bank write bursts system.physmem.perBankWrBursts::13 7859 # Per bank write bursts -system.physmem.perBankWrBursts::14 7265 # Per bank write bursts +system.physmem.perBankWrBursts::14 7264 # Per bank write bursts system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2909603601500 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 2909595814500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157055 # Read request sizes (log2) +system.physmem.readPktSize::6 157053 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117375 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see +system.physmem.writePktSize::6 117373 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165628 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,116 +159,117 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5950 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58748 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 309.779261 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.856223 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.388013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21447 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14643 24.93% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6082 10.35% 71.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3222 5.48% 77.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2599 4.42% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1493 2.54% 84.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1038 1.77% 86.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1067 1.82% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7157 12.18% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58748 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.896737 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 590.107660 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5761 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58778 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.611351 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.749688 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.493771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21450 36.49% 36.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14701 25.01% 61.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6086 10.35% 71.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3214 5.47% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2550 4.34% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1476 2.51% 84.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1054 1.79% 85.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1089 1.85% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7158 12.18% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58778 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5758 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.915596 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 590.311059 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5757 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5762 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5762 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.452100 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.700018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.100411 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4964 86.15% 86.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 94 1.63% 87.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 35 0.61% 88.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 168 2.92% 91.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 22 0.38% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 152 2.64% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.89% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.12% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 11 0.19% 95.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.26% 95.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.07% 95.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 174 3.02% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.12% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.05% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 18 0.31% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.07% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5758 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5758 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.465960 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.711564 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.116644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4961 86.16% 86.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 87 1.51% 87.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 33 0.57% 88.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 172 2.99% 91.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 23 0.40% 91.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 160 2.78% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 50 0.87% 95.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.10% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 7 0.12% 95.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 22 0.38% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.10% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.83% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.17% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.35% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.02% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.02% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.57% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::124-127 1 0.02% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.26% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 16 0.28% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5762 # Writes before turning the bus around for reads -system.physmem.totQLat 1626690000 # Total ticks spent queuing -system.physmem.totMemAccLat 4748827500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832570000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9769.09 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5758 # Writes before turning the bus around for reads +system.physmem.totQLat 1616458000 # Total ticks spent queuing +system.physmem.totMemAccLat 4738464250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9708.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28519.09 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28458.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -278,40 +279,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.01 # Average write queue length when enqueuing -system.physmem.readRowHits 136108 # Number of row buffer hits during reads -system.physmem.writeRowHits 89502 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing +system.physmem.readRowHits 136072 # Number of row buffer hits during reads +system.physmem.writeRowHits 89499 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.72 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.93 # Row buffer hit rate for writes -system.physmem.avgGap 10089372.82 # Average gap between requests -system.physmem.pageHitRate 79.33 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230496840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125767125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702163800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90194010705 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666640821500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948326896850 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.620811 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772423900000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97157840000 # Time in different power states +system.physmem.avgGap 10089485.76 # Average gap between requests +system.physmem.pageHitRate 79.32 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230958000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 126018750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702124800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392882400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90366604425 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666484751750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948343566605 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.628332 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772164122000 # Time in different power states +system.physmem_0.memoryStateTime::REF 97157580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40015565000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40267816750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213638040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116568375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 596637600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370733760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190040735040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88104913965 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668473362500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947916589280 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.479792 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2775503002250 # Time in different power states -system.physmem_1.memoryStateTime::REF 97157840000 # Time in different power states +system.physmem_1.actEnergy 213403680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116440500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 596622000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 370740240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190040226480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88072375230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668497233500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1947907041630 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.478302 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2775541834250 # Time in different power states +system.physmem_1.memoryStateTime::REF 97157580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36942968250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36896609250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -369,13 +370,12 @@ system.cpu.dtb.walker.walkWaitTime::samples 9546 # system.cpu.dtb.walker.walkWaitTime::0 9546 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::total 9546 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkCompletionTime::samples 7382 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 13188.702249 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10926.693941 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 9189.684239 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 13161.947982 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10924.263330 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8540.848722 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::0-32767 7377 99.93% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::total 7382 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 1638910500 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 1638910500 100.00% 100.00% # Table walker pending requests distribution @@ -392,9 +392,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7382 system.cpu.dtb.walker.walkRequestOrigin::total 16928 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24520223 # DTB read hits +system.cpu.dtb.read_hits 24520178 # DTB read hits system.cpu.dtb.read_misses 8124 # DTB read misses -system.cpu.dtb.write_hits 19606444 # DTB write hits +system.cpu.dtb.write_hits 19606457 # DTB write hits system.cpu.dtb.write_misses 1422 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -405,12 +405,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1650 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24528347 # DTB read accesses -system.cpu.dtb.write_accesses 19607866 # DTB write accesses +system.cpu.dtb.read_accesses 24528302 # DTB read accesses +system.cpu.dtb.write_accesses 19607879 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44126667 # DTB hits +system.cpu.dtb.hits 44126635 # DTB hits system.cpu.dtb.misses 9546 # DTB misses -system.cpu.dtb.accesses 44136213 # DTB accesses +system.cpu.dtb.accesses 44136181 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,7 +468,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3108 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7871 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115553087 # ITB inst hits +system.cpu.itb.inst_hits 115552414 # ITB inst hits system.cpu.itb.inst_misses 4763 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -485,40 +485,40 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115557850 # ITB inst accesses -system.cpu.itb.hits 115553087 # DTB hits +system.cpu.itb.inst_accesses 115557177 # ITB inst accesses +system.cpu.itb.hits 115552414 # DTB hits system.cpu.itb.misses 4763 # DTB misses -system.cpu.itb.accesses 115557850 # DTB accesses -system.cpu.numCycles 5819207917 # number of cpu cycles simulated +system.cpu.itb.accesses 115557177 # DTB accesses +system.cpu.numCycles 5819192343 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu.committedInsts 112455934 # Number of instructions committed -system.cpu.committedOps 135586369 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119891885 # Number of integer alu accesses +system.cpu.committedInsts 112455206 # Number of instructions committed +system.cpu.committedOps 135585876 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119891340 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses -system.cpu.num_func_calls 9891908 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15230427 # number of instructions that are conditional controls -system.cpu.num_int_insts 119891885 # number of integer instructions +system.cpu.num_func_calls 9892021 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15230391 # number of instructions that are conditional controls +system.cpu.num_int_insts 119891340 # number of integer instructions system.cpu.num_fp_insts 11161 # number of float instructions -system.cpu.num_int_register_reads 218060317 # number of times the integer registers were read -system.cpu.num_int_register_writes 82644878 # number of times the integer registers were written +system.cpu.num_int_register_reads 218059811 # number of times the integer registers were read +system.cpu.num_int_register_writes 82644916 # number of times the integer registers were written system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 489736143 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51894204 # number of times the CC registers were written -system.cpu.num_mem_refs 45406948 # number of memory refs -system.cpu.num_load_insts 24842511 # Number of load instructions +system.cpu.num_cc_register_reads 489735153 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51893214 # number of times the CC registers were written +system.cpu.num_mem_refs 45407055 # number of memory refs +system.cpu.num_load_insts 24842618 # Number of load instructions system.cpu.num_store_insts 20564437 # Number of store instructions -system.cpu.num_idle_cycles 5379072532.100152 # Number of idle cycles -system.cpu.num_busy_cycles 440135384.899849 # Number of busy cycles -system.cpu.not_idle_fraction 0.075635 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.924365 # Percentage of idle cycles -system.cpu.Branches 25916368 # Number of branches fetched +system.cpu.num_idle_cycles 5379072985.844151 # Number of idle cycles +system.cpu.num_busy_cycles 440119357.155849 # Number of busy cycles +system.cpu.not_idle_fraction 0.075632 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.924368 # Percentage of idle cycles +system.cpu.Branches 25916470 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93174225 67.17% 67.18% # Class of executed instruction -system.cpu.op_class::IntMult 114427 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93173703 67.17% 67.18% # Class of executed instruction +system.cpu.op_class::IntMult 114388 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -542,20 +542,20 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8455 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8453 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24842511 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemRead 24842618 17.91% 85.17% # Class of executed instruction system.cpu.op_class::MemWrite 20564437 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138706392 # Class of executed instruction -system.cpu.dcache.tags.replacements 819093 # number of replacements +system.cpu.op_class::total 138705936 # Class of executed instruction +system.cpu.dcache.tags.replacements 819217 # number of replacements system.cpu.dcache.tags.tagsinuse 511.702336 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43235572 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819605 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.751718 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 43235406 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819729 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.743536 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1736147500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.702336 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999419 # Average percentage of cache occupancy @@ -566,188 +566,188 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177109325 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177109325 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23112645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23112645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18823942 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18823942 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392782 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392782 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443235 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443235 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460203 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460203 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41936587 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41936587 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42329369 # number of overall hits -system.cpu.dcache.overall_hits::total 42329369 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 399856 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 399856 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 298641 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 298641 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118367 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118367 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22751 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22751 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177109321 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177109321 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23112521 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23112521 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18823879 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18823879 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392783 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392783 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443242 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443242 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460216 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460216 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41936400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41936400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42329183 # number of overall hits +system.cpu.dcache.overall_hits::total 42329183 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 399911 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 399911 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298704 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298704 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118377 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118377 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22757 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22757 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 698497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 698497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 816864 # number of overall misses -system.cpu.dcache.overall_misses::total 816864 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6484051000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6484051000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19116145000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19116145000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294006500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 294006500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 698615 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 698615 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 816992 # number of overall misses +system.cpu.dcache.overall_misses::total 816992 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6486417000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6486417000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19109109000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19109109000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 294489000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 294489000 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25600196000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25600196000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25600196000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25600196000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23512501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23512501 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 25595526000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25595526000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25595526000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25595526000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23512432 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23512432 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19122583 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19122583 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511149 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511149 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465986 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 465986 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460205 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460205 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42635084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42635084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43146233 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43146233 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231570 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.231570 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048823 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048823 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511160 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511160 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465999 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465999 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460218 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42635015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42635015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43146175 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43146175 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017008 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017008 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015620 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015620 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231585 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231585 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048835 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048835 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.018932 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16215.965247 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16215.965247 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64010.450675 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64010.450675 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12922.794602 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12922.794602 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.016386 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016386 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018935 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018935 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16219.651372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16219.651372 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63973.395067 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63973.395067 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12940.589709 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12940.589709 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36650.402221 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36650.402221 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31339.606103 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31339.606103 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36637.527107 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36637.527107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31328.979966 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31328.979966 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 20 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 683726 # number of writebacks -system.cpu.dcache.writebacks::total 683726 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 924 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 924 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14242 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14242 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 924 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 924 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 924 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 924 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398932 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 398932 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298641 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298641 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116310 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 116310 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8509 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8509 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683842 # number of writebacks +system.cpu.dcache.writebacks::total 683842 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 930 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 930 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14247 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14247 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 930 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 930 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 930 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 930 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 398981 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 398981 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298704 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298704 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116321 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116321 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8510 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8510 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 697573 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 697573 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 813883 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 813883 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 697685 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 697685 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 814006 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 814006 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6055510500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6055510500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18817504000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 18817504000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1617135000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1617135000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115280000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115280000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6058107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6058107000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18810405000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 18810405000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1614233500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1614233500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 115353500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 115353500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24873014500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24873014500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26490149500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26490149500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6279074500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6279074500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089978000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089978000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369052500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369052500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016967 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227546 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227546 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018260 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018260 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24868512000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24868512000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26482745500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26482745500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6278172000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6278172000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5089977500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5089977500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11368149500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11368149500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016969 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016969 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015620 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227563 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227563 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018262 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018262 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016361 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018863 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15179.304994 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15179.304994 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63010.450675 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63010.450675 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13903.662626 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13903.662626 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13548.007992 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13548.007992 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016364 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018866 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018866 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15183.948609 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15183.948609 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62973.395067 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62973.395067 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13877.403908 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13877.403908 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13555.052879 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13555.052879 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35656.504050 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35656.504050 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32547.859459 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32547.859459 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201653.108742 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201653.108742 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.022581 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.022581 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193591.576277 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193591.576277 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35644.326594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35644.326594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32533.845574 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32533.845574 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201624.124864 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201624.124864 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184493.004458 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184493.004458 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193576.200044 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193576.200044 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1695571 # number of replacements -system.cpu.icache.tags.tagsinuse 510.436867 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113856998 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1696083 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.129379 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 1695565 # number of replacements +system.cpu.icache.tags.tagsinuse 510.436866 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113856331 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1696077 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.129223 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 29070355500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.436867 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.436866 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -756,44 +756,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 195 system.cpu.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117249176 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117249176 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113856998 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113856998 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113856998 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113856998 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113856998 # number of overall hits -system.cpu.icache.overall_hits::total 113856998 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1696089 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1696089 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1696089 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1696089 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1696089 # number of overall misses -system.cpu.icache.overall_misses::total 1696089 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 24269708000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 24269708000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 24269708000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 24269708000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 24269708000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 24269708000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115553087 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115553087 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115553087 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115553087 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115553087 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115553087 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 117248497 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117248497 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113856331 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113856331 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113856331 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113856331 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113856331 # number of overall hits +system.cpu.icache.overall_hits::total 113856331 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1696083 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1696083 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1696083 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1696083 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1696083 # number of overall misses +system.cpu.icache.overall_misses::total 1696083 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 24267960000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 24267960000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 24267960000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 24267960000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 24267960000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 24267960000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115552414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115552414 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115552414 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115552414 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115552414 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115552414 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014678 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.014678 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.014678 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.014678 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.014678 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.014678 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14309.218443 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14309.218443 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14309.218443 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14309.218443 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14309.218443 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14308.238453 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14308.238453 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14308.238453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14308.238453 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14308.238453 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,24 +802,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1695571 # number of writebacks -system.cpu.icache.writebacks::total 1695571 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696089 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1696089 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1696089 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1696089 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1696089 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1696089 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 1695565 # number of writebacks +system.cpu.icache.writebacks::total 1695565 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1696083 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1696083 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1696083 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1696083 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1696083 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1696083 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22573619000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22573619000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22573619000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22573619000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22573619000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22573619000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22571877000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22571877000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22571877000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22571877000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22571877000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22571877000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1142541000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1142541000 # number of overall MSHR uncacheable cycles @@ -830,71 +830,71 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014678 system.cpu.icache.demand_mshr_miss_rate::total 0.014678 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014678 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.014678 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13309.218443 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13309.218443 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13309.218443 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13309.218443 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13308.238453 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13308.238453 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13308.238453 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13308.238453 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126639.436932 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126639.436932 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87564 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64865.227437 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4544047 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152799 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 29.738722 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87562 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64865.195753 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4544223 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 152797 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.740263 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50197.653066 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799333 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012653 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.739092 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.023293 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.765955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50196.671494 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.799338 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012652 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9701.731977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4962.980293 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.765940 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.148037 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989765 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65230 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6852 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56198 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56201 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995331 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40507837 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40507837 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7811 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 40509810 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40509810 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7810 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4039 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11850 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 683726 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 683726 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 1664804 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1664804 # number of WritebackClean hits +system.cpu.l2cache.ReadReq_hits::total 11849 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 683842 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 683842 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 1664795 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 1664795 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 166964 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 166964 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678077 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1678077 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511579 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 511579 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7811 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 167026 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 167026 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1678074 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1678074 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 511640 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 511640 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7810 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 4039 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1678077 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 678543 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2368470 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7811 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 1678074 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 678666 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2368589 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7810 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 4039 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1678077 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 678543 # number of overall hits -system.cpu.l2cache.overall_hits::total 2368470 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1678074 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 678666 # number of overall hits +system.cpu.l2cache.overall_hits::total 2368589 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses @@ -902,72 +902,72 @@ system.cpu.l2cache.UpgradeReq_misses::cpu.data 2740 system.cpu.l2cache.UpgradeReq_misses::total 2740 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 128914 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 128914 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17979 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 128915 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 128915 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 17976 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 17976 # number of ReadCleanReq misses system.cpu.l2cache.ReadSharedReq_misses::cpu.data 12172 # number of ReadSharedReq misses system.cpu.l2cache.ReadSharedReq_misses::total 12172 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 17979 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141086 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 159074 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 17976 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141087 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 159072 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 17979 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141086 # number of overall misses -system.cpu.l2cache.overall_misses::total 159074 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1147500 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 17976 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141087 # number of overall misses +system.cpu.l2cache.overall_misses::total 159072 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 957500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 266000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1413500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1223500 # number of ReadReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1857500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16391193500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 16391193500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2350840500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 2350840500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1613502500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 1613502500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1147500 # number of demand (read+write) miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16383348000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16383348000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 2349142000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 2349142000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1612524000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1612524000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 957500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 266000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 2350840500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18004696000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20356950000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1147500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 2349142000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 17995872000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20346237500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 957500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 266000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 2350840500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18004696000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20356950000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7818 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 2349142000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 17995872000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20346237500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7817 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4041 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 11859 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 683726 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 683726 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 1664804 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 1664804 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 11858 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 683842 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 683842 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 1664795 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 1664795 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2763 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 295878 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 295878 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696056 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 1696056 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523751 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 523751 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7818 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295941 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295941 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1696050 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1696050 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 523812 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 523812 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7817 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 4041 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1696056 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819629 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2527544 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7818 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1696050 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819753 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2527661 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7817 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 4041 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1696056 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819629 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2527544 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1696050 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819753 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2527661 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000895 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000495 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.000759 # miss rate for ReadReq accesses @@ -975,45 +975,45 @@ system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991676 system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435700 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.435700 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010600 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010600 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023240 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023240 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.435610 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.435610 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.023237 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.023237 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000895 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000495 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010600 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172134 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062936 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010599 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172109 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062932 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000895 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000495 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010600 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172134 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062936 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 163928.571429 # average ReadReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010599 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172109 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062932 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136785.714286 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 133000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 157055.555556 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 135944.444444 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 677.919708 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 677.919708 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127148.281025 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127148.281025 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130754.797263 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130754.797263 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132558.535984 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132558.535984 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 163928.571429 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127086.436799 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127086.436799 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 130682.131731 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 130682.131731 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 132478.146566 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 132478.146566 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130754.797263 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127615.043307 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 127971.572979 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 163928.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 127905.838237 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136785.714286 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 133000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130754.797263 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127615.043307 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 127971.572979 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 130682.131731 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 127551.595824 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 127905.838237 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1022,8 +1022,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 81185 # number of writebacks -system.cpu.l2cache.writebacks::total 81185 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 81183 # number of writebacks +system.cpu.l2cache.writebacks::total 81183 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 9 # number of ReadReq MSHR misses @@ -1031,22 +1031,22 @@ system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2740 system.cpu.l2cache.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128914 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 128914 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17979 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 128915 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 128915 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 17976 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 17976 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 12172 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 12172 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 17979 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 141086 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 159074 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 17976 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141087 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 159072 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 17979 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 141086 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 159074 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 17976 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141087 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 159072 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable @@ -1055,37 +1055,37 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1077500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 887500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 246000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1323500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1133500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 194003500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 194003500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 139000 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15102053500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15102053500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2171050500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2171050500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1491782500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1491782500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1077500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 15094198000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 15094198000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2169382000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2169382000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1490804000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1490804000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 887500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 246000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2171050500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16593836000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18766210000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1077500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2169382000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16585002000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18755517500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 887500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 246000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2171050500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16593836000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18766210000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2169382000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16585002000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18755517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1029766000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5889729000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6919495000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5888826500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6918592500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4772574000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4772574000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1029766000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10662303500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11692069500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10661400500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11691166500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000759 # mshr miss rate for ReadReq accesses @@ -1093,104 +1093,104 @@ system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991676 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435700 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435700 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010600 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023240 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023240 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.435610 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.435610 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.023237 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.023237 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062932 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000895 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000495 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172134 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062936 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010599 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172109 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062932 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 123000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 147055.555556 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.014599 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.014599 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 125944.444444 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70804.197080 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70804.197080 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117148.281025 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117148.281025 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120754.797263 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120754.797263 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122558.535984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122558.535984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117086.436799 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117086.436799 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120682.131731 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120682.131731 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122478.146566 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122478.146566 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 153928.571429 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126785.714286 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 123000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120754.797263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117615.043307 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117971.572979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120682.131731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 117551.595824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 117905.838237 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189149.238872 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172298.182271 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.310559 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.310559 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189120.254994 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172275.709661 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172988.292435 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172988.292435 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 114139.436932 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181557.094692 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172579.218881 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181541.718460 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 172565.890271 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 5052300 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536604 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38129 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 5052537 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2536723 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 38125 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 67213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2287266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2287321 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 801101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1664804 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 134612 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801217 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1664795 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 134627 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 523979 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1696083 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 524040 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074993 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574186 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5074972 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2574565 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 13257 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25655 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7688091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215131128 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96411485 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 25654 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7688448 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 215130168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96426845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 311590049 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 175874 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2773719 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.020869 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.142946 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 31268 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 311604445 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 175875 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2773837 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.020867 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.142939 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2715834 97.91% 97.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 57885 2.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2715955 97.91% 97.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 57882 2.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2773719 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4957066000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2773837 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4957294000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2553155500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2553146500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1275758999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1275944500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9216000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1202,6 +1202,7 @@ system.iobus.trans_dist::WriteReq 59014 # Tr system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) @@ -1217,16 +1218,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) @@ -1242,10 +1241,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) @@ -1254,14 +1250,16 @@ system.iobus.reqLayer0.occupancy 46338000 # La system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 97000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 338000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 94500 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 644500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 94500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 644500 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) @@ -1282,29 +1280,23 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6288500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6287500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 174000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36469500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 36469500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 186221548 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 127000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186222546 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084136 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084130 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 313818895000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084136 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 313812613000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.084130 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.067758 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.067758 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -1320,14 +1312,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28180377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28180377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4715427169 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4715427169 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28180377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28180377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28180377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28180377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28228376 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28228376 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4717653172 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4717653172 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28228376 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28228376 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28228376 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28228376 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1344,19 +1336,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123598.144737 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123598.144737 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130174.115752 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130174.115752 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123598.144737 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123598.144737 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123598.144737 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 753 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123808.666667 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123808.666667 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130235.566807 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130235.566807 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123808.666667 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123808.666667 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123808.666667 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 910 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 81 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.296296 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.234568 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1370,14 +1362,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16780377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16780377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2904227169 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2904227169 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16780377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16780377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16780377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16780377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16828376 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16828376 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2906453172 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2906453172 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16828376 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16828376 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16828376 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16828376 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1386,68 +1378,68 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73598.144737 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73598.144737 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80174.115752 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80174.115752 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73598.144737 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73598.144737 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73808.666667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73808.666667 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80235.566807 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80235.566807 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73808.666667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73808.666667 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution -system.membus.trans_dist::ReadResp 70548 # Transaction distribution +system.membus.trans_dist::ReadResp 70545 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution -system.membus.trans_dist::WritebackDirty 117375 # Transaction distribution +system.membus.trans_dist::WritebackDirty 117373 # Transaction distribution system.membus.trans_dist::CleanEvict 6392 # Transaction distribution system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution -system.membus.trans_dist::ReadExReq 127157 # Transaction distribution -system.membus.trans_dist::ReadExResp 127157 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 30388 # Transaction distribution +system.membus.trans_dist::ReadExReq 127158 # Transaction distribution +system.membus.trans_dist::ReadExResp 127158 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30385 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546415 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546409 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655303 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302268 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465621 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15302012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15465365 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782741 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782485 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 389999 # Request fanout histogram +system.membus.snoop_fanout::samples 389997 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 389999 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389997 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 389999 # Request fanout histogram -system.membus.reqLayer0.occupancy 90471000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389997 # Request fanout histogram +system.membus.reqLayer0.occupancy 90470000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 1726000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823075656 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823068661 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952261248 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952238748 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64129261 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64113741 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini index c18617da5..14ca44c08 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -511,10 +511,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -541,7 +540,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -641,12 +640,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -739,16 +735,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -764,7 +759,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -927,13 +922,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -943,9 +938,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -987,7 +981,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -1068,14 +1062,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1092,7 +1085,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -1107,7 +1100,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1230,17 +1223,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1292,7 +1287,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1307,7 +1302,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout index a9e51249c..65b8c5d0a 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 15:55:07 -gem5 executing on e104799-lin, pid 1838 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 11:36:43 +gem5 executing on e104799-lin, pid 31310 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index bf5be371b..9720a4a26 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.783867 # Nu sim_ticks 2783867052000 # Number of ticks simulated final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 544117 # Simulator instruction rate (inst/s) -host_op_rate 662376 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10609508545 # Simulator tick rate (ticks/s) -host_mem_usage 578316 # Number of bytes of host memory used -host_seconds 262.39 # Real time elapsed on the host +host_inst_rate 949157 # Simulator instruction rate (inst/s) +host_op_rate 1155446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18507193552 # Simulator tick rate (ticks/s) +host_mem_usage 578592 # Number of bytes of host memory used +host_seconds 150.42 # Real time elapsed on the host sim_insts 142772879 # Number of instructions simulated sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -666,6 +666,7 @@ system.iobus.trans_dist::WriteReq 59002 # Tr system.iobus.trans_dist::WriteResp 59002 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) @@ -681,16 +682,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) @@ -706,10 +705,7 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 79996f19b..a24fe1dd0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -503,10 +503,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -533,7 +532,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -697,12 +696,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -795,16 +791,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -820,7 +815,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -983,13 +978,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -999,9 +994,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -1043,7 +1037,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -1124,14 +1118,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1148,7 +1141,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -1163,7 +1156,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -1286,17 +1279,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -1348,7 +1343,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -1363,7 +1358,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr index 48d941748..d2f2052ec 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -63,3 +63,19 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 1355ee684..d795d81a2 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 15:55:08 -gem5 executing on e104799-lin, pid 1845 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 11:29:52 +gem5 executing on e104799-lin, pid 30613 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index acd379650..5b2713b0e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.909654 # Number of seconds simulated -sim_ticks 2909653700500 # Number of ticks simulated -final_tick 2909653700500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.909671 # Number of seconds simulated +sim_ticks 2909670971500 # Number of ticks simulated +final_tick 2909670971500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 367664 # Simulator instruction rate (inst/s) -host_op_rate 443285 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9513271691 # Simulator tick rate (ticks/s) -host_mem_usage 578564 # Number of bytes of host memory used -host_seconds 305.85 # Real time elapsed on the host -sim_insts 112450652 # Number of instructions simulated -sim_ops 135579653 # Number of ops (including micro ops) simulated +host_inst_rate 618646 # Simulator instruction rate (inst/s) +host_op_rate 745891 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16006919548 # Simulator tick rate (ticks/s) +host_mem_usage 578852 # Number of bytes of host memory used +host_seconds 181.78 # Real time elapsed on the host +sim_insts 112454909 # Number of instructions simulated +sim_ops 135585028 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 521248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4656256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 523360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4648320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 665348 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4245540 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 663236 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4253220 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10089864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 521248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 665348 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 10089608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 523360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 663236 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1186596 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 7511936 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 8852 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8672 # Number of bytes written to this memory system.physmem.bytes_written::total 7529460 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13432 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73257 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13465 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73133 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 13562 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66353 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 13529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66473 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166623 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 117374 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2213 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2168 # Number of write requests responded to by this memory system.physmem.num_writes::total 121755 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 179144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1600278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 179869 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1597541 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 228669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1459122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 227942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1461753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3467720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 179144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 228669 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 407813 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2581729 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3467611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 179869 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 227942 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 407811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2581713 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 3042 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2980 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2587751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2581729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2587736 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2581713 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 179144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1603321 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 179869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1600584 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 228669 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1462103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 227942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1464733 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6055471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166627 # Number of read requests accepted +system.physmem.bw_total::total 6055347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166623 # Number of read requests accepted system.physmem.writeReqs 121755 # Number of write requests accepted -system.physmem.readBursts 166627 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 166623 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 121755 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10658432 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 10657728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue system.physmem.bytesWritten 7541440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10089864 # Total read bytes from the system interface side +system.physmem.bytesReadSys 10089608 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 7529460 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3888 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 47114 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 47111 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10080 # Per bank write bursts system.physmem.perBankRdBursts::1 9979 # Per bank write bursts system.physmem.perBankRdBursts::2 10697 # Per bank write bursts -system.physmem.perBankRdBursts::3 10658 # Per bank write bursts +system.physmem.perBankRdBursts::3 10654 # Per bank write bursts system.physmem.perBankRdBursts::4 18793 # Per bank write bursts -system.physmem.perBankRdBursts::5 9660 # Per bank write bursts -system.physmem.perBankRdBursts::6 9676 # Per bank write bursts -system.physmem.perBankRdBursts::7 10492 # Per bank write bursts +system.physmem.perBankRdBursts::5 9662 # Per bank write bursts +system.physmem.perBankRdBursts::6 9670 # Per bank write bursts +system.physmem.perBankRdBursts::7 10489 # Per bank write bursts system.physmem.perBankRdBursts::8 9276 # Per bank write bursts system.physmem.perBankRdBursts::9 9982 # Per bank write bursts system.physmem.perBankRdBursts::10 9231 # Per bank write bursts -system.physmem.perBankRdBursts::11 8678 # Per bank write bursts +system.physmem.perBankRdBursts::11 8676 # Per bank write bursts system.physmem.perBankRdBursts::12 9823 # Per bank write bursts system.physmem.perBankRdBursts::13 10380 # Per bank write bursts -system.physmem.perBankRdBursts::14 9720 # Per bank write bursts +system.physmem.perBankRdBursts::14 9722 # Per bank write bursts system.physmem.perBankRdBursts::15 9413 # Per bank write bursts system.physmem.perBankWrBursts::0 7393 # Per bank write bursts system.physmem.perBankWrBursts::1 7263 # Per bank write bursts system.physmem.perBankWrBursts::2 8284 # Per bank write bursts -system.physmem.perBankWrBursts::3 8168 # Per bank write bursts +system.physmem.perBankWrBursts::3 8167 # Per bank write bursts system.physmem.perBankWrBursts::4 7485 # Per bank write bursts system.physmem.perBankWrBursts::5 7265 # Per bank write bursts system.physmem.perBankWrBursts::6 7108 # Per bank write bursts @@ -107,21 +107,21 @@ system.physmem.perBankWrBursts::7 7667 # Pe system.physmem.perBankWrBursts::8 7080 # Per bank write bursts system.physmem.perBankWrBursts::9 7523 # Per bank write bursts system.physmem.perBankWrBursts::10 6694 # Per bank write bursts -system.physmem.perBankWrBursts::11 6470 # Per bank write bursts +system.physmem.perBankWrBursts::11 6468 # Per bank write bursts system.physmem.perBankWrBursts::12 7527 # Per bank write bursts system.physmem.perBankWrBursts::13 7859 # Per bank write bursts -system.physmem.perBankWrBursts::14 7261 # Per bank write bursts +system.physmem.perBankWrBursts::14 7264 # Per bank write bursts system.physmem.perBankWrBursts::15 6788 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 3 # Number of times write queue was full causing retry -system.physmem.totGap 2909653343500 # Total gap between requests +system.physmem.numWrRetry 4 # Number of times write queue was full causing retry +system.physmem.totGap 2909670614500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157055 # Read request sizes (log2) +system.physmem.readPktSize::6 157051 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) @@ -129,8 +129,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 117374 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 165647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 611 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,137 +161,131 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 202 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 199 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 188 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 181 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 176 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 174 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 172 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 169 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 166 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58556 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 310.810301 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.232220 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.272692 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21388 36.53% 36.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14563 24.87% 61.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6001 10.25% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3238 5.53% 77.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2533 4.33% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1526 2.61% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1009 1.72% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1158 1.98% 87.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7140 12.19% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58556 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5712 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.151786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 545.492775 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5709 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.04% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 58603 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.549016 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.176876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.004841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21372 36.47% 36.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14638 24.98% 61.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6011 10.26% 71.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3214 5.48% 77.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2514 4.29% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1548 2.64% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1052 1.80% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1122 1.91% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7132 12.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 58603 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5730 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.058290 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.635756 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5727 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5712 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5712 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.629377 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.719500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.211627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 18 0.32% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.16% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.14% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 11 0.19% 0.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4765 83.42% 84.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 125 2.19% 86.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 59 1.03% 87.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 204 3.57% 91.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.56% 91.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 148 2.59% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 51 0.89% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.14% 95.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 9 0.16% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.30% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.14% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 167 2.92% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.11% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 19 0.33% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 4 0.07% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.04% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 3 0.05% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.02% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 15 0.26% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.04% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5730 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.564572 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.725438 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.838937 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 17 0.30% 0.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 9 0.16% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 8 0.14% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 11 0.19% 0.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4763 83.12% 83.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 132 2.30% 86.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 73 1.27% 87.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 203 3.54% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 27 0.47% 91.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 153 2.67% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 54 0.94% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.03% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.23% 95.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.40% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 95.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.12% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 171 2.98% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 24 0.42% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 3 0.05% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.19% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5712 # Writes before turning the bus around for reads -system.physmem.totQLat 1608810750 # Total ticks spent queuing -system.physmem.totMemAccLat 4731398250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 832690000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9660.32 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5730 # Writes before turning the bus around for reads +system.physmem.totQLat 1612014000 # Total ticks spent queuing +system.physmem.totMemAccLat 4734395250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 832635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9680.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28410.32 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28430.20 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.59 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.47 # Average system read bandwidth in MiByte/s @@ -301,40 +295,40 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.25 # Average write queue length when enqueuing -system.physmem.readRowHits 136274 # Number of row buffer hits during reads -system.physmem.writeRowHits 89542 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.97 # Row buffer hit rate for writes -system.physmem.avgGap 10089580.29 # Average gap between requests -system.physmem.pageHitRate 79.40 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 230519520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 125779500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 702273000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 392901840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 90285662430 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666593127500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1948374558750 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.624648 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772342347250 # Time in different power states -system.physmem_0.memoryStateTime::REF 97159660000 # Time in different power states +system.physmem.avgWrQLen 12.26 # Average write queue length when enqueuing +system.physmem.readRowHits 136241 # Number of row buffer hits during reads +system.physmem.writeRowHits 89517 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes +system.physmem.avgGap 10089780.13 # Average gap between requests +system.physmem.pageHitRate 79.38 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 230746320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125903250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 702187200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 392895360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 90312406830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1666579011000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1948388462040 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.625842 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2772320056250 # Time in different power states +system.physmem_0.memoryStateTime::REF 97160180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40149801500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 40187145000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 212163840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 115764000 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 212292360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 115834125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 596715600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370668960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 190044294960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 88503009660 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1668156858000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1947999475020 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.495738 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2774969217000 # Time in different power states -system.physmem_1.memoryStateTime::REF 97159660000 # Time in different power states +system.physmem_1.writeEnergy 370675440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 190045312080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 88507788255 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1668162009750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1948010627610 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.495988 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774979616000 # Time in different power states +system.physmem_1.memoryStateTime::REF 97160180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37524675500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 37531027500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -384,58 +378,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 6385 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 6385 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1824 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4559 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 6383 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 6383 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 6383 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 5318 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 13413.689357 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11614.000174 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7416.349168 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 3990 75.03% 75.03% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1324 24.90% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 6370 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6370 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1827 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4542 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6369 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5319 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 13473.303252 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11679.114902 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7408.984019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 3974 74.71% 74.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1341 25.21% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::131072-147455 4 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 5318 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 1993677436 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean -0.003389 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 2000434000 100.34% 100.34% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -6756564 -0.34% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1993677436 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3519 66.20% 66.20% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1797 33.80% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5316 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6385 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 5319 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 2989035968 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.330748 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.470482 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 2000419000 66.93% 66.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 988616968 33.07% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 2989035968 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3517 66.13% 66.13% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1801 33.87% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5318 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6370 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6385 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5316 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6370 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5318 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5316 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 11701 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5318 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 11688 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12043498 # DTB read hits -system.cpu0.dtb.read_misses 5581 # DTB read misses -system.cpu0.dtb.write_hits 9607194 # DTB write hits -system.cpu0.dtb.write_misses 804 # DTB write misses -system.cpu0.dtb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12041748 # DTB read hits +system.cpu0.dtb.read_misses 5569 # DTB read misses +system.cpu0.dtb.write_hits 9609883 # DTB write hits +system.cpu0.dtb.write_misses 801 # DTB write misses +system.cpu0.dtb.flush_tlb 2941 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3980 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3992 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 867 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12049079 # DTB read accesses -system.cpu0.dtb.write_accesses 9607998 # DTB write accesses +system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12047317 # DTB read accesses +system.cpu0.dtb.write_accesses 9610684 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21650692 # DTB hits -system.cpu0.dtb.misses 6385 # DTB misses -system.cpu0.dtb.accesses 21657077 # DTB accesses +system.cpu0.dtb.hits 21651631 # DTB hits +system.cpu0.dtb.misses 6370 # DTB misses +system.cpu0.dtb.accesses 21658001 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,131 +460,131 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3199 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3199 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 683 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2516 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3199 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3199 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3199 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2347 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13274.818918 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11551.422255 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6527.623179 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::4096-6143 600 25.56% 25.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::10240-12287 656 27.95% 53.52% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::12288-14335 193 8.22% 61.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.49% 78.23% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.36% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::22528-24575 500 21.30% 99.66% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-26623 8 0.34% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2347 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3218 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3218 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 687 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2531 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3218 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3218 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3218 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2361 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 13277.424820 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11544.822386 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6544.721859 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::4096-6143 607 25.71% 25.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::10240-12287 660 27.95% 53.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::12288-14335 188 7.96% 61.63% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::14336-16383 387 16.39% 78.02% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-18431 3 0.13% 78.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::22528-24575 510 21.60% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-26623 6 0.25% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2361 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 2000380500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 2000380500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 2000380500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1664 70.90% 70.90% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 683 29.10% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2347 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 1674 70.90% 70.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 687 29.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2361 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3199 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3199 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3218 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3218 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2347 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2347 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 5546 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56739503 # ITB inst hits -system.cpu0.itb.inst_misses 3199 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2361 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2361 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 5579 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56731893 # ITB inst hits +system.cpu0.itb.inst_misses 3218 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2940 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 441 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2941 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 437 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2369 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2380 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56742702 # ITB inst accesses -system.cpu0.itb.hits 56739503 # DTB hits -system.cpu0.itb.misses 3199 # DTB misses -system.cpu0.itb.accesses 56742702 # DTB accesses -system.cpu0.numCycles 2910044532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56735111 # ITB inst accesses +system.cpu0.itb.hits 56731893 # DTB hits +system.cpu0.itb.misses 3218 # DTB misses +system.cpu0.itb.accesses 56735111 # DTB accesses +system.cpu0.numCycles 2910044257 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3033 # number of quiesce instructions executed -system.cpu0.committedInsts 55201459 # Number of instructions committed -system.cpu0.committedOps 66609946 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58847772 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5145 # Number of float alu accesses -system.cpu0.num_func_calls 4820077 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7555989 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58847772 # number of integer instructions -system.cpu0.num_fp_insts 5145 # number of float instructions -system.cpu0.num_int_register_reads 106933475 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40499308 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3730 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 240486031 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 25664833 # number of times the CC registers were written -system.cpu0.num_mem_refs 22274491 # number of memory refs -system.cpu0.num_load_insts 12198391 # Number of load instructions -system.cpu0.num_store_insts 10076100 # Number of store instructions -system.cpu0.num_idle_cycles 2694628360.005429 # Number of idle cycles -system.cpu0.num_busy_cycles 215416171.994570 # Number of busy cycles -system.cpu0.not_idle_fraction 0.074025 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.925975 # Percentage of idle cycles -system.cpu0.Branches 12743161 # Number of branches fetched -system.cpu0.op_class::No_OpClass 131 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 45792912 67.22% 67.22% # Class of executed instruction -system.cpu0.op_class::IntMult 56104 0.08% 67.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3963 0.01% 67.30% # Class of executed instruction +system.cpu0.kern.inst.quiesce 3034 # number of quiesce instructions executed +system.cpu0.committedInsts 55192175 # Number of instructions committed +system.cpu0.committedOps 66601030 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58838667 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5226 # Number of float alu accesses +system.cpu0.num_func_calls 4816070 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7555391 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58838667 # number of integer instructions +system.cpu0.num_fp_insts 5226 # number of float instructions +system.cpu0.num_int_register_reads 106920418 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40489001 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3747 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1482 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 240444662 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 25665883 # number of times the CC registers were written +system.cpu0.num_mem_refs 22275144 # number of memory refs +system.cpu0.num_load_insts 12196401 # Number of load instructions +system.cpu0.num_store_insts 10078743 # Number of store instructions +system.cpu0.num_idle_cycles 2694612539.353109 # Number of idle cycles +system.cpu0.num_busy_cycles 215431717.646891 # Number of busy cycles +system.cpu0.not_idle_fraction 0.074030 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.925970 # Percentage of idle cycles +system.cpu0.Branches 12738975 # Number of branches fetched +system.cpu0.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 45781986 67.21% 67.21% # Class of executed instruction +system.cpu0.op_class::IntMult 56167 0.08% 67.29% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3968 0.01% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12198391 17.91% 85.21% # Class of executed instruction -system.cpu0.op_class::MemWrite 10076100 14.79% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12196401 17.90% 85.20% # Class of executed instruction +system.cpu0.op_class::MemWrite 10078743 14.80% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 68127601 # Class of executed instruction -system.cpu0.dcache.tags.replacements 819018 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.702192 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43232909 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819530 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.753296 # Average number of references to valid blocks. +system.cpu0.op_class::total 68117399 # Class of executed instruction +system.cpu0.dcache.tags.replacements 819062 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.702235 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43234880 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819574 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.752869 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1736913500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309115 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393077 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 43.309006 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 468.393230 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.084588 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914830 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.914831 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999418 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id @@ -597,124 +592,124 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177098246 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177098246 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11355856 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11755360 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23111216 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9224406 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9598440 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18822846 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190279 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202400 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392679 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213881 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229331 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443212 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221919 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238270 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460189 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20580262 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 21353800 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41934062 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20770541 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21556200 # number of overall hits -system.cpu0.dcache.overall_hits::total 42326741 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199428 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 200396 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 399824 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 149476 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 149150 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298626 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58742 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59581 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118323 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10843 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11913 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22756 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 177106290 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177106290 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11353905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11758208 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23112113 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9226963 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9596855 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18823818 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190234 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202489 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392723 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 213697 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 229550 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443247 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 221754 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 238460 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460214 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20580868 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21355063 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41935931 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20771102 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21557552 # number of overall hits +system.cpu0.dcache.overall_hits::total 42328654 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 199783 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 200066 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 399849 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 149794 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 148846 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298640 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58818 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 59499 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118317 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10855 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11895 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22750 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 348904 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 349546 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 698450 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 407646 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 409127 # number of overall misses -system.cpu0.dcache.overall_misses::total 816773 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3300764500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3177768500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6478533000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9862313500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9244759000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19107072500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137644000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 156454000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 294098000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 349577 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 348912 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 698489 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 408395 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 408411 # number of overall misses +system.cpu0.dcache.overall_misses::total 816806 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3309369500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3172445000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6481814500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9848447000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9257158000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19105605000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 137223000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 156952000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 294175000 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 13163078000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 12422527500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 25585605500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 13163078000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 12422527500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 25585605500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11555284 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11955756 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23511040 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9373882 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9747590 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19121472 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 249021 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 261981 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511002 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 224724 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 241244 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 465968 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 221919 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 238272 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460191 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 20929166 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21703346 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42632512 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21178187 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21965327 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43143514 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017259 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016761 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_miss_latency::cpu0.data 13157816500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 12429603000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 25587419500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 13157816500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 12429603000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 25587419500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11553688 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11958274 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23511962 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9376757 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9745701 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19122458 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 249052 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 261988 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511040 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 224552 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 241445 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 465997 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 221754 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 238462 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460216 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 20930445 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21703975 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42634420 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21179497 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21965963 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43145460 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.017292 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.016730 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.017006 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015946 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015301 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015975 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015273 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235892 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227425 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231551 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048250 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049382 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048836 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.236168 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227106 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.231522 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048341 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049266 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048820 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016671 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016106 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016702 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016076 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.016383 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019248 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018626 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.018932 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16551.158814 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15857.444759 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16203.462023 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65979.244160 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 61982.963460 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 63983.285112 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12694.272803 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13133.047931 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12923.976094 # average LoadLockedReq miss latency +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019283 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.018593 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018931 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16564.820330 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15856.992193 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16210.655773 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 65746.605338 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 62192.857047 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 63975.371685 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12641.455550 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13194.787726 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12930.769231 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37726.933483 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35539.034920 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36631.978667 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32290.462804 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30363.499598 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31325.234184 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37639.251152 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 35623.890838 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36632.530362 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32218.358452 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30434.055400 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31326.189450 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 76 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -723,201 +718,201 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 683842 # number of writebacks -system.cpu0.dcache.writebacks::total 683842 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 485 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 439 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 924 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7005 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7232 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14237 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 485 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 439 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 924 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 485 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 439 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 924 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 198943 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199957 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 398900 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 149476 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 149150 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298626 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57623 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58651 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116274 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3838 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4681 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8519 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 683867 # number of writebacks +system.cpu0.dcache.writebacks::total 683867 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 454 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 925 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7013 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7211 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14224 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 471 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 454 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 925 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 471 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 454 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 925 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199312 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199612 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 398924 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 149794 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148846 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298640 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57717 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 58554 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116271 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 3842 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4684 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 348419 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 349107 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 697526 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 406042 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 407758 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 813800 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15006 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16132 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.demand_mshr_misses::cpu0.data 349106 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 348458 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 697564 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 406823 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 407012 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 813835 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 14993 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16145 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13389 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14200 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 13371 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14218 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28395 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30332 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 28364 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30363 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3085102500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2965375000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6050477500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9712837500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9095609000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18808446500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 798019000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 816464500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614483500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52409500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62952500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115362000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3093759000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2959743000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6053502000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9698653000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9108312000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 18806965000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 795616000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 818334500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1613950500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 52173500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 63283500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 115457000 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 162000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 162000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12797940000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12060984000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24858924000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13595959000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12877448500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 26473407500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3049211500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3229832500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6279044000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2494979500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2594954500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089934000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5544191000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5824787000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368978000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017217 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016725 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016966 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015946 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015301 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12792412000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 12068055000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24860467000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13588028000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 12886389500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 26474417500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3047137000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3231000000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6278137000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2491876500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2598064000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5089940500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5539013500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5829064000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368077500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017251 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016692 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016967 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015975 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015273 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231398 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223875 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227541 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017079 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019404 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018282 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231747 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.223499 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227518 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017110 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019400 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018296 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016648 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016085 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016361 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019173 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018564 # mshr miss rate for overall accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016679 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016055 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016362 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019208 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.018529 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.018863 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15507.469476 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14830.063464 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15167.905490 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64979.244160 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 60982.963460 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62983.285112 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13848.966558 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13920.725989 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13885.163493 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13655.419489 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13448.515275 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.730250 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15522.191338 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14827.480312 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15174.574606 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 64746.605338 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 61192.857047 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 62975.371685 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13784.777449 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13975.723264 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13880.937637 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13579.776158 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13510.567891 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13541.754633 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36731.464128 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34548.101298 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.705941 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33484.119869 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31581.105705 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.606414 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203199.486872 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200212.775849 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201652.129231 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186345.470162 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182743.274648 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.427743 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195252.368375 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192034.386127 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193590.307695 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36643.346147 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 34632.739096 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35638.976495 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33400.343638 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 31660.957171 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32530.448432 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203237.310745 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 200123.877361 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201623.000835 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 186364.258470 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182730.623154 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184491.663344 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 195283.228741 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 191979.185193 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 193574.974032 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1695285 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.436603 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113852008 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1695797 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.137758 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1695832 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.436658 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113855734 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1696344 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.118305 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 29075840500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 59.971705 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.464899 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117132 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879814 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996946 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 60.007721 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 450.428938 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.117203 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.879744 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996947 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117243614 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117243614 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 55899037 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 57952971 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113852008 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 55899037 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 57952971 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113852008 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 55899037 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 57952971 # number of overall hits -system.cpu0.icache.overall_hits::total 113852008 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 840466 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855337 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1695803 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 840466 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855337 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1695803 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 840466 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855337 # number of overall misses -system.cpu0.icache.overall_misses::total 1695803 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11890019000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12374432000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 24264451000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11890019000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 12374432000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 24264451000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11890019000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 12374432000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 24264451000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 56739503 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 58808308 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115547811 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 56739503 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 58808308 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115547811 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 56739503 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 58808308 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115547811 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014813 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014544 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014676 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014813 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014544 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014676 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014813 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014544 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014676 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14146.936342 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14467.317560 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14308.531710 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14308.531710 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14146.936342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14467.317560 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14308.531710 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117248434 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117248434 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 55890585 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 57965149 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113855734 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 55890585 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 57965149 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113855734 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 55890585 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 57965149 # number of overall hits +system.cpu0.icache.overall_hits::total 113855734 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 841308 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855042 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1696350 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 841308 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855042 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1696350 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 841308 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855042 # number of overall misses +system.cpu0.icache.overall_misses::total 1696350 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11907607000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 12366012000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 24273619000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11907607000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 12366012000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 24273619000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11907607000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 12366012000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 24273619000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 56731893 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 58820191 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115552084 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 56731893 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 58820191 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115552084 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 56731893 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 58820191 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115552084 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014830 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014537 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014680 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014830 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014537 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014680 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014830 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014537 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014680 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14153.683312 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14462.461493 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14309.322369 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14153.683312 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14462.461493 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14309.322369 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14153.683312 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14462.461493 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14309.322369 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -926,56 +921,56 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1695285 # number of writebacks -system.cpu0.icache.writebacks::total 1695285 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 840466 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 855337 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1695803 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 840466 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 855337 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1695803 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 840466 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 855337 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1695803 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1695832 # number of writebacks +system.cpu0.icache.writebacks::total 1695832 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 841308 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 855042 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1696350 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 841308 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 855042 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1696350 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 841308 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 855042 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1696350 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11049553000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11519095000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 22568648000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11049553000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11519095000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 22568648000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11049553000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11519095000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 22568648000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11066299000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11510970000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 22577269000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11066299000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11510970000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 22577269000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11066299000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11510970000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 22577269000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 713903000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 428990000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1142893000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 713903000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 428990000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1142893000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014676 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014676 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014813 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014544 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014676 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13308.531710 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13146.936342 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13467.317560 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13308.531710 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014680 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014680 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014830 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014537 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014680 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13309.322369 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13153.683312 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 13462.461493 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13309.322369 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126466.430469 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127032.869411 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126678.452671 # average ReadReq mshr uncacheable latency @@ -1012,54 +1007,54 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6953 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6953 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2226 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4727 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 6953 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6953 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6953 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5856 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 13269.296448 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11561.565854 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7342.287931 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5855 99.98% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 6967 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6967 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 2209 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4758 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 6967 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6967 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6967 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5854 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 13310.386061 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11595.564813 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7355.876792 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 5853 99.98% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::262144-294911 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5856 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5854 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1639416500 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1639416500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1639416500 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3650 62.33% 62.33% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 2206 37.67% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5856 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6953 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 3666 62.62% 62.62% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 2188 37.38% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5854 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6967 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6953 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5856 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6967 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5854 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5856 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 12809 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12821 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12475099 # DTB read hits -system.cpu1.dtb.read_misses 5924 # DTB read misses -system.cpu1.dtb.write_hits 9998125 # DTB write hits -system.cpu1.dtb.write_misses 1029 # DTB write misses -system.cpu1.dtb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12477838 # DTB read hits +system.cpu1.dtb.read_misses 5947 # DTB read misses +system.cpu1.dtb.write_hits 9996447 # DTB write hits +system.cpu1.dtb.write_misses 1020 # DTB write misses +system.cpu1.dtb.flush_tlb 2941 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4683 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4688 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 921 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12481023 # DTB read accesses -system.cpu1.dtb.write_accesses 9999154 # DTB write accesses +system.cpu1.dtb.perms_faults 231 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12483785 # DTB read accesses +system.cpu1.dtb.write_accesses 9997467 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22473224 # DTB hits -system.cpu1.dtb.misses 6953 # DTB misses -system.cpu1.dtb.accesses 22480177 # DTB accesses +system.cpu1.dtb.hits 22474285 # DTB hits +system.cpu1.dtb.misses 6967 # DTB misses +system.cpu1.dtb.accesses 22481252 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1089,85 +1084,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3510 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3510 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 846 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2664 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3510 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3510 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3510 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2707 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 13960.103436 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 12104.099399 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7184.126564 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1964 72.55% 72.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 742 27.41% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 3507 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3507 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3507 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3507 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3507 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2709 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 13994.462901 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 12131.377414 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7198.145608 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1959 72.31% 72.31% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 749 27.65% 99.96% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2707 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2709 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1638889000 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1638889000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1638889000 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1861 68.75% 68.75% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 846 31.25% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2707 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1869 68.99% 68.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 840 31.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2709 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3510 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3510 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3507 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3507 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2707 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2707 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 6217 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 58808308 # ITB inst hits -system.cpu1.itb.inst_misses 3510 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2709 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2709 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 6216 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 58820191 # ITB inst hits +system.cpu1.itb.inst_misses 3507 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2942 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 476 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2941 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 480 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2708 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2713 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 58811818 # ITB inst accesses -system.cpu1.itb.hits 58808308 # DTB hits -system.cpu1.itb.misses 3510 # DTB misses -system.cpu1.itb.accesses 58811818 # DTB accesses -system.cpu1.numCycles 2909262869 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 58823698 # ITB inst accesses +system.cpu1.itb.hits 58820191 # DTB hits +system.cpu1.itb.misses 3507 # DTB misses +system.cpu1.itb.accesses 58823698 # DTB accesses +system.cpu1.numCycles 2909297686 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 57249193 # Number of instructions committed -system.cpu1.committedOps 68969707 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 61038090 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5951 # Number of float alu accesses -system.cpu1.num_func_calls 5071147 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7673896 # number of instructions that are conditional controls -system.cpu1.num_int_insts 61038090 # number of integer instructions -system.cpu1.num_fp_insts 5951 # number of float instructions -system.cpu1.num_int_register_reads 111115264 # number of times the integer registers were read -system.cpu1.num_int_register_writes 42140927 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4654 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 249224724 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 26227815 # number of times the CC registers were written -system.cpu1.num_mem_refs 23129732 # number of memory refs -system.cpu1.num_load_insts 12642519 # Number of load instructions -system.cpu1.num_store_insts 10487213 # Number of store instructions -system.cpu1.num_idle_cycles 2689871255.481362 # Number of idle cycles -system.cpu1.num_busy_cycles 219391613.518638 # Number of busy cycles -system.cpu1.not_idle_fraction 0.075411 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.924589 # Percentage of idle cycles -system.cpu1.Branches 13171953 # Number of branches fetched -system.cpu1.op_class::No_OpClass 2206 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 47377307 67.13% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 58319 0.08% 67.22% # Class of executed instruction +system.cpu1.committedInsts 57262734 # Number of instructions committed +system.cpu1.committedOps 68983998 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 61052130 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses +system.cpu1.num_func_calls 5075478 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7674901 # number of instructions that are conditional controls +system.cpu1.num_int_insts 61052130 # number of integer instructions +system.cpu1.num_fp_insts 5870 # number of float instructions +system.cpu1.num_int_register_reads 111137302 # number of times the integer registers were read +system.cpu1.num_int_register_writes 42154976 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4637 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1234 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 249286409 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26228170 # number of times the CC registers were written +system.cpu1.num_mem_refs 23131429 # number of memory refs +system.cpu1.num_load_insts 12645834 # Number of load instructions +system.cpu1.num_store_insts 10485595 # Number of store instructions +system.cpu1.num_idle_cycles 2689887383.006891 # Number of idle cycles +system.cpu1.num_busy_cycles 219410302.993109 # Number of busy cycles +system.cpu1.not_idle_fraction 0.075417 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.924583 # Percentage of idle cycles +system.cpu1.Branches 13176890 # Number of branches fetched +system.cpu1.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 47391308 67.14% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 58256 0.08% 67.22% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction @@ -1191,21 +1186,22 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.22% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.22% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4478 0.01% 67.23% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4483 0.01% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12642519 17.91% 85.14% # Class of executed instruction -system.cpu1.op_class::MemWrite 10487213 14.86% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12645834 17.92% 85.15% # Class of executed instruction +system.cpu1.op_class::MemWrite 10485595 14.85% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 70572042 # Class of executed instruction +system.cpu1.op_class::total 70587679 # Class of executed instruction system.iobus.trans_dist::ReadReq 30177 # Transaction distribution system.iobus.trans_dist::ReadResp 30177 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) @@ -1221,16 +1217,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 178382 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) @@ -1246,26 +1240,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321056 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480181 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46335000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46334000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 98000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 95000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 644000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 95000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 644000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) @@ -1286,31 +1279,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6286500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6288000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 172500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 36457000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 36458500 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 186225545 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 126500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186202055 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 37000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36728000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36418 # number of replacements -system.iocache.tags.tagsinuse 1.084308 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.084397 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36434 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 313834390000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084308 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067769 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067769 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 1.084397 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067775 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067775 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1324,14 +1311,14 @@ system.iocache.demand_misses::realview.ide 228 # system.iocache.demand_misses::total 228 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 228 # number of overall misses system.iocache.overall_misses::total 228 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28182877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28182877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4712497178 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4712497178 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28182877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28182877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28182877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28182877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28184876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28184876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4715128669 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4715128669 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28184876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28184876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28184876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28184876 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 228 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 228 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1348,19 +1335,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123609.109649 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123609.109649 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130093.230400 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130093.230400 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123609.109649 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123609.109649 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123609.109649 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 617 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123617.877193 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123617.877193 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130165.875359 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130165.875359 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123617.877193 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123617.877193 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123617.877193 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 572 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 60 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.283333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.533333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1374,14 +1361,14 @@ system.iocache.demand_mshr_misses::realview.ide 228 system.iocache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 228 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16782877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16782877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2901297178 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2901297178 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16782877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16782877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16782877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16782877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16784876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16784876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2903928669 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2903928669 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16784876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16784876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16784876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16784876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1390,37 +1377,37 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73609.109649 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 73609.109649 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80093.230400 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80093.230400 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 73609.109649 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 73609.109649 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 73609.109649 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 73609.109649 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73617.877193 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73617.877193 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80165.875359 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80165.875359 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73617.877193 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73617.877193 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 87564 # number of replacements -system.l2c.tags.tagsinuse 64865.205876 # Cycle average of tags in use -system.l2c.tags.total_refs 4550112 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 152799 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 29.778415 # Average number of references to valid blocks. +system.l2c.tags.replacements 87560 # number of replacements +system.l2c.tags.tagsinuse 64865.201521 # Cycle average of tags in use +system.l2c.tags.total_refs 4551354 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 152795 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 29.787323 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50199.141301 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905024 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4090.389058 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2504.726247 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 50199.128097 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.905025 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4090.007642 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2504.647366 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.838092 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.itb.walker 0.000605 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5610.428826 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2455.776722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5610.818089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2455.856604 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.062414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.038219 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.062409 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.038218 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.085608 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037472 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.085614 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037473 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.989764 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65231 # Occupied blocks per task id @@ -1428,228 +1415,228 @@ system.l2c.tags.age_task_id_blocks_1023::4 4 # system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6848 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56203 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6852 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56199 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.995346 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 40556804 # Number of tag accesses -system.l2c.tags.data_accesses 40556804 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5806 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3022 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6360 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3498 # number of ReadReq hits -system.l2c.ReadReq_hits::total 18686 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 683842 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 683842 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 1664516 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 1664516 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits +system.l2c.tags.tag_accesses 40566832 # Number of tag accesses +system.l2c.tags.data_accesses 40566832 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5848 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3044 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6379 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3501 # number of ReadReq hits +system.l2c.ReadReq_hits::total 18772 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 683867 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 683867 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 1665046 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 1665046 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 80852 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 86095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 166947 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 832656 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 845134 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1677790 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 253841 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 257681 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 511522 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5806 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3022 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 832656 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 334693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6360 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3498 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 845134 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 343776 # number of demand (read+write) hits -system.l2c.demand_hits::total 2374945 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5806 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3022 # number of overall hits -system.l2c.overall_hits::cpu0.inst 832656 # number of overall hits -system.l2c.overall_hits::cpu0.data 334693 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6360 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3498 # number of overall hits -system.l2c.overall_hits::cpu1.inst 845134 # number of overall hits -system.l2c.overall_hits::cpu1.data 343776 # number of overall hits -system.l2c.overall_hits::total 2374945 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 81302 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 85662 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 166964 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 833466 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 844870 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1678336 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 254311 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 257239 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 511550 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5848 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3044 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833466 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 335613 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6379 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3501 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 844870 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 342901 # number of demand (read+write) hits +system.l2c.demand_hits::total 2375622 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5848 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3044 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833466 # number of overall hits +system.l2c.overall_hits::cpu0.data 335613 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6379 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3501 # number of overall hits +system.l2c.overall_hits::cpu1.inst 844870 # number of overall hits +system.l2c.overall_hits::cpu1.data 342901 # number of overall hits +system.l2c.overall_hits::total 2375622 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 8 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1384 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1358 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2742 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1368 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1372 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2740 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 67226 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 61688 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 128914 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 7792 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 10187 # number of ReadCleanReq misses +system.l2c.ReadExReq_misses::cpu0.data 67111 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 61802 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 128913 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 7825 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 10154 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 17979 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 6563 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 5608 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 6560 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 5611 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::total 12171 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7792 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73789 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7825 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73671 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 10187 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 67296 # number of demand (read+write) misses -system.l2c.demand_misses::total 159072 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10154 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 67413 # number of demand (read+write) misses +system.l2c.demand_misses::total 159071 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7792 # number of overall misses -system.l2c.overall_misses::cpu0.data 73789 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7825 # number of overall misses +system.l2c.overall_misses::cpu0.data 73671 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 10187 # number of overall misses -system.l2c.overall_misses::cpu1.data 67296 # number of overall misses -system.l2c.overall_misses::total 159072 # number of overall misses +system.l2c.overall_misses::cpu1.inst 10154 # number of overall misses +system.l2c.overall_misses::cpu1.data 67413 # number of overall misses +system.l2c.overall_misses::total 159071 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 530500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 398500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 133000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 1062000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 1048500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 809000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1857500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 808500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1857000 # number of UpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8525926000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 7856246500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 16382172500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1017223000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1332151500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 2349374500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 871059500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 735537500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1606597000 # number of ReadSharedReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8507840500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 7872807000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 16380647500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1024152500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 1327263000 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 2351415500 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 871431000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 737412500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1608843500 # number of ReadSharedReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 530500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1017223000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 9396985500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1024152500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9379271500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 398500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 133000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1332151500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 8591784000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20339206000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 1327263000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 8610219500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20341968500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 530500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1017223000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 9396985500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1024152500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9379271500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 398500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 133000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1332151500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 8591784000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20339206000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5810 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 6363 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 3499 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 18694 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 683842 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 683842 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 1664516 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 1664516 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1398 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1367 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2765 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 1327263000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 8610219500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20341968500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5852 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3044 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 6382 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3502 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 18780 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 683867 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 683867 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 1665046 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 1665046 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1381 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1382 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2763 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 148078 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 147783 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295861 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 840448 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 855321 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 1695769 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 260404 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 263289 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 523693 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5810 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 840448 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 408482 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 6363 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 3499 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855321 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 411072 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2534017 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5810 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 840448 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 408482 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 6363 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 3499 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855321 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 411072 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2534017 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 148413 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 147464 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295877 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 841291 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 855024 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 1696315 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 260871 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 262850 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 523721 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5852 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3044 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 841291 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 409284 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6382 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3502 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 410314 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2534693 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5852 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3044 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 841291 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 409284 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6382 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3502 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 410314 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2534693 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000286 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.000428 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989986 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.993416 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991682 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.000426 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990587 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992764 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991676 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.453990 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.417423 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.435725 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009271 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011910 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.010602 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.025203 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021300 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.023241 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000688 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009271 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.180642 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for demand accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.452191 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.419099 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.435698 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.009301 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.011876 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.010599 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.025147 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.021347 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.023239 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009301 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.180000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.itb.walker 0.000286 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011910 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.163709 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.062775 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000688 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009271 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.180642 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000471 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011876 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.164296 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.062758 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000684 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009301 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.180000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000470 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.itb.walker 0.000286 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011910 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.163709 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.062775 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011876 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.164296 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.062758 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 132625 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 133000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 132750 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 757.586705 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 595.729013 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 677.425237 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 766.447368 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 589.285714 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 677.737226 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126824.829679 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127354.534107 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 127078.304141 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130547.099589 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130769.755571 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 130673.257690 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132722.763980 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131158.612696 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 132002.054063 # average ReadSharedReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 126772.667670 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 127387.576454 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 127067.460225 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 130882.108626 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 130713.314950 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 130786.779020 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 132840.091463 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 131422.651934 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 132186.632158 # average ReadSharedReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 130547.099589 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 127349.408448 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 130882.108626 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 127312.938605 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 130769.755571 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 127671.540656 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 127861.634983 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 130713.314950 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 127723.428716 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 127879.805244 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 132625 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 130547.099589 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 127349.408448 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 130882.108626 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 127312.938605 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132833.333333 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 133000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 130769.755571 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 127671.540656 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 127861.634983 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 130713.314950 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 127723.428716 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 127879.805244 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1664,231 +1651,231 @@ system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 3 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 8 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1384 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1358 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2742 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1368 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1372 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2740 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 67226 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 61688 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 128914 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 7792 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10187 # number of ReadCleanReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 67111 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 61802 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 128913 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 7825 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10154 # number of ReadCleanReq MSHR misses system.l2c.ReadCleanReq_mshr_misses::total 17979 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6563 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 5608 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 6560 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 5611 # number of ReadSharedReq MSHR misses system.l2c.ReadSharedReq_mshr_misses::total 12171 # number of ReadSharedReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 7792 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 73789 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7825 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 73671 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 3 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 10187 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 67296 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 159072 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10154 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 67413 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 159071 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 7792 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 73789 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 7825 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 73671 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 10187 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 67296 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 159072 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10154 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 67413 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 159071 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 5645 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15006 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 14993 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 3377 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16132 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16145 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13389 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14200 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 13371 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14218 # number of WriteReq MSHR uncacheable system.l2c.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 5645 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28395 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 28364 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 3377 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30332 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 30363 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 490500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 368500 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 123000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 982000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 98005000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 96151000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 194156000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 96874500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 97146000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 194020500 # number of UpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 139000 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 139000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7853666000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7239366500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 15093032500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 939303000 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1230281500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 2169584500 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 805429500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 679457500 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1484887000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7836730500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 7254787000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 15091517500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 945902500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 1225723000 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 2171625500 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 805831000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 681302500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 1487133500 # number of ReadSharedReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 490500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 939303000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 8659095500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 945902500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 8642561500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 368500 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 123000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 1230281500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 7918824000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 18748486000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 1225723000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 7936089500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 18751258500 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 490500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 939303000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 8659095500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 945902500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 8642561500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 368500 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 123000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 1230281500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 7918824000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 18748486000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 1225723000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 7936089500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 18751258500 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 643340500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2861588500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2859676500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 386777500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3028128000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6919834500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2340936000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2431594500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4772530500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3029132000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6918926500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2338041000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2434495500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4772536500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 643340500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5202524500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5197717500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 386777500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5459722500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11692365000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5463627500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11691463000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.000428 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.989986 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.993416 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991682 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.000426 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.990587 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992764 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991676 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.453990 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.417423 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.435725 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010602 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025203 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021300 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023241 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for demand accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.452191 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.419099 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.435698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.010599 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.025147 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.023239 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.062775 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009271 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.180642 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000471 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062758 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000684 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009301 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.180000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000470 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000286 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011910 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.163709 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.062775 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.164296 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062758 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 122750 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70812.861272 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70803.387334 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70808.169220 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70814.692982 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70806.122449 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70810.401460 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116824.829679 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117354.534107 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 117078.304141 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120673.257690 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122722.763980 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121158.612696 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122002.054063 # average ReadSharedReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 116772.667670 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 117387.576454 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 117067.460225 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 120786.779020 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 122840.091463 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 121422.651934 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 122186.632158 # average ReadSharedReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 122625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120547.099589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117349.408448 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120882.108626 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 117312.938605 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122833.333333 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120769.755571 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117671.540656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 117861.634983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 120713.314950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 117723.428716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 117879.805244 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190696.288151 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190734.109251 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187709.397471 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172306.635956 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174840.241990 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171239.049296 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.715720 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187620.439765 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 172284.026394 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 174859.098048 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171226.297651 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172986.933198 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113966.430469 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183219.739391 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 183250.511211 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 114532.869411 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179998.763682 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 172583.580569 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 179943.599117 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 172570.266720 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40160 # Transaction distribution system.membus.trans_dist::ReadResp 70546 # Transaction distribution system.membus.trans_dist::WriteReq 27589 # Transaction distribution system.membus.trans_dist::WriteResp 27589 # Transaction distribution system.membus.trans_dist::WritebackDirty 117374 # Transaction distribution -system.membus.trans_dist::CleanEvict 6393 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4497 # Transaction distribution +system.membus.trans_dist::CleanEvict 6389 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4498 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4499 # Transaction distribution -system.membus.trans_dist::ReadExReq 127159 # Transaction distribution -system.membus.trans_dist::ReadExResp 127159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4500 # Transaction distribution +system.membus.trans_dist::ReadExReq 127155 # Transaction distribution +system.membus.trans_dist::ReadExResp 127155 # Transaction distribution system.membus.trans_dist::ReadSharedReq 30386 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438823 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 546415 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 546405 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108894 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 655309 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 655299 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15302204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15465557 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15301948 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15465301 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17782677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17782421 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 492 # Total snoops (count) -system.membus.snoop_fanout::samples 390002 # Request fanout histogram +system.membus.snoop_fanout::samples 389996 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 390002 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 389996 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 390002 # Request fanout histogram -system.membus.reqLayer0.occupancy 90453500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 389996 # Request fanout histogram +system.membus.reqLayer0.occupancy 90452500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1722000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1723000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 823113783 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 823109916 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 952221498 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 952195249 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64071640 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64063181 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -1931,60 +1918,60 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 5052869 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 2537534 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 38120 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 5053996 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 2538070 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 38133 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 581 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 581 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 74671 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2294380 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 74719 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2295003 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 801219 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 1664516 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 134433 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2765 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 801245 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 1665046 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 134452 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2763 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2767 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295861 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295861 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1695803 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 523921 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2765 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295877 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295877 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1696350 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 523949 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5074132 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2573976 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18410 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34795 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7701313 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215094328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96414109 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26084 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48692 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 311583213 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 176501 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2780821 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021276 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144303 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5075755 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2574108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18469 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34870 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7703202 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 215163192 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96418525 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 48936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 311656837 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 176461 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2781455 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021257 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.144239 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 2721656 97.87% 97.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 59165 2.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 2722330 97.87% 97.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 59125 2.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2780821 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4960265000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2781455 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4961451000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 380876 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2552726500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2553547000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1275647499 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1275712000 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11889000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 11923000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22622000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 22636000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 89c5a64dd..5c3616770 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -30,7 +30,7 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -841,8 +841,8 @@ frontend_latency=2 response_latency=2 use_default_range=false width=16 -default=system.pc.pciconfig.pio -master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +default=system.pc.pci_host.pio +master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] @@ -869,7 +869,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[19] +cpu_side=system.iobus.master[18] mem_side=system.membus.slave[4] [system.iocache.tags] @@ -919,7 +919,7 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge eventq_index=0 intrctrl=system.intrctrl system=system @@ -940,7 +940,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[13] +pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 @@ -952,7 +952,7 @@ pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal -pio=system.iobus.master[14] +pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal @@ -978,7 +978,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[15] +pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake @@ -996,7 +996,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[16] +pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake @@ -1014,7 +1014,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[17] +pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake @@ -1032,7 +1032,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[18] +pio=system.iobus.master[17] [system.pc.i_dont_exist1] type=IsaFake @@ -1050,7 +1050,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[11] +pio=system.iobus.master[10] [system.pc.i_dont_exist2] type=IsaFake @@ -1068,17 +1068,19 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[12] +pio=system.iobus.master[11] -[system.pc.pciconfig] -type=PciConfigAll -bus=0 +[system.pc.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=13835058055282163712 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=9223372036854775808 platform=system.pc -size=16777216 system=system pio=system.iobus.default @@ -1201,14 +1203,13 @@ config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 eventq_index=0 +host=system.pc.pci_host io_shift=0 pci_bus=0 pci_dev=4 pci_func=0 pio_latency=30000 -platform=system.pc system=system -config=system.iobus.master[4] dma=system.iobus.slave[1] pio=system.iobus.master[3] @@ -1232,7 +1233,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/work/gem5/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1255,7 +1256,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1360,7 +1361,7 @@ pio_addr=4273995776 pio_latency=100000 system=system int_master=system.iobus.slave[2] -pio=system.iobus.master[10] +pio=system.iobus.master[9] [system.pc.south_bridge.keyboard] type=I8042 @@ -1374,7 +1375,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=100000 system=system -pio=system.iobus.master[5] +pio=system.iobus.master[4] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin @@ -1395,7 +1396,7 @@ pio_addr=9223372036854775840 pio_latency=100000 slave=system.pc.south_bridge.pic2 system=system -pio=system.iobus.master[6] +pio=system.iobus.master[5] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin @@ -1412,7 +1413,7 @@ pio_addr=9223372036854775968 pio_latency=100000 slave=Null system=system -pio=system.iobus.master[7] +pio=system.iobus.master[6] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin @@ -1427,7 +1428,7 @@ int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 system=system -pio=system.iobus.master[8] +pio=system.iobus.master[7] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin @@ -1441,7 +1442,7 @@ i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[8] [system.physmem] type=SimpleMemory diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 3e11aa2b8..ed7b11845 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 15 2015 15:16:56 -gem5 started Nov 15 2015 15:17:27 -gem5 executing on ribera.cs.wisc.edu, pid 9888 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic +gem5 compiled Dec 4 2015 15:10:31 +gem5 started Dec 4 2015 15:38:36 +gem5 executing on e104799-lin, pid 32389 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112152301500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 51bcfd8ae..85513c27b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112152 # Nu sim_ticks 5112152301500 # Number of ticks simulated final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 934572 # Simulator instruction rate (inst/s) -host_op_rate 1913274 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23880410274 # Simulator tick rate (ticks/s) -host_mem_usage 654088 # Number of bytes of host memory used -host_seconds 214.07 # Real time elapsed on the host +host_inst_rate 973581 # Simulator instruction rate (inst/s) +host_op_rate 1993134 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24877176621 # Simulator tick rate (ticks/s) +host_mem_usage 614804 # Number of bytes of host memory used +host_seconds 205.50 # Real time elapsed on the host sim_insts 200066731 # Number of instructions simulated sim_ops 409580371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -514,7 +514,6 @@ system.iobus.trans_dist::MessageResp 1696 # Tr system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) @@ -528,7 +527,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 20044316 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) @@ -538,7 +537,6 @@ system.iobus.pkt_count::total 20142954 # Pa system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) @@ -552,7 +550,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 10028276 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 61d43af95..3cac96d35 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 kernel_addr_check=true load_addr_mask=18446744073709551615 load_offset=0 @@ -30,7 +30,7 @@ memories=system.physmem mmap_using_noreserve=false multi_thread=false num_work_ids=16 -readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh smbios_table=system.smbios_table symbolfile= work_begin_ckpt_count=0 @@ -837,8 +837,8 @@ frontend_latency=2 response_latency=2 use_default_range=false width=16 -default=system.pc.pciconfig.pio -master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +default=system.pc.pci_host.pio +master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master [system.iocache] @@ -865,7 +865,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[19] +cpu_side=system.iobus.master[18] mem_side=system.membus.slave[4] [system.iocache.tags] @@ -915,7 +915,7 @@ pio=system.membus.default [system.pc] type=Pc -children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pciconfig south_bridge +children=behind_pci com_1 fake_com_2 fake_com_3 fake_com_4 fake_floppy i_dont_exist1 i_dont_exist2 pci_host south_bridge eventq_index=0 intrctrl=system.intrctrl system=system @@ -936,7 +936,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[13] +pio=system.iobus.master[12] [system.pc.com_1] type=Uart8250 @@ -948,7 +948,7 @@ pio_latency=100000 platform=system.pc system=system terminal=system.pc.com_1.terminal -pio=system.iobus.master[14] +pio=system.iobus.master[13] [system.pc.com_1.terminal] type=Terminal @@ -974,7 +974,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[15] +pio=system.iobus.master[14] [system.pc.fake_com_3] type=IsaFake @@ -992,7 +992,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[16] +pio=system.iobus.master[15] [system.pc.fake_com_4] type=IsaFake @@ -1010,7 +1010,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[17] +pio=system.iobus.master[16] [system.pc.fake_floppy] type=IsaFake @@ -1028,7 +1028,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[18] +pio=system.iobus.master[17] [system.pc.i_dont_exist1] type=IsaFake @@ -1046,7 +1046,7 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[11] +pio=system.iobus.master[10] [system.pc.i_dont_exist2] type=IsaFake @@ -1064,17 +1064,19 @@ ret_data8=255 system=system update_data=false warn_access= -pio=system.iobus.master[12] +pio=system.iobus.master[11] -[system.pc.pciconfig] -type=PciConfigAll -bus=0 +[system.pc.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=13835058055282163712 +conf_device_bits=8 +conf_size=16777216 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=9223372036854775808 platform=system.pc -size=16777216 system=system pio=system.iobus.default @@ -1197,14 +1199,13 @@ config_latency=20000 ctrl_offset=0 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1 eventq_index=0 +host=system.pc.pci_host io_shift=0 pci_bus=0 pci_dev=4 pci_func=0 pio_latency=30000 -platform=system.pc system=system -config=system.iobus.master[4] dma=system.iobus.slave[1] pio=system.iobus.master[3] @@ -1228,7 +1229,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/work/gem5/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1251,7 +1252,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/work/gem5/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1356,7 +1357,7 @@ pio_addr=4273995776 pio_latency=100000 system=system int_master=system.iobus.slave[2] -pio=system.iobus.master[10] +pio=system.iobus.master[9] [system.pc.south_bridge.keyboard] type=I8042 @@ -1370,7 +1371,7 @@ mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=100000 system=system -pio=system.iobus.master[5] +pio=system.iobus.master[4] [system.pc.south_bridge.keyboard.keyboard_int_pin] type=X86IntSourcePin @@ -1391,7 +1392,7 @@ pio_addr=9223372036854775840 pio_latency=100000 slave=system.pc.south_bridge.pic2 system=system -pio=system.iobus.master[6] +pio=system.iobus.master[5] [system.pc.south_bridge.pic1.output] type=X86IntSourcePin @@ -1408,7 +1409,7 @@ pio_addr=9223372036854775968 pio_latency=100000 slave=Null system=system -pio=system.iobus.master[7] +pio=system.iobus.master[6] [system.pc.south_bridge.pic2.output] type=X86IntSourcePin @@ -1423,7 +1424,7 @@ int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=100000 system=system -pio=system.iobus.master[8] +pio=system.iobus.master[7] [system.pc.south_bridge.pit.int_pin] type=X86IntSourcePin @@ -1437,7 +1438,7 @@ i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=100000 system=system -pio=system.iobus.master[9] +pio=system.iobus.master[8] [system.physmem] type=DRAMCtrl diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index eaa04330e..1ecfaaabf 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 15 2015 15:16:56 -gem5 started Nov 15 2015 15:17:25 -gem5 executing on ribera.cs.wisc.edu, pid 9883 -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing +gem5 compiled Dec 4 2015 15:10:31 +gem5 started Dec 4 2015 15:10:45 +gem5 executing on e104799-lin, pid 29579 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /work/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5194978362500 because m5_exit instruction encountered +Exiting @ tick 5194947216500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index efb97e559..714c6f363 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.194978 # Number of seconds simulated -sim_ticks 5194978362500 # Number of ticks simulated -final_tick 5194978362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.194947 # Number of seconds simulated +sim_ticks 5194947216500 # Number of ticks simulated +final_tick 5194947216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 576808 # Simulator instruction rate (inst/s) -host_op_rate 1111789 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 23330637170 # Simulator tick rate (ticks/s) -host_mem_usage 654084 # Number of bytes of host memory used -host_seconds 222.67 # Real time elapsed on the host +host_inst_rate 724563 # Simulator instruction rate (inst/s) +host_op_rate 1396583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29306793052 # Simulator tick rate (ticks/s) +host_mem_usage 614800 # Number of bytes of host memory used +host_seconds 177.26 # Real time elapsed on the host sim_insts 128436556 # Number of instructions simulated -sim_ops 247559471 # Number of ops (including micro ops) simulated +sim_ops 247559476 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory @@ -33,21 +33,21 @@ system.physmem.num_writes::writebacks 127367 # Nu system.physmem.num_writes::total 127367 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1738430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158074 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738440 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1902034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158073 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1569109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1569109 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1569109 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 1902045 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158074 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1569119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1569119 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1569119 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1738430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 158074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738440 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3471143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3471164 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 154391 # Number of read requests accepted system.physmem.writeReqs 127367 # Number of write requests accepted system.physmem.readBursts 154391 # Number of DRAM read bursts, including those serviced by the write queue @@ -94,7 +94,7 @@ system.physmem.perBankWrBursts::14 8023 # Pe system.physmem.perBankWrBursts::15 7877 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5194978301500 # Total gap between requests +system.physmem.totGap 5194947155500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -109,8 +109,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 127367 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 151032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2782 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see @@ -207,17 +207,17 @@ system.physmem.wrQLenPdf::62 8 # Wh system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 56850 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 316.988566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.998481 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.316521 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20120 35.39% 35.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13756 24.20% 59.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.004327 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.313677 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20115 35.38% 35.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13762 24.21% 59.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 6339 11.15% 70.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3490 6.14% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2421 4.26% 81.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1596 2.81% 83.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3489 6.14% 76.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2420 4.26% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1597 2.81% 83.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1162 2.04% 85.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 976 1.72% 87.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6990 12.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 977 1.72% 87.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6989 12.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 56850 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 5891 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::mean 26.179766 # Reads before turning the bus around for writes @@ -259,12 +259,12 @@ system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Wr system.physmem.wrPerTurnAround::156-159 2 0.03% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 3 0.05% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5891 # Writes before turning the bus around for reads -system.physmem.totQLat 1582264251 # Total ticks spent queuing -system.physmem.totMemAccLat 4474283001 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1583291001 # Total ticks spent queuing +system.physmem.totMemAccLat 4475309751 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 771205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10258.39 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10265.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29008.39 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29015.05 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s @@ -279,69 +279,69 @@ system.physmem.readRowHits 125535 # Nu system.physmem.writeRowHits 99190 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads system.physmem.writeRowHitRate 77.88 # Row buffer hit rate for writes -system.physmem.avgGap 18437731.32 # Average gap between requests +system.physmem.avgGap 18437620.78 # Average gap between requests system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 210712320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 114972000 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 210727440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 114980250 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 605896200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 410112720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 137072385045 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2996748141750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3474472943475 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.813734 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4985245725974 # Time in different power states -system.physmem_0.memoryStateTime::REF 173471480000 # Time in different power states +system.physmem_0.refreshEnergy 339308689200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 137072684295 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2996729192250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3474452282355 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.813767 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4985214188974 # Time in different power states +system.physmem_0.memoryStateTime::REF 173470440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36261007776 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36262439776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219073680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119534250 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 219058560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119526000 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 597183600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 415011600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 137522699865 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2996353144500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3474537370935 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.826133 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4984581893484 # Time in different power states -system.physmem_1.memoryStateTime::REF 173471480000 # Time in different power states +system.physmem_1.refreshEnergy 339308689200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 137519874945 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2996336934750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3474516278655 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.826083 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4984554950984 # Time in different power states +system.physmem_1.memoryStateTime::REF 173470440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 36924866266 # Time in different power states +system.physmem_1.memoryStateTime::ACT 36921702766 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10389956725 # number of cpu cycles simulated +system.cpu.numCycles 10389894433 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.committedInsts 128436556 # Number of instructions committed -system.cpu.committedOps 247559471 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232158304 # Number of integer alu accesses +system.cpu.committedOps 247559476 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232158308 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 2315823 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23152915 # number of instructions that are conditional controls -system.cpu.num_int_insts 232158304 # number of integer instructions +system.cpu.num_conditional_control_insts 23152916 # number of instructions that are conditional controls +system.cpu.num_int_insts 232158308 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 434959162 # number of times the integer registers were read -system.cpu.num_int_register_writes 197962951 # number of times the integer registers were written +system.cpu.num_int_register_reads 434959182 # number of times the integer registers were read +system.cpu.num_int_register_writes 197962963 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132872909 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95460932 # number of times the CC registers were written +system.cpu.num_cc_register_reads 132872914 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95460933 # number of times the CC registers were written system.cpu.num_mem_refs 22321110 # number of memory refs system.cpu.num_load_insts 13911495 # Number of load instructions system.cpu.num_store_insts 8409615 # Number of store instructions system.cpu.num_idle_cycles 9773995534.086119 # Number of idle cycles -system.cpu.num_busy_cycles 615961190.913881 # Number of busy cycles -system.cpu.not_idle_fraction 0.059284 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.940716 # Percentage of idle cycles -system.cpu.Branches 26327381 # Number of branches fetched -system.cpu.op_class::No_OpClass 172225 0.07% 0.07% # Class of executed instruction +system.cpu.num_busy_cycles 615898898.913881 # Number of busy cycles +system.cpu.not_idle_fraction 0.059279 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.940721 # Percentage of idle cycles +system.cpu.Branches 26327382 # Number of branches fetched +system.cpu.op_class::No_OpClass 172226 0.07% 0.07% # Class of executed instruction system.cpu.op_class::IntAlu 224809718 90.81% 90.88% # Class of executed instruction system.cpu.op_class::IntMult 140099 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 122811 0.05% 90.99% # Class of executed instruction +system.cpu.op_class::IntDiv 122815 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -372,12 +372,12 @@ system.cpu.op_class::MemRead 13906523 5.62% 96.60% # Cl system.cpu.op_class::MemWrite 8409615 3.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247561007 # Class of executed instruction -system.cpu.dcache.tags.replacements 1623701 # number of replacements +system.cpu.op_class::total 247561012 # Class of executed instruction +system.cpu.dcache.tags.replacements 1623700 # number of replacements system.cpu.dcache.tags.tagsinuse 511.995481 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20139430 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1624213 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.399501 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 20139431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1624212 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.399509 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.995481 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy @@ -388,36 +388,36 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88718098 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88718098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12002647 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12002647 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8075474 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8075474 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 88718097 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88718097 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12002646 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12002646 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8075476 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8075476 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 59092 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 59092 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20078121 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20078121 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20137213 # number of overall hits -system.cpu.dcache.overall_hits::total 20137213 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 907310 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 907310 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 326145 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 326145 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 20078122 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20078122 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20137214 # number of overall hits +system.cpu.dcache.overall_hits::total 20137214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 907311 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 907311 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326143 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 326143 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 402797 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 402797 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1233455 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1233455 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636252 # number of overall misses -system.cpu.dcache.overall_misses::total 1636252 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13562374500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13562374500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18447994471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18447994471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32010368971 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32010368971 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32010368971 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32010368971 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 1233454 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1233454 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636251 # number of overall misses +system.cpu.dcache.overall_misses::total 1636251 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 13562069000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 13562069000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18448528971 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18448528971 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32010597971 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32010597971 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32010597971 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32010597971 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 12909957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 12909957 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 8401619 # number of WriteReq accesses(hits+misses) @@ -438,14 +438,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.057877 system.cpu.dcache.demand_miss_rate::total 0.057877 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.075149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.075149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.894876 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.894876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56563.781358 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56563.781358 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.793110 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25951.793110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.226796 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19563.226796 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.541692 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.541692 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56565.767075 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56565.767075 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.999808 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25951.999808 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.378706 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19563.378706 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 18014 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 511 # number of cycles access was blocked @@ -454,8 +454,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.252446 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540806 # number of writebacks -system.cpu.dcache.writebacks::total 1540806 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1540805 # number of writebacks +system.cpu.dcache.writebacks::total 1540805 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9476 # number of WriteReq MSHR hits @@ -464,38 +464,38 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 9763 system.cpu.dcache.demand_mshr_hits::total 9763 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 9763 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 9763 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907023 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907023 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316669 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316669 # number of WriteReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907024 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 907024 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316667 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 316667 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402763 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 402763 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1223692 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1223692 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1626455 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1626455 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1223691 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1223691 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1626454 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1626454 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12653263500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12653263500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17148578471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17148578471 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6516458500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6516458500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29801841971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29801841971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36318300471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36318300471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95164003500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95164003500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12652957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12652957000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17148864471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17148864471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6516948000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6516948000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29801821471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29801821471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36318769471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36318769471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95132083500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95132083500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786304500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786304500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97950308000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 97950308000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918388000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918388000 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070258 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070258 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037691 # mshr miss rate for WriteReq accesses @@ -506,29 +506,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057419 system.cpu.dcache.demand_mshr_miss_rate::total 0.057419 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074699 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074699 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13950.322649 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13950.322649 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54153.006676 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54153.006676 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16179.387133 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16179.387133 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.038411 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.038411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22329.729670 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22329.729670 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174182.667211 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174182.667211 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13949.969350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13949.969350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54154.251851 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54154.251851 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16180.602488 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16180.602488 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.041560 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.041560 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22330.031757 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22330.031757 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174124.242696 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174124.242696 # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161 # average WriteReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174828.220881 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174828.220881 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.247943 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.247943 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7583 # number of replacements system.cpu.dtb_walker_cache.tags.tagsinuse 5.052194 # Cycle average of tags in use system.cpu.dtb_walker_cache.tags.total_refs 13349 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 7599 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.tags.avg_refs 1.756679 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163389935000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5163358790000 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052194 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy @@ -612,58 +612,58 @@ system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9973. system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 790533 # number of replacements -system.cpu.icache.tags.tagsinuse 510.212427 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144635656 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 510.213577 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144635652 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 791045 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.841249 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 164582664500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.212427 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996509 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996509 # Average percentage of cache occupancy +system.cpu.icache.tags.avg_refs 182.841244 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 164551519500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.213577 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996511 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996511 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146217760 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146217760 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144635656 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144635656 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144635656 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144635656 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144635656 # number of overall hits -system.cpu.icache.overall_hits::total 144635656 # number of overall hits +system.cpu.icache.tags.tag_accesses 146217756 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146217756 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144635652 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144635652 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144635652 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144635652 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144635652 # number of overall hits +system.cpu.icache.overall_hits::total 144635652 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 791052 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791052 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 791052 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791052 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 791052 # number of overall misses system.cpu.icache.overall_misses::total 791052 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11850841500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11850841500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11850841500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11850841500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11850841500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11850841500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145426708 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145426708 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145426708 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145426708 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145426708 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145426708 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11851389500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11851389500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11851389500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11851389500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11851389500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11851389500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145426704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145426704 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145426704 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145426704 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145426704 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145426704 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.115654 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14981.115654 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.115654 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14981.115654 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.115654 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14981.115654 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.808402 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14981.808402 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.808402 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14981.808402 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.808402 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14981.808402 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,32 +680,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 791052 system.cpu.icache.demand_mshr_misses::total 791052 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 791052 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 791052 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11059789500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11059789500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11059789500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11059789500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11059789500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11059789500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060337500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11060337500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060337500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11060337500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060337500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11060337500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.115654 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.115654 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.115654 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.115654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.115654 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.115654 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.808402 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.808402 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.808402 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.808402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.808402 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.808402 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.069439 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.tagsinuse 3.069434 # Cycle average of tags in use system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5168995728500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069439 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.warmup_cycle 5168964583500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069434 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191840 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.191840 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id @@ -792,22 +792,22 @@ system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9568. system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9568.872145 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 87285 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64590.293077 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 64590.437600 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4366421 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 151981 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 28.730045 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50117.072106 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 50117.146585 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006346 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146905 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3409.574017 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.493703 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.764726 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146882 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3409.592137 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.545650 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.764727 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052026 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.168816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.985570 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.985572 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 64696 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id @@ -815,32 +815,32 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2800 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56265 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987183 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 39229745 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 39229745 # Number of data accesses -system.cpu.l2cache.WritebackDirty_hits::writebacks 1544563 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1544563 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 39229727 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39229727 # Number of data accesses +system.cpu.l2cache.WritebackDirty_hits::writebacks 1544562 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 1544562 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 790520 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 790520 # number of WritebackClean hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200934 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200934 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200932 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200932 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 778207 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 778207 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6472 # number of ReadSharedReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2856 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280544 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1289872 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280545 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 1289873 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 6472 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 2856 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.inst 778207 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481478 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2269013 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1481477 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2269012 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 6472 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 2856 # number of overall hits system.cpu.l2cache.overall_hits::cpu.inst 778207 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481478 # number of overall hits -system.cpu.l2cache.overall_hits::total 2269013 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1481477 # number of overall hits +system.cpu.l2cache.overall_hits::total 2269012 # number of overall hits system.cpu.l2cache.UpgradeReq_misses::cpu.data 1406 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1406 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 113512 # number of ReadExReq misses @@ -863,52 +863,52 @@ system.cpu.l2cache.overall_misses::cpu.data 142006 # system.cpu.l2cache.overall_misses::total 154844 # number of overall misses system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 53960000 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency::total 53960000 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14442230500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14442230500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1691982000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 1691982000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14442540500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 14442540500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1692530000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1692530000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 147000 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 637500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3748921500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3749706000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3749093000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3749877500 # number of ReadSharedReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 147000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 637500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1691982000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 18191152000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19883918500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1692530000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 18191633500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 19884948000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 147000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 637500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1691982000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 18191152000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19883918500 # number of overall miss cycles -system.cpu.l2cache.WritebackDirty_accesses::writebacks 1544563 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 1544563 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.overall_miss_latency::cpu.inst 1692530000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 18191633500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 19884948000 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 1544562 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 1544562 # number of WritebackDirty accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::writebacks 790520 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 790520 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1726 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 1726 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314446 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314446 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314444 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314444 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 791039 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::total 791039 # number of ReadCleanReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6473 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2861 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309038 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 1318372 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309039 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1318373 # number of ReadSharedReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6473 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 2861 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.inst 791039 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1623484 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2423857 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1623483 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2423856 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6473 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 2861 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 791039 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1623484 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2423857 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1623483 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2423856 # number of overall (read+write) accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814600 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814600 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360990 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.360990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360993 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.360993 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016222 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016222 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadSharedReq accesses @@ -927,24 +927,24 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.087470 system.cpu.l2cache.overall_miss_rate::total 0.063883 # miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38378.378378 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38378.378378 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127230.869864 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127230.869864 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131856.452618 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131856.452618 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127233.600853 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127233.600853 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131899.158354 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131899.158354 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147000 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 127500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131568.803959 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131568.631579 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131574.822770 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131574.649123 # average ReadSharedReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131856.452618 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128101.291495 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 128412.586216 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131899.158354 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128104.682197 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 128419.234843 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131856.452618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128101.291495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 128412.586216 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131899.158354 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128104.682197 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 128419.234843 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -985,36 +985,36 @@ system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 560266 system.cpu.l2cache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100407500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100407500 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13307110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13307110500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1563662000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1563662000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13307420500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13307420500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1564210000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1564210000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 137000 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 587500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3463981500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3464706000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3464153000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3464877500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 137000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1563662000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16771092000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18335478500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1564210000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16771573500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18336508000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 137000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1563662000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16771092000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18335478500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88334673500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88334673500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1564210000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16771573500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18336508000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88302753500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88302753500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626222500 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626222500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90960896000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90960896000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90928976000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90928976000 # number of overall MSHR uncacheable cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360993 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360993 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016222 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for ReadSharedReq accesses @@ -1033,68 +1033,68 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087470 system.cpu.l2cache.overall_mshr_miss_rate::total 0.063883 # mshr miss rate for overall accesses system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117230.869864 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117230.869864 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121856.452618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121856.452618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117233.600853 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117233.600853 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121899.158354 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121899.158354 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121568.803959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121568.631579 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121574.822770 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121574.649123 # average ReadSharedReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121899.158354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118104.682197 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118419.234843 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161682.658059 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161682.658059 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121899.158354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118104.682197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118419.234843 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161624.233544 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161624.233544 # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483 # average WriteReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162353.053728 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162353.053728 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.080790 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.080790 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 4855760 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425141 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 4855758 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425140 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2660535 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2660536 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1671932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1671931 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 790520 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 91754 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314452 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314450 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314450 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 791052 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323668 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323669 # Transaction distribution system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372611 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5995602 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5995599 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8612 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19573 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8396398 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8396395 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101219776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204103208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204103080 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232576 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 306160808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 306160680 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 189298 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3174836 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3174835 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.077863 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3163102 99.63% 99.63% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3163101 99.63% 99.63% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 9208 0.29% 99.92% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 2526 0.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram @@ -1102,14 +1102,14 @@ system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Re system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3174836 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5050069000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3174835 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5050067000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1186578000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2990781992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2990780492 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1124,7 +1124,6 @@ system.iobus.trans_dist::MessageResp 1654 # Tr system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) @@ -1138,7 +1137,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 452398 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) @@ -1148,7 +1147,6 @@ system.iobus.pkt_count::total 550830 # Pa system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) @@ -1162,7 +1160,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 232479 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) @@ -1177,38 +1175,36 @@ system.iobus.reqLayer2.occupancy 6000 # La system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 10045000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 149500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1094500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 1094500 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 79000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 79000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 50500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 306124500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 306124500 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1113000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1113000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 177500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 177500 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 24284500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 24284500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 240815899 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 240815899 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 1216500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 1067000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 441392000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 50036000 # Layer occupancy (ticks) @@ -1220,7 +1216,7 @@ system.iocache.tags.tagsinuse 0.108263 # Cy system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5048362105000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 5048330960000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy @@ -1363,11 +1359,11 @@ system.membus.reqLayer1.occupancy 503567500 # La system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 4013184 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 852595093 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 852595593 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 2359184 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1928197366 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1928199616 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer4.occupancy 85638132 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) |