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authorNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-01-24 12:29:00 -0600
commit9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b (patch)
tree64b85031cb791a21af6059778384d358d992b817 /tests/quick/fs/10.linux-boot
parentdbeabedaf0f8d9ec0ea3331db2e44b1add53f79f (diff)
downloadgem5-9bc132e4738c53be2dd9c2fdf5e4dd8e73d8970b.tar.xz
regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others the patch updates config.ini and name changes to statistical variables.
Diffstat (limited to 'tests/quick/fs/10.linux-boot')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini227
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout12
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini249
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout12
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt138
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini227
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout14
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini249
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout12
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt282
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini10
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt46
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini244
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr1
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt138
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini10
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt46
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini9
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt34
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini10
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini1
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout6
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt10
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini1
-rwxr-xr-xtests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout6
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt10
34 files changed, 1121 insertions, 963 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 9a2e4ebac..573c7933c 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -11,14 +11,16 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -34,22 +36,21 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -58,17 +59,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
@@ -81,21 +83,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@@ -110,21 +109,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@@ -133,6 +129,9 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=AlphaInterrupts
+[system.cpu0.isa]
+type=AlphaISA
+
[system.cpu0.itb]
type=AlphaTLB
size=48
@@ -142,11 +141,11 @@ type=ExeTracer
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -155,17 +154,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu1.tracer
width=1
@@ -178,21 +178,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@@ -207,21 +204,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@@ -230,6 +224,9 @@ mem_side=system.toL2Bus.slave[2]
[system.cpu1.interrupts]
type=AlphaInterrupts
+[system.cpu1.isa]
+type=AlphaISA
+
[system.cpu1.itb]
type=AlphaTLB
size=48
@@ -254,7 +251,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -274,7 +271,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -294,53 +291,47 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@@ -352,13 +343,14 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
@@ -371,14 +363,28 @@ warn_access=
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
@@ -390,7 +396,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -403,7 +409,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
@@ -418,10 +424,11 @@ system=system
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu0
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
@@ -429,8 +436,9 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
@@ -475,7 +483,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
@@ -486,12 +494,10 @@ dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
@@ -508,9 +514,10 @@ pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
@@ -524,9 +531,10 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -540,9 +548,10 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -556,9 +565,10 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -572,9 +582,10 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -588,9 +599,10 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -604,9 +616,10 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -620,9 +633,10 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -636,9 +650,10 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -652,9 +667,10 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -668,9 +684,10 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -684,9 +701,10 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -700,9 +718,10 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -716,9 +735,10 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -732,9 +752,10 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -748,9 +769,10 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -764,9 +786,10 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -780,9 +803,10 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -796,9 +820,10 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -812,9 +837,10 @@ pio=system.iobus.master[6]
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
@@ -858,16 +884,15 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
@@ -876,9 +901,10 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
@@ -887,8 +913,9 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
@@ -896,7 +923,8 @@ pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
@@ -904,8 +932,9 @@ pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index 9d0955474..a62617d01 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:40:04
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:01:11
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
-Exiting @ tick 1870335522500 because m5_exit instruction encountered
+Exiting @ tick 1870325497500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 0cbad844c..6b719babe 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.870325 # Nu
sim_ticks 1870325497500 # Number of ticks simulated
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1528286 # Simulator instruction rate (inst/s)
-host_op_rate 1528286 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45262701867 # Simulator tick rate (ticks/s)
-host_mem_usage 296828 # Number of bytes of host memory used
-host_seconds 41.32 # Real time elapsed on the host
+host_inst_rate 2356651 # Simulator instruction rate (inst/s)
+host_op_rate 2356650 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69796056257 # Simulator tick rate (ticks/s)
+host_mem_usage 349376 # Number of bytes of host memory used
+host_seconds 26.80 # Real time elapsed on the host
sim_insts 63151114 # Number of instructions simulated
sim_ops 63151114 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 29a31b8cf..50088b4ab 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -8,17 +8,19 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -34,22 +36,21 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -58,17 +59,18 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -81,25 +83,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
@@ -110,33 +109,65 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
[system.cpu.tracer]
type=ExeTracer
@@ -157,7 +188,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -177,7 +208,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -197,52 +228,24 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
@@ -255,13 +258,14 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
@@ -274,14 +278,28 @@ warn_access=
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
@@ -293,7 +311,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -303,16 +321,6 @@ number=0
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
@@ -321,10 +329,11 @@ system=system
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
@@ -332,8 +341,9 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
@@ -378,7 +388,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
@@ -389,12 +399,10 @@ dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
@@ -411,9 +419,10 @@ pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
@@ -427,9 +436,10 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -443,9 +453,10 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -459,9 +470,10 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -475,9 +487,10 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -491,9 +504,10 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -507,9 +521,10 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -523,9 +538,10 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -539,9 +555,10 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -555,9 +572,10 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -571,9 +589,10 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -587,9 +606,10 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -603,9 +623,10 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -619,9 +640,10 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -635,9 +657,10 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -651,9 +674,10 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -667,9 +691,10 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -683,9 +708,10 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -699,9 +725,10 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -715,9 +742,10 @@ pio=system.iobus.master[6]
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
@@ -761,16 +789,15 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
@@ -779,9 +806,10 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
@@ -790,8 +818,9 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
@@ -799,7 +828,8 @@ pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
@@ -807,8 +837,9 @@ pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index ed03a48be..c4aa2f920 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:39:53
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:01:49
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1829332258000 because m5_exit instruction encountered
+Exiting @ tick 1829330593000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index 99b74717c..2435d9264 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.829331 # Nu
sim_ticks 1829330593000 # Number of ticks simulated
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1577718 # Simulator instruction rate (inst/s)
-host_op_rate 1577717 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48072530632 # Simulator tick rate (ticks/s)
-host_mem_usage 294780 # Number of bytes of host memory used
-host_seconds 38.05 # Real time elapsed on the host
+host_inst_rate 1133415 # Simulator instruction rate (inst/s)
+host_op_rate 1133413 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34534714924 # Simulator tick rate (ticks/s)
+host_mem_usage 347332 # Number of bytes of host memory used
+host_seconds 52.97 # Real time elapsed on the host
sim_insts 60037737 # Number of instructions simulated
sim_ops 60037737 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
@@ -464,70 +464,6 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2042707 # number of replacements
-system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
-system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
-system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
-system.cpu.dcache.writebacks::total 833491 # number of writebacks
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 992297 # number of replacements
system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2433228 # Total number of references to valid blocks.
@@ -608,5 +544,69 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks
system.cpu.l2cache.writebacks::total 74287 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2042707 # number of replacements
+system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
+system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
+system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
+system.cpu.dcache.writebacks::total 833491 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index e9608d5ae..99e580564 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -11,14 +11,16 @@ type=LinuxAlphaSystem
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -34,22 +36,21 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -57,15 +58,16 @@ dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu0.tracer
workload=
@@ -77,21 +79,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
@@ -106,21 +105,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
@@ -129,6 +125,9 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.interrupts]
type=AlphaInterrupts
+[system.cpu0.isa]
+type=AlphaISA
+
[system.cpu0.itb]
type=AlphaTLB
size=48
@@ -138,11 +137,11 @@ type=ExeTracer
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -150,15 +149,16 @@ dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu1.tracer
workload=
@@ -170,21 +170,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
@@ -199,21 +196,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
@@ -222,6 +216,9 @@ mem_side=system.toL2Bus.slave[2]
[system.cpu1.interrupts]
type=AlphaInterrupts
+[system.cpu1.isa]
+type=AlphaISA
+
[system.cpu1.itb]
type=AlphaTLB
size=48
@@ -246,7 +243,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -266,7 +263,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -286,53 +283,47 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
@@ -344,13 +335,14 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
@@ -363,14 +355,28 @@ warn_access=
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
@@ -382,7 +388,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -395,7 +401,7 @@ port=3456
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
@@ -410,10 +416,11 @@ system=system
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu0
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
@@ -421,8 +428,9 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
@@ -467,7 +475,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
@@ -478,12 +486,10 @@ dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
@@ -500,9 +506,10 @@ pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
@@ -516,9 +523,10 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -532,9 +540,10 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -548,9 +557,10 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -564,9 +574,10 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -580,9 +591,10 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -596,9 +608,10 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -612,9 +625,10 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -628,9 +642,10 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -644,9 +659,10 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -660,9 +676,10 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -676,9 +693,10 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -692,9 +710,10 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -708,9 +727,10 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -724,9 +744,10 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -740,9 +761,10 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -756,9 +778,10 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -772,9 +795,10 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -788,9 +812,10 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -804,9 +829,10 @@ pio=system.iobus.master[6]
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
@@ -850,16 +876,15 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
@@ -868,9 +893,10 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
@@ -879,8 +905,9 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
@@ -888,7 +915,8 @@ pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
@@ -896,8 +924,9 @@ pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 3b87d756d..aa1334176 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:40:05
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:42
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 573593000
-Exiting @ tick 1954209529000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 608846000
+Exiting @ tick 1950813955500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index ab95e5b1c..0e2cc710f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.950814 # Nu
sim_ticks 1950813955500 # Number of ticks simulated
final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 770652 # Simulator instruction rate (inst/s)
-host_op_rate 770652 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24652738853 # Simulator tick rate (ticks/s)
-host_mem_usage 325660 # Number of bytes of host memory used
-host_seconds 79.13 # Real time elapsed on the host
+host_inst_rate 720692 # Simulator instruction rate (inst/s)
+host_op_rate 720692 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23054537293 # Simulator tick rate (ticks/s)
+host_mem_usage 378432 # Number of bytes of host memory used
+host_seconds 84.62 # Real time elapsed on the host
sim_insts 60983017 # Number of instructions simulated
sim_ops 60983017 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 734887994..d8f41ddb0 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -8,17 +8,19 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
@@ -34,22 +36,21 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -57,15 +58,16 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=
@@ -77,25 +79,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
@@ -106,33 +105,65 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
[system.cpu.tracer]
type=ExeTracer
@@ -153,7 +184,7 @@ table_size=65536
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -173,7 +204,7 @@ table_size=65536
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -193,52 +224,24 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
@@ -251,13 +254,14 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
@@ -270,14 +274,28 @@ warn_access=
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
@@ -289,7 +307,7 @@ system=system
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
@@ -299,16 +317,6 @@ number=0
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
@@ -317,10 +325,11 @@ system=system
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
@@ -328,8 +337,9 @@ pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
@@ -374,7 +384,7 @@ SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
@@ -385,12 +395,10 @@ dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
@@ -407,9 +415,10 @@ pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
@@ -423,9 +432,10 @@ pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -439,9 +449,10 @@ pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -455,9 +466,10 @@ pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -471,9 +483,10 @@ pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -487,9 +500,10 @@ pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -503,9 +517,10 @@ pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -519,9 +534,10 @@ pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -535,9 +551,10 @@ pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -551,9 +568,10 @@ pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -567,9 +585,10 @@ pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -583,9 +602,10 @@ pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -599,9 +619,10 @@ pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -615,9 +636,10 @@ pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -631,9 +653,10 @@ pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -647,9 +670,10 @@ pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -663,9 +687,10 @@ pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -679,9 +704,10 @@ pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -695,9 +721,10 @@ pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
@@ -711,9 +738,10 @@ pio=system.iobus.master[6]
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
@@ -757,16 +785,15 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
@@ -775,9 +802,10 @@ pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
@@ -786,8 +814,9 @@ pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
@@ -795,7 +824,8 @@ pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
@@ -803,8 +833,9 @@ pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index e4a5afde7..229260842 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:40:05
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:32:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1920853042000 because m5_exit instruction encountered
+Exiting @ tick 1910582068000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index dfbac48e1..e3ca77030 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.910582 # Nu
sim_ticks 1910582068000 # Number of ticks simulated
final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 942466 # Simulator instruction rate (inst/s)
-host_op_rate 942466 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32082735017 # Simulator tick rate (ticks/s)
-host_mem_usage 321492 # Number of bytes of host memory used
-host_seconds 59.55 # Real time elapsed on the host
+host_inst_rate 951839 # Simulator instruction rate (inst/s)
+host_op_rate 951839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32401800424 # Simulator tick rate (ticks/s)
+host_mem_usage 374212 # Number of bytes of host memory used
+host_seconds 58.97 # Real time elapsed on the host
sim_insts 56125446 # Number of instructions simulated
sim_ops 56125446 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
@@ -548,142 +548,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 11647.123628
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1389800 # number of replacements
-system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits
-system.cpu.dcache.overall_hits::total 13654126 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 17223 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1373108 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1373108 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1373108 # number of overall misses
-system.cpu.dcache.overall_misses::total 1373108 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 22711107000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 22711107000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8598536500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8598536500 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227697000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 227697000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 31309643500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 31309643500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 31309643500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 31309643500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 8875115 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 8875115 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6152119 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6152119 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15027234 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.091375 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.091375 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.091375 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.091375 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks
-system.cpu.dcache.writebacks::total 834403 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 336061 # number of replacements
system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2445310 # Total number of references to valid blocks.
@@ -854,5 +718,141 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1389800 # number of replacements
+system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits
+system.cpu.dcache.overall_hits::total 13654126 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 17223 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 1373108 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1373108 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1373108 # number of overall misses
+system.cpu.dcache.overall_misses::total 1373108 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 22711107000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 22711107000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8598536500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8598536500 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 227697000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 227697000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 31309643500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 31309643500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 31309643500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 31309643500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 8875115 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 8875115 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6152119 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6152119 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 15027234 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15027234 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15027234 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15027234 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120435 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.120435 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049452 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.049452 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086010 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086010 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.091375 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.091375 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.091375 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.091375 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21247.653610 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28263.090339 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22802.025405 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22802.025405 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22802.025405 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 834403 # number of writebacks
+system.cpu.dcache.writebacks::total 834403 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068876 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1068876 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304232 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 304232 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17223 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17223 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1373108 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1373108 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1373108 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1373108 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20573355000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 20573355000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7990072500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7990072500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193251000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193251000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28563427500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 28563427500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28563427500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 28563427500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2010997500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2010997500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435233500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435233500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120435 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120435 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049452 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049452 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086010 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086010 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.091375 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091375 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.091375 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19247.653610 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19247.653610 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26263.090339 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26263.090339 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11220.519073 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 9cf4fe14a..25f4e376e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -65,12 +65,13 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
@@ -197,6 +198,7 @@ type=ExeTracer
[system.cpu1]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index 4bb186944..c2890e671 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:29:32
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:45:38
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 912096763500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index 362d16758..5fe42fc21 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,31 +4,13 @@ sim_seconds 0.912097 # Nu
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 599236 # Simulator instruction rate (inst/s)
-host_op_rate 771515 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8869004975 # Simulator tick rate (ticks/s)
-host_mem_usage 384344 # Number of bytes of host memory used
-host_seconds 102.84 # Real time elapsed on the host
+host_inst_rate 1193297 # Simulator instruction rate (inst/s)
+host_op_rate 1536367 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17661410361 # Simulator tick rate (ticks/s)
+host_mem_usage 435356 # Number of bytes of host memory used
+host_seconds 51.64 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
@@ -242,6 +224,24 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 70658 # number of replacements
system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
system.l2c.total_refs 1623339 # Total number of references to valid blocks.
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 20da648f5..687db2fa1 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -8,22 +8,23 @@ time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
+mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
-midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -39,7 +40,7 @@ system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
@@ -64,16 +65,16 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -82,6 +83,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -92,6 +94,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -104,27 +107,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
@@ -134,41 +132,53 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -177,10 +187,42 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -201,56 +243,24 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-clock=1
-forward_snoops=true
-hash_delay=1
-hit_latency=10000
-is_top_level=false
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
@@ -263,11 +273,11 @@ use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
@@ -283,15 +293,28 @@ warn_access=warn
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
@@ -306,7 +329,7 @@ system=system
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
@@ -315,7 +338,7 @@ pio=system.membus.master[5]
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
@@ -362,7 +385,7 @@ SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
@@ -380,11 +403,12 @@ pio=system.iobus.master[7]
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@@ -393,7 +417,7 @@ pio=system.iobus.master[4]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
@@ -402,7 +426,7 @@ pio=system.iobus.master[9]
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
@@ -419,7 +443,7 @@ pio=system.iobus.master[24]
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
@@ -433,7 +457,7 @@ pio=system.membus.master[3]
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
@@ -443,7 +467,7 @@ pio=system.iobus.master[16]
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
@@ -453,7 +477,7 @@ pio=system.iobus.master[17]
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
@@ -463,7 +487,7 @@ pio=system.iobus.master[18]
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
@@ -477,7 +501,7 @@ pio=system.iobus.master[5]
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
@@ -490,7 +514,7 @@ pio=system.iobus.master[6]
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
@@ -519,7 +543,7 @@ pio=system.membus.master[6]
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
@@ -529,7 +553,7 @@ pio=system.iobus.master[22]
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
@@ -541,7 +565,7 @@ port=system.membus.master[1]
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
@@ -553,7 +577,7 @@ pio=system.iobus.master[1]
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
@@ -566,7 +590,7 @@ pio=system.iobus.master[23]
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
@@ -576,7 +600,7 @@ pio=system.iobus.master[20]
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
@@ -586,7 +610,7 @@ pio=system.iobus.master[13]
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
@@ -596,7 +620,7 @@ pio=system.iobus.master[14]
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
@@ -606,7 +630,7 @@ pio=system.iobus.master[19]
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -620,7 +644,7 @@ pio=system.iobus.master[2]
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
@@ -633,7 +657,7 @@ pio=system.iobus.master[3]
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
@@ -648,7 +672,7 @@ pio=system.iobus.master[0]
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
@@ -658,7 +682,7 @@ pio=system.iobus.master[10]
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
@@ -668,7 +692,7 @@ pio=system.iobus.master[11]
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
@@ -678,7 +702,7 @@ pio=system.iobus.master[12]
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
@@ -692,16 +716,6 @@ number=0
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
[system.vncserver]
type=VncServer
frame_capture=false
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index 9a28ceb37..3ee89fc27 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
@@ -11,7 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index 2d2abdc83..ec6b1ae21 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:18
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:44:32
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2332810264000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index ccb9a5402..bc1e2b029 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1184768 # Simulator instruction rate (inst/s)
-host_op_rate 1523538 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45752340761 # Simulator tick rate (ticks/s)
-host_mem_usage 382236 # Number of bytes of host memory used
-host_seconds 50.99 # Real time elapsed on the host
+host_inst_rate 1101050 # Simulator instruction rate (inst/s)
+host_op_rate 1415882 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42519386287 # Simulator tick rate (ticks/s)
+host_mem_usage 435224 # Number of bytes of host memory used
+host_seconds 54.86 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
@@ -333,70 +333,6 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 623337 # number of replacements
-system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
-system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
-system.cpu.dcache.overall_misses::total 615611 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
-system.cpu.dcache.writebacks::total 592643 # number of writebacks
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 62243 # number of replacements
system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks.
@@ -505,6 +441,70 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 623337 # number of replacements
+system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
+system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
+system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
+system.cpu.dcache.overall_misses::total 615611 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
+system.cpu.dcache.writebacks::total 592643 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 8e8c112af..88cdb89c6 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -65,12 +65,13 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
@@ -193,6 +194,7 @@ type=ExeTracer
[system.cpu1]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index cecfd8ad7..97bbe0010 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:31:36
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:46:40
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1182882156500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
index b637311d9..ebe1b98fa 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
@@ -4,31 +4,13 @@ sim_seconds 1.182882 # Nu
sim_ticks 1182882156500 # Number of ticks simulated
final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184229 # Simulator instruction rate (inst/s)
-host_op_rate 234741 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3546252898 # Simulator tick rate (ticks/s)
-host_mem_usage 402168 # Number of bytes of host memory used
-host_seconds 333.56 # Real time elapsed on the host
+host_inst_rate 497131 # Simulator instruction rate (inst/s)
+host_op_rate 633435 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9569364300 # Simulator tick rate (ticks/s)
+host_mem_usage 452888 # Number of bytes of host memory used
+host_seconds 123.61 # Real time elapsed on the host
sim_insts 61450993 # Number of instructions simulated
sim_ops 78299715 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
@@ -242,6 +224,24 @@ system.physmem.writeRowHits 789308 # Nu
system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes
system.physmem.avgGap 158232.25 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 69442 # number of replacements
system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use
system.l2c.total_refs 1672967 # Total number of references to valid blocks.
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index eecdc36d4..f1513514e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
@@ -65,12 +65,13 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index fedaf9185..a83c8cf44 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:31:27
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:45:50
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2603634694000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
index fcb402e49..b72126c20 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
@@ -4,25 +4,13 @@ sim_seconds 2.603635 # Nu
sim_ticks 2603634694000 # Number of ticks simulated
final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 156094 # Simulator instruction rate (inst/s)
-host_op_rate 198627 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6751306864 # Simulator tick rate (ticks/s)
-host_mem_usage 397752 # Number of bytes of host memory used
-host_seconds 385.65 # Real time elapsed on the host
+host_inst_rate 413538 # Simulator instruction rate (inst/s)
+host_op_rate 526220 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17886148072 # Simulator tick rate (ticks/s)
+host_mem_usage 448796 # Number of bytes of host memory used
+host_seconds 145.57 # Real time elapsed on the host
sim_insts 60197457 # Number of instructions simulated
sim_ops 76600355 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
@@ -219,6 +207,18 @@ system.physmem.writeRowHits 785061 # Nu
system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes
system.physmem.avgGap 159677.30 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index a1eb19238..e3b4a020a 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
@@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
@@ -27,8 +27,6 @@ mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
@@ -67,12 +65,13 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
@@ -199,6 +198,7 @@ type=ExeTracer
[system.cpu1]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
index 19928f0ac..ac14d4997 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 11 2012 16:28:23
-gem5 started Dec 11 2012 16:28:36
-gem5 executing on e103721-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:48:26
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
index d4e639ad7..21a80bd51 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu
sim_ticks 2332810256000 # Number of ticks simulated
final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 669803 # Simulator instruction rate (inst/s)
-host_op_rate 861325 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25865872844 # Simulator tick rate (ticks/s)
-host_mem_usage 384756 # Number of bytes of host memory used
-host_seconds 90.19 # Real time elapsed on the host
+host_inst_rate 1011951 # Simulator instruction rate (inst/s)
+host_op_rate 1301307 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39078665084 # Simulator tick rate (ticks/s)
+host_mem_usage 435224 # Number of bytes of host memory used
+host_seconds 59.70 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 12b6dc7b6..527c82daf 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -74,6 +74,7 @@ slave=system.membus.master[1]
[system.cpu]
type=AtomicSimpleCPU
children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index c9e113bf6..c7231a234 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:32:27
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
warning: add_child('terminal'): child 'terminal' already has parent
@@ -12,4 +12,4 @@ Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112043255000 because m5_exit instruction encountered
+Exiting @ tick 5112040970500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
index 4d2d6b5c4..175418c2b 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.112041 # Nu
sim_ticks 5112040970500 # Number of ticks simulated
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1661898 # Simulator instruction rate (inst/s)
-host_op_rate 3402855 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42518772648 # Simulator tick rate (ticks/s)
-host_mem_usage 621064 # Number of bytes of host memory used
-host_seconds 120.23 # Real time elapsed on the host
+host_inst_rate 1071475 # Simulator instruction rate (inst/s)
+host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27413112180 # Simulator tick rate (ticks/s)
+host_mem_usage 626876 # Number of bytes of host memory used
+host_seconds 186.48 # Real time elapsed on the host
sim_insts 199810242 # Number of instructions simulated
sim_ops 409125923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 378234e02..f5bfaf68d 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -74,6 +74,7 @@ slave=system.membus.master[1]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index 954f254a4..0439ed364 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:02:27
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
warning: add_child('terminal'): child 'terminal' already has parent
@@ -12,4 +12,4 @@ Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5196043137000 because m5_exit instruction encountered
+Exiting @ tick 5191112864000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 5586ee7f0..5387a3a4f 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.191113 # Nu
sim_ticks 5191112864000 # Number of ticks simulated
final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1076481 # Simulator instruction rate (inst/s)
-host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43574012985 # Simulator tick rate (ticks/s)
-host_mem_usage 651144 # Number of bytes of host memory used
-host_seconds 119.13 # Real time elapsed on the host
+host_inst_rate 663100 # Simulator instruction rate (inst/s)
+host_op_rate 1278245 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26841102406 # Simulator tick rate (ticks/s)
+host_mem_usage 658020 # Number of bytes of host memory used
+host_seconds 193.40 # Real time elapsed on the host
sim_insts 128244620 # Number of instructions simulated
sim_ops 247214608 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory