diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/quick/fs | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/quick/fs')
12 files changed, 5677 insertions, 4959 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 349090c6e..44f9ef01c 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3158607 # Simulator instruction rate (inst/s) -host_op_rate 3158605 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93543458564 # Simulator tick rate (ticks/s) -host_mem_usage 309852 # Number of bytes of host memory used -host_seconds 19.99 # Real time elapsed on the host +host_inst_rate 2258331 # Simulator instruction rate (inst/s) +host_op_rate 2258329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66881420828 # Simulator tick rate (ticks/s) +host_mem_usage 346748 # Number of bytes of host memory used +host_seconds 27.97 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -307,6 +307,41 @@ system.cpu0.num_busy_cycles 57233845.415270 # system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles system.cpu0.Branches 8650704 # Number of branches fetched +system.cpu0.op_class::No_OpClass 3102513 5.42% 5.42% # Class of executed instruction +system.cpu0.op_class::IntAlu 37823162 66.09% 71.51% # Class of executed instruction +system.cpu0.op_class::IntMult 59490 0.10% 71.61% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 18488 0.03% 71.65% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction +system.cpu0.op_class::MemRead 9401052 16.43% 88.08% # Class of executed instruction +system.cpu0.op_class::MemWrite 5956984 10.41% 98.49% # Class of executed instruction +system.cpu0.op_class::IprAccess 866222 1.51% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 57230132 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed @@ -612,6 +647,41 @@ system.cpu1.num_busy_cycles 5936690.922345 # system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles system.cpu1.Branches 836747 # Number of branches fetched +system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 3533366 59.53% 63.57% # Class of executed instruction +system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction +system.cpu1.op_class::FloatAdd 7265 0.12% 63.85% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction +system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction +system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction +system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 5935766 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index b2c0b7d09..d987ad3fa 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3003513 # Simulator instruction rate (inst/s) -host_op_rate 3003511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91515177007 # Simulator tick rate (ticks/s) -host_mem_usage 306744 # Number of bytes of host memory used -host_seconds 19.99 # Real time elapsed on the host +host_inst_rate 2367650 # Simulator instruction rate (inst/s) +host_op_rate 2367648 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72140813877 # Simulator tick rate (ticks/s) +host_mem_usage 343680 # Number of bytes of host memory used +host_seconds 25.36 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -160,6 +160,41 @@ system.cpu.num_busy_cycles 60055430.608382 # system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983585 # Percentage of idle cycles system.cpu.Branches 9064385 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199104 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39460699 65.71% 71.04% # Class of executed instruction +system.cpu.op_class::IntMult 60680 0.10% 71.14% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 71.14% # Class of executed instruction +system.cpu.op_class::FloatAdd 25609 0.04% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction +system.cpu.op_class::MemRead 9975081 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 60050143 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 85845c2fe..a1c48ce35 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.961814 # Number of seconds simulated -sim_ticks 1961813569500 # Number of ticks simulated -final_tick 1961813569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962822 # Number of seconds simulated +sim_ticks 1962822184500 # Number of ticks simulated +final_tick 1962822184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1769979 # Simulator instruction rate (inst/s) -host_op_rate 1769979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57024152249 # Simulator tick rate (ticks/s) -host_mem_usage 311592 # Number of bytes of host memory used -host_seconds 34.40 # Real time elapsed on the host -sim_insts 60892925 # Number of instructions simulated -sim_ops 60892925 # Number of ops (including micro ops) simulated +host_inst_rate 916137 # Simulator instruction rate (inst/s) +host_op_rate 916137 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30287148246 # Simulator tick rate (ticks/s) +host_mem_usage 346744 # Number of bytes of host memory used +host_seconds 64.81 # Real time elapsed on the host +sim_insts 59372170 # Number of instructions simulated +sim_ops 59372170 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 833088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24884096 # Number of bytes read from this memory -system.physmem.bytes_read::tsunami.ide 2650880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 337152 # Number of bytes read from this memory -system.physmem.bytes_read::total 28737152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 833088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7735232 # Number of bytes written to this memory -system.physmem.bytes_written::total 7735232 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388814 # Number of read requests responded to by this memory -system.physmem.num_reads::tsunami.ide 41420 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 5268 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449018 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 120863 # Number of write requests responded to by this memory -system.physmem.num_writes::total 120863 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 424652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12684231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1351240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 16279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 171857 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14648258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 424652 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 16279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440931 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3942899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3942899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3942899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 424652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12684231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1351240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 16279 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 171857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0.inst 724800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24150336 # Number of bytes read from this memory +system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 138496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1080640 # Number of bytes read from this memory +system.physmem.bytes_read::total 28743616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 724800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 138496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 863296 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7747520 # Number of bytes written to this memory +system.physmem.bytes_written::total 7747520 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 377349 # Number of read requests responded to by this memory +system.physmem.num_reads::tsunami.ide 41396 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16885 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449119 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 121055 # Number of write requests responded to by this memory +system.physmem.num_writes::total 121055 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 369264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12303884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1349763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 550554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14644024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 369264 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 439824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3947133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3947133 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3947133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 369264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12303884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1349763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 550554 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18591157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 449018 # Number of read requests accepted -system.physmem.writeReqs 120863 # Number of write requests accepted -system.physmem.readBursts 449018 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 120863 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28729600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue -system.physmem.bytesWritten 7733952 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28737152 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7735232 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.readReqs 449119 # Number of read requests accepted +system.physmem.writeReqs 121055 # Number of write requests accepted +system.physmem.readBursts 449119 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 121055 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28736320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7296 # Total number of bytes read from write queue +system.physmem.bytesWritten 7746176 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28743616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7747520 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 114 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 6983 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 28166 # Per bank write bursts -system.physmem.perBankRdBursts::1 28350 # Per bank write bursts -system.physmem.perBankRdBursts::2 28054 # Per bank write bursts -system.physmem.perBankRdBursts::3 27500 # Per bank write bursts -system.physmem.perBankRdBursts::4 27615 # Per bank write bursts -system.physmem.perBankRdBursts::5 27605 # Per bank write bursts -system.physmem.perBankRdBursts::6 28127 # Per bank write bursts -system.physmem.perBankRdBursts::7 27851 # Per bank write bursts -system.physmem.perBankRdBursts::8 28176 # Per bank write bursts -system.physmem.perBankRdBursts::9 27723 # Per bank write bursts -system.physmem.perBankRdBursts::10 27750 # Per bank write bursts -system.physmem.perBankRdBursts::11 28018 # Per bank write bursts -system.physmem.perBankRdBursts::12 28330 # Per bank write bursts -system.physmem.perBankRdBursts::13 28694 # Per bank write bursts -system.physmem.perBankRdBursts::14 28891 # Per bank write bursts -system.physmem.perBankRdBursts::15 28050 # Per bank write bursts -system.physmem.perBankWrBursts::0 7929 # Per bank write bursts -system.physmem.perBankWrBursts::1 7797 # Per bank write bursts -system.physmem.perBankWrBursts::2 7545 # Per bank write bursts -system.physmem.perBankWrBursts::3 7029 # Per bank write bursts -system.physmem.perBankWrBursts::4 7135 # Per bank write bursts -system.physmem.perBankWrBursts::5 7129 # Per bank write bursts -system.physmem.perBankWrBursts::6 7643 # Per bank write bursts -system.physmem.perBankWrBursts::7 7252 # Per bank write bursts -system.physmem.perBankWrBursts::8 7395 # Per bank write bursts -system.physmem.perBankWrBursts::9 7084 # Per bank write bursts -system.physmem.perBankWrBursts::10 7104 # Per bank write bursts -system.physmem.perBankWrBursts::11 7401 # Per bank write bursts -system.physmem.perBankWrBursts::12 7833 # Per bank write bursts -system.physmem.perBankWrBursts::13 8315 # Per bank write bursts -system.physmem.perBankWrBursts::14 8551 # Per bank write bursts -system.physmem.perBankWrBursts::15 7701 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 28065 # Per bank write bursts +system.physmem.perBankRdBursts::1 28141 # Per bank write bursts +system.physmem.perBankRdBursts::2 27986 # Per bank write bursts +system.physmem.perBankRdBursts::3 28553 # Per bank write bursts +system.physmem.perBankRdBursts::4 28160 # Per bank write bursts +system.physmem.perBankRdBursts::5 27775 # Per bank write bursts +system.physmem.perBankRdBursts::6 27616 # Per bank write bursts +system.physmem.perBankRdBursts::7 27528 # Per bank write bursts +system.physmem.perBankRdBursts::8 27559 # Per bank write bursts +system.physmem.perBankRdBursts::9 27974 # Per bank write bursts +system.physmem.perBankRdBursts::10 27981 # Per bank write bursts +system.physmem.perBankRdBursts::11 28021 # Per bank write bursts +system.physmem.perBankRdBursts::12 28612 # Per bank write bursts +system.physmem.perBankRdBursts::13 28738 # Per bank write bursts +system.physmem.perBankRdBursts::14 28459 # Per bank write bursts +system.physmem.perBankRdBursts::15 27837 # Per bank write bursts +system.physmem.perBankWrBursts::0 7862 # Per bank write bursts +system.physmem.perBankWrBursts::1 7636 # Per bank write bursts +system.physmem.perBankWrBursts::2 7481 # Per bank write bursts +system.physmem.perBankWrBursts::3 8065 # Per bank write bursts +system.physmem.perBankWrBursts::4 7619 # Per bank write bursts +system.physmem.perBankWrBursts::5 7244 # Per bank write bursts +system.physmem.perBankWrBursts::6 7159 # Per bank write bursts +system.physmem.perBankWrBursts::7 6941 # Per bank write bursts +system.physmem.perBankWrBursts::8 6882 # Per bank write bursts +system.physmem.perBankWrBursts::9 7297 # Per bank write bursts +system.physmem.perBankWrBursts::10 7427 # Per bank write bursts +system.physmem.perBankWrBursts::11 7400 # Per bank write bursts +system.physmem.perBankWrBursts::12 8124 # Per bank write bursts +system.physmem.perBankWrBursts::13 8265 # Per bank write bursts +system.physmem.perBankWrBursts::14 8168 # Per bank write bursts +system.physmem.perBankWrBursts::15 7464 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 12 # Number of times write queue was full causing retry -system.physmem.totGap 1961806557500 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1962815073500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 449018 # Read request sizes (log2) +system.physmem.readPktSize::6 449119 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 120863 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407987 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1708 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1160 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3779 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3964 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1914 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1527 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see +system.physmem.writePktSize::6 121055 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1995 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3971 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1613 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1890 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2087 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 975 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -158,355 +158,356 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4812 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1045 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 30 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48187 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 641.951066 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 418.430190 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 422.843508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8213 17.04% 17.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7073 14.68% 31.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2891 6.00% 37.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1720 3.57% 41.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1328 2.76% 44.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 906 1.88% 45.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 669 1.39% 47.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 536 1.11% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24851 51.57% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48187 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6896 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 65.095418 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2542.617511 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6893 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6896 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6896 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.523637 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.253710 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.981541 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4466 64.76% 64.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 342 4.96% 69.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 377 5.47% 75.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1323 19.19% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 32 0.46% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.23% 95.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.17% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 22 0.32% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 43 0.62% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 30 0.44% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 27 0.39% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 32 0.46% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 29 0.42% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 31 0.45% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 6 0.09% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 8 0.12% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 10 0.15% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.04% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 4 0.06% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 4 0.06% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 3 0.04% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 3 0.04% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 5 0.07% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.04% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 2 0.03% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 2 0.03% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 3 0.04% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 3 0.04% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 6 0.09% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 12 0.17% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 5 0.07% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 7 0.10% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 3 0.04% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 5 0.07% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 6 0.09% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 1425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 879 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 68642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.489409 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 323.678439 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.279001 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15609 22.74% 22.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11929 17.38% 40.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5150 7.50% 47.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3087 4.50% 52.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3390 4.94% 57.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1779 2.59% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1473 2.15% 61.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1315 1.92% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24910 36.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 68642 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7087 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 63.355581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1920.089024 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 7082 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 1 0.01% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-45055 1 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::73728-77823 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::122880-126975 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7087 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.078312 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.846071 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.814192 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5314 74.98% 74.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 115 1.62% 76.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1264 17.84% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 37 0.52% 94.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 12 0.17% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 12 0.17% 95.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 26 0.37% 95.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 96 1.35% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 18 0.25% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 39 0.55% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 16 0.23% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 10 0.14% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 12 0.17% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 8 0.11% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.06% 98.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 15 0.21% 98.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 3 0.04% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 4 0.06% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 2 0.03% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.01% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 3 0.04% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 2 0.03% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 10 0.14% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 6 0.08% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 6 0.08% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 2 0.03% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 4 0.06% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 10 0.14% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.03% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::55 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 9 0.13% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 14 0.20% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::58 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6896 # Writes before turning the bus around for reads -system.physmem.totQLat 7845433250 # Total ticks spent queuing -system.physmem.totMemAccLat 16453873250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2244500000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6363940000 # Total ticks spent accessing banks -system.physmem.avgQLat 17477.02 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14176.74 # Average bank access latency per DRAM burst +system.physmem.wrPerTurnAround::total 7087 # Writes before turning the bus around for reads +system.physmem.totQLat 7297703000 # Total ticks spent queuing +system.physmem.totMemAccLat 15716546750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2245025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16253.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36653.76 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35003.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 14.64 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.52 # Average write queue length when enqueuing -system.physmem.readRowHits 403422 # Number of row buffer hits during reads -system.physmem.writeRowHits 97436 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.62 # Row buffer hit rate for writes -system.physmem.avgGap 3442484.58 # Average gap between requests -system.physmem.pageHitRate 87.91 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.55 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18651494 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292756 # Transaction distribution -system.membus.trans_dist::ReadResp 292756 # Transaction distribution -system.membus.trans_dist::WriteReq 14067 # Transaction distribution -system.membus.trans_dist::WriteResp 14067 # Transaction distribution -system.membus.trans_dist::Writeback 120863 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16150 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11271 # Transaction distribution -system.membus.trans_dist::UpgradeResp 6986 # Transaction distribution -system.membus.trans_dist::ReadExReq 164854 # Transaction distribution -system.membus.trans_dist::ReadExResp 164030 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930030 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 972562 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124666 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1097228 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31164224 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31246178 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5308160 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 36554338 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 36554338 # Total data (bytes) -system.membus.snoop_data_through_bus 36416 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 43154000 # Layer occupancy (ticks) +system.physmem.avgWrQLen 25.12 # Average write queue length when enqueuing +system.physmem.readRowHits 403892 # Number of row buffer hits during reads +system.physmem.writeRowHits 97505 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.95 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.55 # Row buffer hit rate for writes +system.physmem.avgGap 3442484.35 # Average gap between requests +system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840580762750 # Time in different power states +system.physmem.memoryStateTime::REF 65542880000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 56696821000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 18645480 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292657 # Transaction distribution +system.membus.trans_dist::ReadResp 292657 # Transaction distribution +system.membus.trans_dist::WriteReq 12414 # Transaction distribution +system.membus.trans_dist::WriteResp 12414 # Transaction distribution +system.membus.trans_dist::Writeback 121055 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4555 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1018 # Transaction distribution +system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution +system.membus.trans_dist::ReadExReq 164356 # Transaction distribution +system.membus.trans_dist::ReadExResp 164254 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 943501 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1068148 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31184320 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 31253058 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5306816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5306816 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 36559874 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 36559874 # Total data (bytes) +system.membus.snoop_data_through_bus 37888 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 39221000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1578633000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1574833000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3834132000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3826410374 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376702000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376647250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342098 # number of replacements -system.l2c.tags.tagsinuse 65220.106735 # Cycle average of tags in use -system.l2c.tags.total_refs 2445213 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407285 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.003690 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8658635750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55273.758884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4807.212496 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4935.163888 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 160.761256 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 43.210211 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843411 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073352 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075305 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002453 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000659 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995180 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65187 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 784 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7171 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51861 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994675 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25954090 # Number of tag accesses -system.l2c.tags.data_accesses 25954090 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 690864 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668298 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 311515 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 104210 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774887 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 792911 # number of Writeback hits -system.l2c.Writeback_hits::total 792911 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 184 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 529 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 713 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 40 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 64 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 130516 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42247 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172763 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 690864 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 798814 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 311515 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 146457 # number of demand (read+write) hits -system.l2c.demand_hits::total 1947650 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 690864 # number of overall hits -system.l2c.overall_hits::cpu0.data 798814 # number of overall hits -system.l2c.overall_hits::cpu1.inst 311515 # number of overall hits -system.l2c.overall_hits::cpu1.data 146457 # number of overall hits -system.l2c.overall_hits::total 1947650 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13020 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271630 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 507 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 237 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285394 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2952 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1737 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4689 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 888 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 909 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1797 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117936 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5042 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 122978 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13020 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389566 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 507 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 5279 # number of demand (read+write) misses -system.l2c.demand_misses::total 408372 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13020 # number of overall misses -system.l2c.overall_misses::cpu0.data 389566 # number of overall misses -system.l2c.overall_misses::cpu1.inst 507 # number of overall misses -system.l2c.overall_misses::cpu1.data 5279 # number of overall misses -system.l2c.overall_misses::total 408372 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 958908741 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17698605243 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 37880750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 17386000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18712780734 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1103962 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 9942571 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11046533 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 835964 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 161993 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 997957 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8071982510 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 364247989 # 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number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 703884 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 939928 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 312022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 104447 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2060281 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 792911 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 792911 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3136 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2266 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5402 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 928 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 933 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60839.625077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53504.540544 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61323.243993 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60715.816579 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54048.159692 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -641,44 +642,44 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41694 # number of replacements -system.iocache.tags.tagsinuse 0.569649 # Cycle average of tags in use +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.570023 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755503918000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.569649 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035603 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035603 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756486423000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.570023 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035626 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035626 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375534 # Number of tag accesses -system.iocache.tags.data_accesses 375534 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses -system.iocache.ReadReq_misses::total 174 # number of ReadReq misses +system.iocache.tags.tag_accesses 375552 # Number of tag accesses +system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses +system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses -system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses -system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21248883 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21248883 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13129991411 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13129991411 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13151240294 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13151240294 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13151240294 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13151240294 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 41728 # number of demand (read+write) misses +system.iocache.demand_misses::total 41728 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 41728 # number of overall misses +system.iocache.overall_misses::total 41728 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21474883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21474883 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12370994210 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12370994210 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12392469093 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12392469093 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12392469093 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12392469093 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41728 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 41728 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41728 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 41728 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses @@ -687,40 +688,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122120.017241 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122120.017241 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 315989.396684 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 315989.396684 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 315180.949384 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 315180.949384 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 315180.949384 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 388544 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122016.380682 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122016.380682 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 297723.195273 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 297723.195273 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 296982.100580 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 296982.100580 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 296982.100580 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 362942 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28481 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28216 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.642218 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.862986 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 41520 # number of writebacks -system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 41523 # number of writebacks +system.iocache.writebacks::total 41523 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199883 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12199883 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10966952411 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10966952411 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10979152294 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10979152294 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10979152294 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10979152294 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 41728 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41728 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41728 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12321883 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10208100710 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10208100710 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10220422593 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10220422593 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10220422593 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10220422593 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -729,14 +730,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70114.270115 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70114.270115 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 263933.202036 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 263933.202036 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263124.965106 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 263124.965106 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70010.698864 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70010.698864 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 245670.502262 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 245670.502262 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 244929.605852 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 244929.605852 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -754,22 +755,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7562587 # DTB read hits +system.cpu0.dtb.read_hits 6067358 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5147352 # DTB write hits +system.cpu0.dtb.write_hits 4265662 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12709939 # DTB hits +system.cpu0.dtb.data_hits 10333020 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3660806 # ITB hits +system.cpu0.itb.fetch_hits 3354842 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3664790 # ITB accesses +system.cpu0.itb.fetch_accesses 3358826 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -782,56 +783,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3923627139 # number of cpu cycles simulated +system.cpu0.numCycles 3925644369 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 48127942 # Number of instructions committed -system.cpu0.committedOps 48127942 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44644072 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 213646 # Number of float alu accesses -system.cpu0.num_func_calls 1209779 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5646914 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44644072 # number of integer instructions -system.cpu0.num_fp_insts 213646 # number of float instructions -system.cpu0.num_int_register_reads 61387929 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33243119 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 104403 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 106204 # number of times the floating registers were written -system.cpu0.num_mem_refs 12751056 # number of memory refs -system.cpu0.num_load_insts 7590434 # Number of load instructions -system.cpu0.num_store_insts 5160622 # Number of store instructions -system.cpu0.num_idle_cycles 3699531471.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 224095667.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.057114 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.942886 # Percentage of idle cycles -system.cpu0.Branches 7246727 # Number of branches fetched +system.cpu0.committedInsts 38276564 # Number of instructions committed +system.cpu0.committedOps 38276564 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 35596868 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 153627 # Number of float alu accesses +system.cpu0.num_func_calls 936507 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4464991 # number of instructions that are conditional controls +system.cpu0.num_int_insts 35596868 # number of integer instructions +system.cpu0.num_fp_insts 153627 # number of float instructions +system.cpu0.num_int_register_reads 48919002 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26532177 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 75066 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 75978 # number of times the floating registers were written +system.cpu0.num_mem_refs 10366198 # number of memory refs +system.cpu0.num_load_insts 6090760 # Number of load instructions +system.cpu0.num_store_insts 4275438 # Number of store instructions +system.cpu0.num_idle_cycles 3742234246.498094 # Number of idle cycles +system.cpu0.num_busy_cycles 183410122.501907 # Number of busy cycles +system.cpu0.not_idle_fraction 0.046721 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.953279 # Percentage of idle cycles +system.cpu0.Branches 5694814 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2096369 5.48% 5.48% # Class of executed instruction +system.cpu0.op_class::IntAlu 24995370 65.29% 70.76% # Class of executed instruction +system.cpu0.op_class::IntMult 39322 0.10% 70.86% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 70.86% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12602 0.03% 70.90% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction +system.cpu0.op_class::MemRead 6233117 16.28% 87.18% # Class of executed instruction +system.cpu0.op_class::MemWrite 4280683 11.18% 98.36% # Class of executed instruction +system.cpu0.op_class::IprAccess 626236 1.64% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 38285582 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6803 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 166332 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 57240 40.25% 40.25% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1974 1.39% 41.73% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82451 57.97% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 142220 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56707 49.09% 49.09% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1974 1.71% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1902164041000 96.96% 96.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95225000 0.00% 96.96% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 767277500 0.04% 97.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314374500 0.02% 97.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58471894000 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1961812812000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 4866 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 138364 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 44810 38.76% 38.76% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 68668 59.40% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 115600 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 44285 48.84% 48.84% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 44269 48.82% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 90676 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1909704051500 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94854000 0.00% 97.30% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 764030500 0.04% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 52245891000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1962821412500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988284 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682624 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.812256 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.644682 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -863,37 +899,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3107 2.06% 2.40% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed -system.cpu0.kern.callpal::swpipl 135267 89.81% 92.25% # number of callpals executed -system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 150615 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7022 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches +system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2218 1.80% 1.88% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed +system.cpu0.kern.callpal::swpipl 109461 88.95% 90.88% # number of callpals executed +system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed +system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 123054 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 5726 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1371 -system.cpu0.kern.mode_good::user 1372 +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195244 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.239260 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.326781 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1958041026500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3771781000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.386220 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1959031016000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3790392000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3108 # number of times the context was actually changed +system.cpu0.kern.swap_context 2219 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -925,48 +961,48 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 103965077 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2102306 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2102291 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 792911 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16363 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11335 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 27698 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 339143 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 297593 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407788 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624045 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452421 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5619111 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45048576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120057312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19969408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16548674 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 201623970 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 201613666 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2346432 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4795947858 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.throughput 108070579 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2148343 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2148328 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 850135 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 4614 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1062 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 5676 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 363639 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 322090 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078600 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181406 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927231 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598323 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5785560 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34514560 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81611821 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29671360 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63815893 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 209613634 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 209603138 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 2520192 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 5075991989 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3170057255 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5536383084 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1404201241 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2429088500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 4030648808 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 2086694241 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 776393157 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1398487 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7373 # Transaction distribution -system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55619 # Transaction distribution -system.iobus.trans_dist::WriteResp 55619 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 2646669064 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) +system.iobus.throughput 1391043 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7376 # Transaction distribution +system.iobus.trans_dist::ReadResp 7376 # Transaction distribution +system.iobus.trans_dist::WriteReq 53966 # Transaction distribution +system.iobus.trans_dist::WriteResp 53966 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -977,12 +1013,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 39228 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 122684 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1936 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -993,14 +1029,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2743570 # Total data (bytes) -system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 68738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 2730370 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2730370 # Total data (bytes) +system.iobus.reqLayer0.occupancy 9969000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 362000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1020,67 +1056,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380082294 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380139843 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43185000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43231750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 703274 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.380970 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47433057 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 703786 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.396989 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40278267250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.380970 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992932 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992932 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 538677 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.393435 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37746273 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 539189 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.005644 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393435 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48840865 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48840865 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47433057 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47433057 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47433057 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47433057 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47433057 # number of overall hits -system.cpu0.icache.overall_hits::total 47433057 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 703904 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 703904 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 703904 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 703904 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 703904 # number of overall misses -system.cpu0.icache.overall_misses::total 703904 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10025783755 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10025783755 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10025783755 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10025783755 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10025783755 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10025783755 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136961 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 48136961 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 48136961 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 48136961 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 48136961 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 48136961 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014623 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014623 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014623 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014623 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014623 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014623 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14243.112349 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14243.112349 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14243.112349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14243.112349 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14243.112349 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 38824893 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 38824893 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37746273 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37746273 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37746273 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37746273 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37746273 # number of overall hits +system.cpu0.icache.overall_hits::total 37746273 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 539310 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 539310 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 539310 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 539310 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 539310 # number of overall misses +system.cpu0.icache.overall_misses::total 539310 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7764312000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7764312000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7764312000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7764312000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7764312000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7764312000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285583 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38285583 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38285583 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38285583 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38285583 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38285583 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014087 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014087 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014087 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014087 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014087 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014087 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14396.751405 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14396.751405 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14396.751405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14396.751405 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14396.751405 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1089,119 +1125,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703904 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 703904 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 703904 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 703904 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 703904 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 703904 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8612997245 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8612997245 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8612997245 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8612997245 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8612997245 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8612997245 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014623 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014623 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014623 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014623 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12236.039638 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12236.039638 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12236.039638 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539310 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 539310 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 539310 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 539310 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 539310 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 539310 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6681305000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6681305000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6681305000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6681305000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6681305000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6681305000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014087 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014087 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014087 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12388.616936 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12388.616936 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12388.616936 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12388.616936 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1191290 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.228160 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11513399 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1191802 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.660496 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 108508250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.228160 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986774 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986774 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 871224 # number of replacements +system.cpu0.dcache.tags.tagsinuse 481.747613 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9466123 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 871736 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.858933 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.747613 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940913 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.940913 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 52084916 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 52084916 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6477391 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6477391 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4731575 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4731575 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141550 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 141550 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149263 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149263 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11208966 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11208966 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11208966 # number of overall hits -system.cpu0.dcache.overall_hits::total 11208966 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942691 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942691 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 258024 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 258024 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13717 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13717 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1200715 # 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miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035239 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035239 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096756 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.096756 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096756 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.096756 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28917.196894 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28917.196894 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39851.835252 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39851.835252 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11000.328060 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11000.328060 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7701.648569 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7701.648569 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31266.962765 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31266.962765 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31266.962765 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 42234072 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 42234072 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5299987 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5299987 # 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miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086302 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36220.715211 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 36220.715211 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41312.247353 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41312.247353 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13136.697306 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13136.697306 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7206.185859 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7206.185859 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37533.515459 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37533.515459 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37533.515459 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37533.515459 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1210,62 +1246,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 686471 # number of writebacks -system.cpu0.dcache.writebacks::total 686471 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7833 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 495 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 495 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 869524 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 869524 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 869524 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 869524 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958342736 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958342736 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8764766768 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8764766768 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87220250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87220250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2576938 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2576938 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723109504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 30723109504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723109504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 30723109504 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004924500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004924500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718153000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718153000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723077500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723077500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108544 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108544 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054285 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059060 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059060 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003748 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003748 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086302 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086302 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086302 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34026.744213 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34026.744213 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39093.866886 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39093.866886 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11134.973829 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11134.973829 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5205.935354 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5205.935354 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35333.250726 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35333.250726 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1277,22 +1313,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2348422 # DTB read hits +system.cpu1.dtb.read_hits 3617105 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1677006 # DTB write hits +system.cpu1.dtb.write_hits 2433899 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4025428 # DTB hits +system.cpu1.dtb.data_hits 6051004 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1801062 # ITB hits +system.cpu1.itb.fetch_hits 1988116 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1802126 # ITB accesses +system.cpu1.itb.fetch_accesses 1989180 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1305,52 +1341,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3921881188 # number of cpu cycles simulated +system.cpu1.numCycles 3923841481 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12764983 # Number of instructions committed -system.cpu1.committedOps 12764983 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11763372 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses -system.cpu1.num_func_calls 404056 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1265589 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11763372 # number of integer instructions -system.cpu1.num_fp_insts 170364 # number of float instructions -system.cpu1.num_int_register_reads 16177579 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8656447 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written -system.cpu1.num_mem_refs 4047975 # number of memory refs -system.cpu1.num_load_insts 2361944 # Number of load instructions -system.cpu1.num_store_insts 1686031 # Number of store instructions -system.cpu1.num_idle_cycles 3873256564.808130 # Number of idle cycles -system.cpu1.num_busy_cycles 48624623.191870 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012398 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987602 # Percentage of idle cycles -system.cpu1.Branches 1821589 # Number of branches fetched +system.cpu1.committedInsts 21095606 # Number of instructions committed +system.cpu1.committedOps 21095606 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 19410796 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses +system.cpu1.num_func_calls 648522 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2286515 # number of instructions that are conditional controls +system.cpu1.num_int_insts 19410796 # number of integer instructions +system.cpu1.num_fp_insts 175175 # number of float instructions +system.cpu1.num_int_register_reads 26519930 # number of times the integer registers were read +system.cpu1.num_int_register_writes 14289781 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written +system.cpu1.num_mem_refs 6073244 # number of memory refs +system.cpu1.num_load_insts 3630952 # Number of load instructions +system.cpu1.num_store_insts 2442292 # Number of store instructions +system.cpu1.num_idle_cycles 3837671905.347151 # Number of idle cycles +system.cpu1.num_busy_cycles 86169575.652849 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021961 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978039 # Percentage of idle cycles +system.cpu1.Branches 3164985 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1250072 5.92% 5.92% # Class of executed instruction +system.cpu1.op_class::IntAlu 13187049 62.50% 68.43% # Class of executed instruction +system.cpu1.op_class::IntMult 30193 0.14% 68.57% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13163 0.06% 68.63% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction +system.cpu1.op_class::MemRead 3726131 17.66% 86.30% # Class of executed instruction +system.cpu1.op_class::MemWrite 2443312 11.58% 97.88% # Class of executed instruction +system.cpu1.op_class::IprAccess 446806 2.12% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 21098485 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2741 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77081 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26132 38.19% 38.19% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 39821 58.19% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 68428 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25288 48.13% 48.13% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 24782 47.16% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 52545 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1909614205500 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 700881500 0.04% 97.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 353850000 0.02% 97.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50271627000 2.56% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1960940564000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.967702 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 100735 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 37219 40.29% 40.29% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 53109 57.49% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 92384 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 36367 48.68% 48.68% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 36281 48.57% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 74704 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1906656399000 97.18% 97.18% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 706249000 0.04% 97.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 54498695500 2.78% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1961920710500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.622335 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.767887 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.683142 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.808625 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1366,87 +1437,87 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62267 88.12% 91.51% # number of callpals executed -system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed -system.cpu1.kern.callpal::rti 3685 5.22% 99.77% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed +system.cpu1.kern.callpal::swpipl 87061 91.90% 94.06% # number of callpals executed +system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed +system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 70661 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1917 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2889 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 798 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 430 -system.cpu1.kern.mode_switch_good::kernel 0.416275 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 94734 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches +system.cpu1.kern.mode_switch::user 366 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 414 +system.cpu1.kern.mode_good::user 366 +system.cpu1.kern.mode_good::idle 48 +system.cpu1.kern.mode_switch_good::kernel 0.171429 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.148840 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.308465 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17543884000 0.90% 0.90% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1484004500 0.08% 0.97% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941017048000 99.03% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1956 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 311472 # number of replacements -system.cpu1.icache.tags.tagsinuse 449.263709 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12455839 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 311983 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.924736 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1960006992500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 449.263709 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.877468 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.877468 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 437 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13079885 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13079885 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12455839 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12455839 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12455839 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12455839 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12455839 # number of overall hits -system.cpu1.icache.overall_hits::total 12455839 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 312023 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 312023 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 312023 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 312023 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 312023 # number of overall misses -system.cpu1.icache.overall_misses::total 312023 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4106650741 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4106650741 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4106650741 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4106650741 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4106650741 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4106650741 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12767862 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12767862 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12767862 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12767862 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12767862 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024438 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024438 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024438 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024438 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024438 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024438 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13161.371889 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13161.371889 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13161.371889 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13161.371889 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13161.371889 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.171856 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 65780447000 3.35% 3.35% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1486717000 0.08% 3.43% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893764152500 96.57% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2021 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 463064 # number of replacements +system.cpu1.icache.tags.tagsinuse 500.061225 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 20634869 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 463576 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 44.512376 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061225 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 21562101 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21562101 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 20634869 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 20634869 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 20634869 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 20634869 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 20634869 # number of overall hits +system.cpu1.icache.overall_hits::total 20634869 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 463616 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 463616 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 463616 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 463616 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 463616 # number of overall misses +system.cpu1.icache.overall_misses::total 463616 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6201828741 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6201828741 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6201828741 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6201828741 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6201828741 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6201828741 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098485 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21098485 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21098485 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21098485 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21098485 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21098485 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021974 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.021974 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021974 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.021974 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021974 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.021974 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13377.080905 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13377.080905 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13377.080905 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13377.080905 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13377.080905 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1455,118 +1526,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312023 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 312023 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 312023 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 312023 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 312023 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 312023 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3482409259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3482409259 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3482409259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3482409259 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3482409259 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3482409259 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024438 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024438 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024438 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024438 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11160.745391 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11160.745391 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11160.745391 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463616 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 463616 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 463616 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 463616 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 463616 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 463616 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5273752259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5273752259 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5273752259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5273752259 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5273752259 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5273752259 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021974 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.021974 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021974 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.021974 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11375.259394 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11375.259394 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11375.259394 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 155135 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.308895 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3855441 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 155464 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.799574 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852146500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308895 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949822 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949822 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16322717 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16322717 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2189668 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2189668 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1567568 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1567568 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46969 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 46969 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49480 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 49480 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3757236 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3757236 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3757236 # number of overall hits -system.cpu1.dcache.overall_hits::total 3757236 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 113735 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 113735 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 55930 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 55930 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8863 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8863 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5883 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5883 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 169665 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 169665 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 169665 # number of overall misses -system.cpu1.dcache.overall_misses::total 169665 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1371834000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1371834000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1009197248 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1009197248 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80472000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80472000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43306909 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43306909 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2381031248 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2381031248 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2381031248 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2381031248 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303403 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2303403 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623498 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1623498 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55832 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 55832 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55363 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 55363 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3926901 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3926901 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3926901 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3926901 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049377 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049377 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034450 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034450 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158744 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158744 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106262 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106262 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043206 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043206 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043206 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043206 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.669671 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.669671 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18043.934347 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18043.934347 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9079.544172 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9079.544172 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7361.364780 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7361.364780 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14033.720850 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14033.720850 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14033.720850 # average overall miss latency +system.cpu1.dcache.tags.replacements 581734 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.027113 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5462976 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 582077 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 9.385315 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027113 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 300 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.669922 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 24828652 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 24828652 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3080166 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3080166 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2260006 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2260006 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60928 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 60928 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71558 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71558 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5340172 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5340172 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5340172 # number of overall hits +system.cpu1.dcache.overall_hits::total 5340172 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 473210 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 473210 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 102503 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 102503 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11672 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11672 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 567 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 567 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 575713 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 575713 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 575713 # number of overall misses +system.cpu1.dcache.overall_misses::total 575713 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938920500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5938920500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2340100234 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2340100234 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149905750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 149905750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4163080 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4163080 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8279020734 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8279020734 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8279020734 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8279020734 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553376 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3553376 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362509 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2362509 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72600 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 72600 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 72125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 5915885 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 5915885 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 5915885 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 5915885 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133172 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.133172 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160771 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160771 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007861 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007861 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097316 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.097316 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097316 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.097316 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12550.285286 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12550.285286 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22829.578003 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22829.578003 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12843.193112 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12843.193112 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7342.292769 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.292769 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14380.465152 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14380.465152 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14380.465152 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1575,62 +1646,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 106440 # number of writebacks -system.cpu1.dcache.writebacks::total 106440 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113735 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 113735 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55930 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 55930 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8863 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8863 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 169665 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 169665 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 169665 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 169665 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144290000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144290000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 895105752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 895105752 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62746000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62746000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31539091 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31539091 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2039395752 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2039395752 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2039395752 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2039395752 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18776500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18776500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713537000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713537000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732313500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732313500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049377 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049377 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158744 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158744 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106262 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106262 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043206 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043206 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043206 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.019035 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.019035 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16004.036331 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16004.036331 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.544172 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.544172 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.055754 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.055754 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12020.132331 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12020.132331 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 444943 # number of writebacks +system.cpu1.dcache.writebacks::total 444943 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473210 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 473210 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102503 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 102503 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11672 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11672 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 567 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 567 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 575713 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 575713 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 575713 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 575713 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4992146500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4992146500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2128603766 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2128603766 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126561250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126561250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3028920 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3028920 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7120750266 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7120750266 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7120750266 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7120750266 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907861000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907861000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387519500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387519500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133172 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133172 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160771 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160771 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007861 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007861 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.097316 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097316 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.097316 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10549.537203 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10549.537203 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20766.258217 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20766.258217 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.150274 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.150274 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.010582 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.010582 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12368.576471 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12368.576471 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5b0dc7b99..24f1d16b8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,127 +1,127 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920416 # Number of seconds simulated -sim_ticks 1920416181000 # Number of ticks simulated -final_tick 1920416181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.919447 # Number of seconds simulated +sim_ticks 1919446558000 # Number of ticks simulated +final_tick 1919446558000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1752736 # Simulator instruction rate (inst/s) -host_op_rate 1752735 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59896862792 # Simulator tick rate (ticks/s) -host_mem_usage 308520 # Number of bytes of host memory used -host_seconds 32.06 # Real time elapsed on the host -sim_insts 56196255 # Number of instructions simulated -sim_ops 56196255 # Number of ops (including micro ops) simulated +host_inst_rate 885398 # Simulator instruction rate (inst/s) +host_op_rate 885398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30291378157 # Simulator tick rate (ticks/s) +host_mem_usage 344696 # Number of bytes of host memory used +host_seconds 63.37 # Real time elapsed on the host +sim_insts 56104177 # Number of instructions simulated +sim_ops 56104177 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 850752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24858240 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory -system.physmem.bytes_read::total 28363328 # Number of bytes read from this memory +system.physmem.bytes_read::total 28361344 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850752 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7405888 # Number of bytes written to this memory -system.physmem.bytes_written::total 7405888 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 7404032 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404032 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388410 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 41443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443177 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115717 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115717 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 443004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12945227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1381134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14769365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 443004 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 443004 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3856397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3856397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3856397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 443004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12945227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1381134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18625763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443177 # Number of read requests accepted -system.physmem.writeReqs 115717 # Number of write requests accepted -system.physmem.readBursts 443177 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115717 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28355584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7744 # Total number of bytes read from write queue -system.physmem.bytesWritten 7404416 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28363328 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7405888 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 121 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 443146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115688 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115688 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 443228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12950733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1381832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14775792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 443228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 443228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3857379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3857379 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3857379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 443228 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12950733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1381832 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18633171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 443146 # Number of read requests accepted +system.physmem.writeReqs 115688 # Number of write requests accepted +system.physmem.readBursts 443146 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115688 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28353856 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue +system.physmem.bytesWritten 7402304 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28361344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7404032 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27851 # Per bank write bursts -system.physmem.perBankRdBursts::1 28132 # Per bank write bursts -system.physmem.perBankRdBursts::2 28319 # Per bank write bursts -system.physmem.perBankRdBursts::3 28010 # Per bank write bursts -system.physmem.perBankRdBursts::4 27531 # Per bank write bursts -system.physmem.perBankRdBursts::5 27552 # Per bank write bursts -system.physmem.perBankRdBursts::6 26732 # Per bank write bursts -system.physmem.perBankRdBursts::7 26855 # Per bank write bursts -system.physmem.perBankRdBursts::8 27890 # Per bank write bursts -system.physmem.perBankRdBursts::9 27110 # Per bank write bursts -system.physmem.perBankRdBursts::10 27744 # Per bank write bursts -system.physmem.perBankRdBursts::11 27465 # Per bank write bursts -system.physmem.perBankRdBursts::12 27482 # Per bank write bursts -system.physmem.perBankRdBursts::13 28199 # Per bank write bursts -system.physmem.perBankRdBursts::14 28116 # Per bank write bursts -system.physmem.perBankRdBursts::15 28068 # Per bank write bursts -system.physmem.perBankWrBursts::0 7630 # Per bank write bursts -system.physmem.perBankWrBursts::1 7636 # Per bank write bursts -system.physmem.perBankWrBursts::2 7854 # Per bank write bursts -system.physmem.perBankWrBursts::3 7535 # Per bank write bursts -system.physmem.perBankWrBursts::4 7127 # Per bank write bursts -system.physmem.perBankWrBursts::5 6994 # Per bank write bursts -system.physmem.perBankWrBursts::6 6317 # Per bank write bursts -system.physmem.perBankWrBursts::7 6319 # Per bank write bursts -system.physmem.perBankWrBursts::8 7309 # Per bank write bursts -system.physmem.perBankWrBursts::9 6529 # Per bank write bursts -system.physmem.perBankWrBursts::10 7110 # Per bank write bursts -system.physmem.perBankWrBursts::11 6915 # Per bank write bursts -system.physmem.perBankWrBursts::12 7060 # Per bank write bursts -system.physmem.perBankWrBursts::13 7819 # Per bank write bursts -system.physmem.perBankWrBursts::14 7860 # Per bank write bursts -system.physmem.perBankWrBursts::15 7680 # Per bank write bursts +system.physmem.perBankRdBursts::0 27768 # Per bank write bursts +system.physmem.perBankRdBursts::1 28019 # Per bank write bursts +system.physmem.perBankRdBursts::2 28336 # Per bank write bursts +system.physmem.perBankRdBursts::3 28020 # Per bank write bursts +system.physmem.perBankRdBursts::4 27518 # Per bank write bursts +system.physmem.perBankRdBursts::5 27546 # Per bank write bursts +system.physmem.perBankRdBursts::6 26737 # Per bank write bursts +system.physmem.perBankRdBursts::7 26852 # Per bank write bursts +system.physmem.perBankRdBursts::8 27860 # Per bank write bursts +system.physmem.perBankRdBursts::9 27104 # Per bank write bursts +system.physmem.perBankRdBursts::10 27841 # Per bank write bursts +system.physmem.perBankRdBursts::11 27413 # Per bank write bursts +system.physmem.perBankRdBursts::12 27378 # Per bank write bursts +system.physmem.perBankRdBursts::13 28201 # Per bank write bursts +system.physmem.perBankRdBursts::14 28236 # Per bank write bursts +system.physmem.perBankRdBursts::15 28200 # Per bank write bursts +system.physmem.perBankWrBursts::0 7550 # Per bank write bursts +system.physmem.perBankWrBursts::1 7529 # Per bank write bursts +system.physmem.perBankWrBursts::2 7869 # Per bank write bursts +system.physmem.perBankWrBursts::3 7540 # Per bank write bursts +system.physmem.perBankWrBursts::4 7115 # Per bank write bursts +system.physmem.perBankWrBursts::5 6983 # Per bank write bursts +system.physmem.perBankWrBursts::6 6321 # Per bank write bursts +system.physmem.perBankWrBursts::7 6313 # Per bank write bursts +system.physmem.perBankWrBursts::8 7293 # Per bank write bursts +system.physmem.perBankWrBursts::9 6538 # Per bank write bursts +system.physmem.perBankWrBursts::10 7205 # Per bank write bursts +system.physmem.perBankWrBursts::11 6861 # Per bank write bursts +system.physmem.perBankWrBursts::12 6964 # Per bank write bursts +system.physmem.perBankWrBursts::13 7821 # Per bank write bursts +system.physmem.perBankWrBursts::14 7979 # Per bank write bursts +system.physmem.perBankWrBursts::15 7780 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1920404309000 # Total gap between requests +system.physmem.totGap 1919434637000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443177 # Read request sizes (log2) +system.physmem.readPktSize::6 443146 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115717 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1586 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 3793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3969 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2033 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1710 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115688 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 2507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 883 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -148,190 +148,191 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1872 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 29 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 46117 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 658.429646 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 435.074403 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 420.347464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7559 16.39% 16.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6338 13.74% 30.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2663 5.77% 35.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1600 3.47% 39.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1319 2.86% 42.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 861 1.87% 44.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 594 1.29% 45.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 461 1.00% 46.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24722 53.61% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 46117 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6598 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 67.149288 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2598.278449 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6595 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6598 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6598 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.534707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.278859 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 3.820387 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4179 63.34% 63.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 322 4.88% 68.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 428 6.49% 74.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1303 19.75% 94.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 22 0.33% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 17 0.26% 95.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 11 0.17% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 27 0.41% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 43 0.65% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 28 0.42% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 21 0.32% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 25 0.38% 97.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 19 0.29% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 43 0.65% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.06% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 12 0.18% 98.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 10 0.15% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.02% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 5 0.08% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 4 0.06% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 4 0.06% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 5 0.08% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38 2 0.03% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 9 0.14% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.06% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 4 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 1 0.02% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 2 0.03% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 3 0.05% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 1 0.02% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 1 0.02% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 6 0.09% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 8 0.12% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 5 0.08% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 6 0.09% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 3 0.05% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54 4 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::55 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::57 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6598 # Writes before turning the bus around for reads -system.physmem.totQLat 7790286250 # Total ticks spent queuing -system.physmem.totMemAccLat 16274878750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2215280000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6269312500 # Total ticks spent accessing banks -system.physmem.avgQLat 17583.07 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 14150.16 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::15 1354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1033 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66429 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 538.261302 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 328.855989 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.099114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14887 22.41% 22.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11472 17.27% 39.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4684 7.05% 46.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3132 4.71% 51.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3072 4.62% 56.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1874 2.82% 58.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1342 2.02% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1444 2.17% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24522 36.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66429 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6775 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 65.389077 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 16.529238 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2564.130292 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 6772 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6775 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6775 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.071734 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.848509 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 3.695111 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 5062 74.72% 74.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 127 1.87% 76.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1207 17.82% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 25 0.37% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 12 0.18% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.24% 95.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 18 0.27% 95.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 98 1.45% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 22 0.32% 97.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 41 0.61% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.30% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 8 0.12% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.10% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 8 0.12% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 7 0.10% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 15 0.22% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 9 0.13% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.01% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.01% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.01% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.01% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.01% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 4 0.06% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 9 0.13% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 8 0.12% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 2 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 2 0.03% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 2 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 1 0.01% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 1 0.01% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 8 0.12% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 7 0.10% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::51 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56 7 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::57 9 0.13% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::59 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6775 # Writes before turning the bus around for reads +system.physmem.totQLat 7315796250 # Total ticks spent queuing +system.physmem.totMemAccLat 15622590000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2215145000 # Total ticks spent in databus transfers +system.physmem.avgQLat 16513.13 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36733.23 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 35263.13 # Average memory access latency per DRAM burst system.physmem.avgRdBW 14.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 14.77 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 14.78 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.86 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.59 # Average write queue length when enqueuing -system.physmem.readRowHits 398457 # Number of row buffer hits during reads -system.physmem.writeRowHits 94179 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.93 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.39 # Row buffer hit rate for writes -system.physmem.avgGap 3436079.67 # Average gap between requests -system.physmem.pageHitRate 88.16 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.57 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 18667397 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292363 # Transaction distribution -system.membus.trans_dist::ReadResp 292363 # Transaction distribution -system.membus.trans_dist::WriteReq 9650 # Transaction distribution -system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115717 # Transaction distribution +system.physmem.avgWrQLen 23.40 # Average write queue length when enqueuing +system.physmem.readRowHits 398273 # Number of row buffer hits during reads +system.physmem.writeRowHits 93988 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.90 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.24 # Row buffer hit rate for writes +system.physmem.avgGap 3434713.42 # Average gap between requests +system.physmem.pageHitRate 88.11 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1800016178000 # Time in different power states +system.physmem.memoryStateTime::REF 64094420000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 55332653250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 18674823 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 292356 # Transaction distribution +system.membus.trans_dist::ReadResp 292356 # Transaction distribution +system.membus.trans_dist::WriteReq 9649 # Transaction distribution +system.membus.trans_dist::WriteResp 9649 # Transaction distribution +system.membus.trans_dist::Writeback 115688 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 158297 # Transaction distribution -system.membus.trans_dist::ReadExResp 158297 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911366 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 158273 # Transaction distribution +system.membus.trans_dist::ReadExResp 158273 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878115 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911273 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036046 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30460096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30504660 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1035953 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30456256 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30500812 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 35813780 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 35813780 # Total data (bytes) +system.membus.tot_pkt_size::total 35809932 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 35809932 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32377500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 32376000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1492987250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1491996000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3752965347 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3751677600 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 376688000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 376660500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344147 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344872 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754500427000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344147 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084009 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084009 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753525004000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344872 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084054 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084054 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -345,14 +346,14 @@ system.iocache.demand_misses::tsunami.ide 41725 # n system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21134633 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21134633 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 13148459442 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 13148459442 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 13169594075 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 13169594075 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 13169594075 # number of overall miss cycles -system.iocache.overall_miss_latency::total 13169594075 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21253133 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21253133 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 12447285431 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12447285431 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 12468538564 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12468538564 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 12468538564 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12468538564 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -369,19 +370,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122165.508671 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122165.508671 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 316433.852570 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 316433.852570 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 315628.378071 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 315628.378071 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 315628.378071 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 393896 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122850.479769 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122850.479769 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 299559.237365 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 299559.237365 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 298826.568340 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 298826.568340 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 298826.568340 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 365803 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 28296 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 28265 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 13.920554 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.941907 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -395,14 +396,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 41725 system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12137633 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12137633 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10985430442 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10985430442 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 10997568075 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10997568075 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 10997568075 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10997568075 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12255133 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12255133 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 10284312431 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 10284312431 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 10296567564 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 10296567564 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 10296567564 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 10296567564 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -411,14 +412,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70159.728324 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70159.728324 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 264377.898585 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 264377.898585 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 263572.632115 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 263572.632115 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70838.919075 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70838.919075 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 247504.631089 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 247504.631089 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 246772.140539 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 246772.140539 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -437,22 +438,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9066711 # DTB read hits -system.cpu.dtb.read_misses 10324 # DTB read misses +system.cpu.dtb.read_hits 9052923 # DTB read hits +system.cpu.dtb.read_misses 10354 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728853 # DTB read accesses -system.cpu.dtb.write_hits 6357503 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses +system.cpu.dtb.read_accesses 728911 # DTB read accesses +system.cpu.dtb.write_hits 6349403 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 15424214 # DTB hits -system.cpu.dtb.data_misses 11466 # DTB misses +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15402326 # DTB hits +system.cpu.dtb.data_misses 11497 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020784 # DTB accesses -system.cpu.itb.fetch_hits 4974520 # ITB hits +system.cpu.dtb.data_accesses 1020843 # DTB accesses +system.cpu.itb.fetch_hits 4974965 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979530 # ITB accesses +system.cpu.itb.fetch_accesses 4979975 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -465,52 +466,87 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840832362 # number of cpu cycles simulated +system.cpu.numCycles 3838893116 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56196255 # Number of instructions committed -system.cpu.committedOps 56196255 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 52067788 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1483738 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6469789 # number of instructions that are conditional controls -system.cpu.num_int_insts 52067788 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71342399 # number of times the integer registers were read -system.cpu.num_int_register_writes 38531411 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15476821 # number of memory refs -system.cpu.num_load_insts 9103557 # Number of load instructions -system.cpu.num_store_insts 6373264 # Number of store instructions -system.cpu.num_idle_cycles 3589010980.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251821381.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065564 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934436 # Percentage of idle cycles -system.cpu.Branches 8424076 # Number of branches fetched +system.cpu.committedInsts 56104177 # Number of instructions committed +system.cpu.committedOps 56104177 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51979169 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324594 # Number of float alu accesses +system.cpu.num_func_calls 1481286 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461218 # number of instructions that are conditional controls +system.cpu.num_int_insts 51979169 # number of integer instructions +system.cpu.num_fp_insts 324594 # number of float instructions +system.cpu.num_int_register_reads 71209746 # number of times the integer registers were read +system.cpu.num_int_register_writes 38460532 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163708 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166588 # number of times the floating registers were written +system.cpu.num_mem_refs 15454993 # number of memory refs +system.cpu.num_load_insts 9089820 # Number of load instructions +system.cpu.num_store_insts 6365173 # Number of store instructions +system.cpu.num_idle_cycles 3587243859.498131 # Number of idle cycles +system.cpu.num_busy_cycles 251649256.501869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065553 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934447 # Percentage of idle cycles +system.cpu.Branches 8413035 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197761 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36186344 64.48% 70.18% # Class of executed instruction +system.cpu.op_class::IntMult 61011 0.11% 70.29% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.29% # Class of executed instruction +system.cpu.op_class::FloatAdd 25613 0.05% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction +system.cpu.op_class::MemRead 9316905 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6371245 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953526 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 56116041 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212001 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74899 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106222 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183184 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73532 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 106210 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183167 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149127 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858066400000 96.75% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91407000 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737349500 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61520290500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920415447000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857252195000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91387500 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 737178000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61365063500 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1919445824000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692248 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814083 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692289 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814110 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -546,33 +582,33 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4179 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175963 91.22% 93.41% # number of callpals executed -system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175948 91.21% 93.41% # number of callpals executed +system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed -system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192909 # number of callpals executed +system.cpu.kern.callpal::total 192895 # number of callpals executed system.cpu.kern.mode_switch::kernel 5904 # number of protection mode switches system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1912 system.cpu.kern.mode_good::user 1741 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323679 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 171 +system.cpu.kern.mode_switch_good::kernel 0.323848 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46067941500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5182686000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869164817500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392527 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46108525500 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5189217000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868148079500 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4180 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -604,12 +640,12 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409159 # Throughput (bytes/s) +system.iobus.throughput 1409867 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51202 # Transaction distribution -system.iobus.trans_dist::WriteResp 51202 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5156 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51201 # Transaction distribution +system.iobus.trans_dist::WriteResp 51201 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -621,11 +657,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33160 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116610 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -637,12 +673,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2706172 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2706172 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4767000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 2706164 # Total data (bytes) +system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -664,67 +700,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 380034075 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 380199064 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 43162000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 43233500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928494 # number of replacements -system.cpu.icache.tags.tagsinuse 508.301721 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55278924 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929005 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.503365 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39895254250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.301721 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992777 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992777 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 927875 # number of replacements +system.cpu.icache.tags.tagsinuse 508.303976 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55187496 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928386 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.444559 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.303976 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57137254 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57137254 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55278924 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55278924 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55278924 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55278924 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55278924 # number of overall hits -system.cpu.icache.overall_hits::total 55278924 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929165 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929165 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929165 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929165 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929165 # number of overall misses -system.cpu.icache.overall_misses::total 929165 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12919006759 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12919006759 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12919006759 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12919006759 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12919006759 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12919006759 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56208089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56208089 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56208089 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56208089 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56208089 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56208089 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016531 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016531 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016531 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016531 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016531 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016531 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.888716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13903.888716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13903.888716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.888716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13903.888716 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57044588 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57044588 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55187496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55187496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55187496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55187496 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55187496 # number of overall hits +system.cpu.icache.overall_hits::total 55187496 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928546 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928546 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928546 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928546 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928546 # number of overall misses +system.cpu.icache.overall_misses::total 928546 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12910342260 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12910342260 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12910342260 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12910342260 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12910342260 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12910342260 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56116042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56116042 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56116042 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56116042 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56116042 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56116042 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016547 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016547 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016547 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016547 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016547 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016547 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13903.826262 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13903.826262 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13903.826262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13903.826262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13903.826262 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -733,135 +769,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929165 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929165 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929165 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929165 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929165 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929165 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11055577241 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11055577241 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11055577241 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11055577241 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11055577241 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11055577241 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016531 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016531 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016531 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016531 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.400436 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.400436 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.400436 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.400436 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928546 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928546 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928546 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928546 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928546 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928546 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048086740 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11048086740 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048086740 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11048086740 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048086740 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11048086740 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016547 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016547 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016547 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016547 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11898.265396 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11898.265396 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11898.265396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11898.265396 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336265 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65295.577509 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2447728 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895641500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229787500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229787500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250259 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141506 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607242375 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607242375 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 800656260 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20906735629 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21707391889 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 800656260 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20906735629 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21707391889 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334145500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1895432500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1895432500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229578000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229578000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250313 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141564 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383733 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383733 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173297 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014307 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279476 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173297 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60282.085233 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52633.010656 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52989.454421 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384060 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # 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average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60231.419544 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53772.468182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53985.997988 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -937,13 +973,13 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390702 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.088927 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978877 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -951,72 +987,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63164291 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091433 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091433 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091433 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27122.777447 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27122.777447 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35852.292223 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35852.292223 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.881157 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.881157 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29056.421306 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29056.421306 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29056.421306 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1025,54 +1061,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835359 # number of writebacks -system.cpu.dcache.writebacks::total 835359 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069509 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069509 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304562 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304562 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17233 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17233 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1374071 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1374071 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1374071 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1374071 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26755042991 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26755042991 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10192844115 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10192844115 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194257500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194257500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36947887106 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36947887106 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36947887106 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36947887106 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011441500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011441500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435677500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435677500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120361 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120361 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049459 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086053 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086053 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091338 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091338 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25016.192469 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25016.192469 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33467.222158 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33467.222158 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.413393 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.413393 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26889.358051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26889.358051 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834591 # number of writebacks +system.cpu.dcache.writebacks::total 834591 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069264 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069264 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304240 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304240 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17216 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17216 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373504 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373504 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373504 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373504 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26737269496 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26737269496 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10246531614 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10246531614 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193767750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193767750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36983801110 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36983801110 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36983801110 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36983801110 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424235500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011220500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011220500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435456000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435456000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120520 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120520 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049471 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091433 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091433 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091433 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25005.302242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25005.302242 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33679.107330 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33679.107330 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11255.097003 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11255.097003 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26926.606046 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26926.606046 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1080,31 +1116,31 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 105199341 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2023010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2022993 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 835359 # Transaction distribution +system.cpu.toL2Bus.throughput 105186760 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2022129 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2022112 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834591 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 346097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304546 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858310 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5509594 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59465280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142559956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 202025236 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 202015188 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 345775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304224 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857072 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5506418 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59425664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142473420 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 201899084 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 201889036 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 11328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2426388000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 2424633500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1396297259 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395400760 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2187438394 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186975140 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 49e1054f0..547f88656 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,33 +4,15 @@ sim_seconds 0.912098 # Nu sim_ticks 912098398000 # Number of ticks simulated final_tick 912098398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1169212 # Simulator instruction rate (inst/s) -host_op_rate 1505339 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17301899059 # Simulator tick rate (ticks/s) -host_mem_usage 421332 # Number of bytes of host memory used -host_seconds 52.72 # Real time elapsed on the host +host_inst_rate 1024713 # Simulator instruction rate (inst/s) +host_op_rate 1319299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15163617701 # Simulator tick rate (ticks/s) +host_mem_usage 465872 # Number of bytes of host memory used +host_seconds 60.15 # Real time elapsed on the host sim_insts 61636937 # Number of instructions simulated sim_ops 79356422 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -86,6 +68,24 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To system.physmem.bw_total::cpu1.inst 235277 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6989035 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 62341647 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 64987015 # Throughput (bytes/s) system.membus.data_through_bus 59274552 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) @@ -397,6 +397,41 @@ system.cpu0.num_busy_cycles 39676799.500046 # system.cpu0.not_idle_fraction 0.021757 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.978243 # Percentage of idle cycles system.cpu0.Branches 5492144 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16326 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 24520115 62.53% 62.57% # Class of executed instruction +system.cpu0.op_class::IntMult 45259 0.12% 62.69% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1421 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 62.69% # Class of executed instruction +system.cpu0.op_class::MemRead 8359235 21.32% 84.01% # Class of executed instruction +system.cpu0.op_class::MemWrite 6270624 15.99% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 39212980 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 50449 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 428546 # number of replacements @@ -627,6 +662,41 @@ system.cpu1.num_busy_cycles 40793919.244318 # system.cpu1.not_idle_fraction 0.022363 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.977637 # Percentage of idle cycles system.cpu1.Branches 5037975 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12508 0.03% 0.03% # Class of executed instruction +system.cpu1.op_class::IntAlu 26844895 66.65% 66.68% # Class of executed instruction +system.cpu1.op_class::IntMult 49628 0.12% 66.80% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 737 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 66.80% # Class of executed instruction +system.cpu1.op_class::MemRead 7642991 18.98% 85.78% # Class of executed instruction +system.cpu1.op_class::MemWrite 5728160 14.22% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 40278919 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 40450 # number of quiesce instructions executed system.cpu1.icache.tags.replacements 433942 # number of replacements diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 101d25ddf..04261a831 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332812 # Nu sim_ticks 2332811899500 # Number of ticks simulated final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1065837 # Simulator instruction rate (inst/s) -host_op_rate 1370594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41157671581 # Simulator tick rate (ticks/s) -host_mem_usage 420236 # Number of bytes of host memory used -host_seconds 56.68 # Real time elapsed on the host +host_inst_rate 975328 # Simulator instruction rate (inst/s) +host_op_rate 1254205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37662621026 # Simulator tick rate (ticks/s) +host_mem_usage 462792 # Number of bytes of host memory used +host_seconds 61.94 # Real time elapsed on the host sim_insts 60411489 # Number of instructions simulated sim_ops 77685090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -182,6 +182,41 @@ system.cpu.num_busy_cycles 78801726.992856 # system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles system.cpu.idle_fraction 0.983110 # Percentage of idle cycles system.cpu.Branches 10299261 # Number of branches fetched +system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 50337551 64.69% 64.72% # Class of executed instruction +system.cpu.op_class::IntMult 87780 0.11% 64.84% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 2117 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::MemRead 15640088 20.10% 84.94% # Class of executed instruction +system.cpu.op_class::MemWrite 11722333 15.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 77818387 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu.icache.tags.replacements 850590 # number of replacements diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 789d25c60..8e4b444a3 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,170 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.196225 # Number of seconds simulated -sim_ticks 1196225147500 # Number of ticks simulated -final_tick 1196225147500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.195945 # Number of seconds simulated +sim_ticks 1195945260000 # Number of ticks simulated +final_tick 1195945260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 669591 # Simulator instruction rate (inst/s) -host_op_rate 853186 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13029857543 # Simulator tick rate (ticks/s) -host_mem_usage 426076 # Number of bytes of host memory used -host_seconds 91.81 # Real time elapsed on the host -sim_insts 61472758 # Number of instructions simulated -sim_ops 78327958 # Number of ops (including micro ops) simulated +host_inst_rate 424891 # Simulator instruction rate (inst/s) +host_op_rate 541366 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8267957779 # Simulator tick rate (ticks/s) +host_mem_usage 468940 # Number of bytes of host memory used +host_seconds 144.65 # Real time elapsed on the host +sim_insts 61459750 # Number of instructions simulated +sim_ops 78307634 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 378508 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4532924 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393612 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4714684 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 337988 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4964984 # Number of bytes read from this memory -system.physmem.bytes_read::total 62119428 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 378508 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 337988 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716496 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4092288 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 324676 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4804472 # Number of bytes read from this memory +system.physmem.bytes_read::total 62142468 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393612 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 324676 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 718288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4110592 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7119632 # Number of bytes written to this memory +system.physmem.bytes_written::total 7137936 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12142 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70901 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73741 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5372 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77606 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654093 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63942 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75098 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654453 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64228 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820778 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43390253 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821064 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43400408 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 316419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3789357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 329122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3942224 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 282545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4150543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51929545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 316419 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 282545 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 598964 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3421001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14211 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2516536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5951749 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3421001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43390253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 271481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4017301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51960963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 329122 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 271481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 600603 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3437107 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14215 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2517125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 5968447 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3437107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43400408 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 316419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3803568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 329122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3956439 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 282545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6667079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57881294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654093 # Number of read requests accepted -system.physmem.writeReqs 820778 # Number of write requests accepted -system.physmem.readBursts 6654093 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 820778 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425823936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 38016 # Total number of bytes read from write queue -system.physmem.bytesWritten 7142848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62119428 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7119632 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 594 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709146 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 11979 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415258 # Per bank write bursts -system.physmem.perBankRdBursts::1 415304 # Per bank write bursts -system.physmem.perBankRdBursts::2 415298 # Per bank write bursts -system.physmem.perBankRdBursts::3 415715 # Per bank write bursts -system.physmem.perBankRdBursts::4 422332 # Per bank write bursts -system.physmem.perBankRdBursts::5 415542 # Per bank write bursts -system.physmem.perBankRdBursts::6 415821 # Per bank write bursts -system.physmem.perBankRdBursts::7 415579 # Per bank write bursts -system.physmem.perBankRdBursts::8 415943 # Per bank write bursts -system.physmem.perBankRdBursts::9 415582 # Per bank write bursts -system.physmem.perBankRdBursts::10 415396 # Per bank write bursts -system.physmem.perBankRdBursts::11 414885 # Per bank write bursts -system.physmem.perBankRdBursts::12 414891 # Per bank write bursts -system.physmem.perBankRdBursts::13 415396 # Per bank write bursts -system.physmem.perBankRdBursts::14 415532 # Per bank write bursts -system.physmem.perBankRdBursts::15 415025 # Per bank write bursts -system.physmem.perBankWrBursts::0 6797 # Per bank write bursts -system.physmem.perBankWrBursts::1 6838 # Per bank write bursts -system.physmem.perBankWrBursts::2 6874 # Per bank write bursts -system.physmem.perBankWrBursts::3 7108 # Per bank write bursts -system.physmem.perBankWrBursts::4 7245 # Per bank write bursts -system.physmem.perBankWrBursts::5 7088 # Per bank write bursts -system.physmem.perBankWrBursts::6 7332 # Per bank write bursts -system.physmem.perBankWrBursts::7 7150 # Per bank write bursts -system.physmem.perBankWrBursts::8 7392 # Per bank write bursts -system.physmem.perBankWrBursts::9 7114 # Per bank write bursts -system.physmem.perBankWrBursts::10 7008 # Per bank write bursts -system.physmem.perBankWrBursts::11 6578 # Per bank write bursts -system.physmem.perBankWrBursts::12 6732 # Per bank write bursts -system.physmem.perBankWrBursts::13 6801 # Per bank write bursts -system.physmem.perBankWrBursts::14 7004 # Per bank write bursts -system.physmem.perBankWrBursts::15 6546 # Per bank write bursts +system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 271481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6534426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57929411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654453 # Number of read requests accepted +system.physmem.writeReqs 821064 # Number of write requests accepted +system.physmem.readBursts 6654453 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 821064 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 425841472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43520 # Total number of bytes read from write queue +system.physmem.bytesWritten 7149184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 62142468 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7137936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 680 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709327 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12098 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 415328 # Per bank write bursts +system.physmem.perBankRdBursts::1 415212 # Per bank write bursts +system.physmem.perBankRdBursts::2 415403 # Per bank write bursts +system.physmem.perBankRdBursts::3 415611 # Per bank write bursts +system.physmem.perBankRdBursts::4 422397 # Per bank write bursts +system.physmem.perBankRdBursts::5 415577 # Per bank write bursts +system.physmem.perBankRdBursts::6 415747 # Per bank write bursts +system.physmem.perBankRdBursts::7 415496 # Per bank write bursts +system.physmem.perBankRdBursts::8 416027 # Per bank write bursts +system.physmem.perBankRdBursts::9 415632 # Per bank write bursts +system.physmem.perBankRdBursts::10 415426 # Per bank write bursts +system.physmem.perBankRdBursts::11 414842 # Per bank write bursts +system.physmem.perBankRdBursts::12 414820 # Per bank write bursts +system.physmem.perBankRdBursts::13 415557 # Per bank write bursts +system.physmem.perBankRdBursts::14 415554 # Per bank write bursts +system.physmem.perBankRdBursts::15 415144 # Per bank write bursts +system.physmem.perBankWrBursts::0 6840 # Per bank write bursts +system.physmem.perBankWrBursts::1 6732 # Per bank write bursts +system.physmem.perBankWrBursts::2 6969 # Per bank write bursts +system.physmem.perBankWrBursts::3 7025 # Per bank write bursts +system.physmem.perBankWrBursts::4 7326 # Per bank write bursts +system.physmem.perBankWrBursts::5 7107 # Per bank write bursts +system.physmem.perBankWrBursts::6 7317 # Per bank write bursts +system.physmem.perBankWrBursts::7 7078 # Per bank write bursts +system.physmem.perBankWrBursts::8 7464 # Per bank write bursts +system.physmem.perBankWrBursts::9 7155 # Per bank write bursts +system.physmem.perBankWrBursts::10 7023 # Per bank write bursts +system.physmem.perBankWrBursts::11 6543 # Per bank write bursts +system.physmem.perBankWrBursts::12 6616 # Per bank write bursts +system.physmem.perBankWrBursts::13 6901 # Per bank write bursts +system.physmem.perBankWrBursts::14 6977 # Per bank write bursts +system.physmem.perBankWrBursts::15 6633 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1196220625500 # Total gap between requests +system.physmem.totGap 1195940759000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6849 # Read request sizes (log2) system.physmem.readPktSize::3 6488064 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159180 # Read request sizes (log2) +system.physmem.readPktSize::6 159540 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 756836 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 63942 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 568386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 406756 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 406740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 413202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 408903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 410926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1188562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1189774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1562236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 22558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 14685 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 15166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 13714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 12546 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 9828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64228 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 572493 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 410656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 412880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 461685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 417933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 446395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1149366 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1113988 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1438120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 64577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 50343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 45843 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 44044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8771 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -194,45 +180,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -243,370 +229,393 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 427748 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.884371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 962.233746 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 147.681447 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5003 1.17% 1.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3928 0.92% 2.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2092 0.49% 2.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1312 0.31% 2.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1079 0.25% 3.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 787 0.18% 3.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 742 0.17% 3.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 447 0.10% 3.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 412358 96.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 427748 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5121 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1299.254638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 29808.283067 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 5114 99.86% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.06% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.57286e+06-1.6384e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5121 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.793986 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.383938 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.006526 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2131 41.61% 41.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 296 5.78% 47.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 286 5.58% 52.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1314 25.66% 78.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 15 0.29% 78.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 5 0.10% 79.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 79.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.04% 79.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 79.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 3 0.06% 79.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 79.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.02% 79.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 953 18.61% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 61 1.19% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 17 0.33% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 33 0.64% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5121 # Writes before turning the bus around for reads -system.physmem.totQLat 249828830750 # Total ticks spent queuing -system.physmem.totMemAccLat 297299498250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33267495000 # Total ticks spent in databus transfers -system.physmem.totBankLat 14203172500 # Total ticks spent accessing banks -system.physmem.avgQLat 37548.49 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 2134.69 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 473596 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 914.261641 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 784.047795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 289.306705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25239 5.33% 5.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21585 4.56% 9.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5945 1.26% 11.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2453 0.52% 11.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2290 0.48% 12.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1636 0.35% 12.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4075 0.86% 13.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 899 0.19% 13.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 409474 86.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 473596 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6482 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 1026.497532 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 34346.134147 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-131071 6476 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-262143 3 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-655359 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-917503 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.49037e+06-2.62144e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6482 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6482 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.233261 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.205432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.970583 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2453 37.84% 37.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 80 1.23% 39.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3936 60.72% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 11 0.17% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6482 # Writes before turning the bus around for reads +system.physmem.totQLat 171035006500 # Total ticks spent queuing +system.physmem.totMemAccLat 295793250250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 33268865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25704.97 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44683.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 355.97 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.97 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.93 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44454.97 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 356.07 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 51.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.83 # Data bus utilization in percentage system.physmem.busUtilRead 2.78 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 4.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 29.44 # Average write queue length when enqueuing -system.physmem.readRowHits 6202256 # Number of row buffer hits during reads -system.physmem.writeRowHits 93908 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.22 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.12 # Row buffer hit rate for writes -system.physmem.avgGap 160032.28 # Average gap between requests -system.physmem.pageHitRate 93.07 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 6.14 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 59898120 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703395 # Transaction distribution -system.membus.trans_dist::ReadResp 7703395 # Transaction distribution -system.membus.trans_dist::WriteReq 767585 # Transaction distribution -system.membus.trans_dist::WriteResp 767585 # Transaction distribution -system.membus.trans_dist::Writeback 63942 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31730 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17317 # Transaction distribution -system.membus.trans_dist::UpgradeResp 11979 # Transaction distribution -system.membus.trans_dist::ReadExReq 137317 # Transaction distribution -system.membus.trans_dist::ReadExResp 136921 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382690 # Packet count per connected master and slave (bytes) +system.physmem.avgRdQLen 4.89 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.45 # Average write queue length when enqueuing +system.physmem.readRowHits 6199461 # Number of row buffer hits during reads +system.physmem.writeRowHits 92422 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.71 # Row buffer hit rate for writes +system.physmem.avgGap 159981.01 # Average gap between requests +system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 947634468500 # Time in different power states +system.physmem.memoryStateTime::REF 39935220000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 208375212750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 59946686 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703403 # Transaction distribution +system.membus.trans_dist::ReadResp 7703403 # Transaction distribution +system.membus.trans_dist::WriteReq 767582 # Transaction distribution +system.membus.trans_dist::WriteResp 767582 # Transaction distribution +system.membus.trans_dist::Writeback 64228 # Transaction distribution +system.membus.trans_dist::UpgradeReq 31700 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17261 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12098 # Transaction distribution +system.membus.trans_dist::ReadExReq 137709 # Transaction distribution +system.membus.trans_dist::ReadExResp 137266 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382666 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10302 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 914 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971094 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4365038 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1972180 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366104 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17341166 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390070 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17342232 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390035 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20604 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17334548 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19747126 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1820 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17375892 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19788443 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71651638 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71651638 # Total data (bytes) +system.membus.tot_pkt_size::total 71692955 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71692955 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224825500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1224801000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9234000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9242500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 786000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 784500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9208108500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9211274000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5075173558 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5078680829 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 16181474500 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 16046108250 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69062 # number of replacements -system.l2c.tags.tagsinuse 52959.899517 # Cycle average of tags in use -system.l2c.tags.total_refs 1674433 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134270 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.470641 # Average number of references to valid blocks. +system.l2c.tags.replacements 69421 # number of replacements +system.l2c.tags.tagsinuse 53012.823108 # Cycle average of tags in use +system.l2c.tags.total_refs 1672128 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134609 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.422111 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40142.433744 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 40185.217534 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.003238 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3707.808501 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4231.213775 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742447 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2816.465022 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2059.232379 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.612525 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3710.755623 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4242.358437 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.742287 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001689 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2808.724549 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2063.021033 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.613178 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056577 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064563 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.056622 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.064733 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042976 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031421 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042858 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.031479 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.808911 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65203 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1924 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7908 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1920 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8039 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55163 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994919 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17240213 # Number of tag accesses -system.l2c.tags.data_accesses 17240213 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 2997 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1656 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 349452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6371 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1905 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 535287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 180837 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1248430 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 572475 # number of Writeback hits -system.l2c.Writeback_hits::total 572475 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 587 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1630 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 220 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 84 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 304 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 47236 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 62412 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109648 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 2997 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1656 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 349452 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 217161 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6371 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1905 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 535287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 243249 # number of demand (read+write) hits -system.l2c.demand_hits::total 1358078 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 2997 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1656 # number of overall hits -system.l2c.overall_hits::cpu0.inst 349452 # number of overall hits -system.l2c.overall_hits::cpu0.data 217161 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6371 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1905 # number of overall hits -system.l2c.overall_hits::cpu1.inst 535287 # number of overall hits -system.l2c.overall_hits::cpu1.data 243249 # number of overall hits -system.l2c.overall_hits::total 1358078 # number of overall hits +system.l2c.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17207703 # Number of tag accesses +system.l2c.tags.data_accesses 17207703 # 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average ReadReq mshr uncacheable latency @@ -788,67 +809,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119642613 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2536412 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2536412 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767585 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767585 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 572475 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30937 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17621 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48558 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260776 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260776 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 723469 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1059051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 4339 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7907 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1082141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4772543 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7929 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 20256 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7677635 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 22743520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35146882 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6636 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 11992 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 34596404 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 46050592 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7620 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 25500 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138589146 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138589146 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4530356 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4766758175 # Layer occupancy (ticks) +system.toL2Bus.throughput 119513329 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2535217 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2535217 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767582 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767582 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 570869 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 30989 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 17585 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 48574 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 260651 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 260651 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 863496 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226215 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12691 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 940498 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4601530 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7672224 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27215456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41348685 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6964 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30072692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39622266 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 22032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138310979 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138310979 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4620420 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4758868690 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1607753214 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1517597206 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1923485226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1752589322 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2680000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 4396000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 4909499 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 8880000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2437223968 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2117887474 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 3163938724 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 6024000 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 2927028338 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 13881500 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 9913999 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45388263 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671442 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671442 # Transaction distribution -system.iobus.trans_dist::WriteReq 7967 # Transaction distribution -system.iobus.trans_dist::WriteResp 7967 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8070 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45398856 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671434 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671434 # Transaction distribution +system.iobus.trans_dist::WriteReq 7963 # Transaction distribution +system.iobus.trans_dist::WriteResp 7963 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 742 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -865,17 +886,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382690 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382666 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358818 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 15358794 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40319 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1484 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -892,14 +913,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390070 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390035 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294582 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294582 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21430000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 54294547 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294547 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21418000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4041000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -909,7 +930,7 @@ system.iobus.reqLayer4.occupancy 27000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) @@ -945,9 +966,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374723000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374703000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16195242500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16368811750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -972,25 +993,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 5879584 # DTB read hits -system.cpu0.dtb.read_misses 2138 # DTB read misses -system.cpu0.dtb.write_hits 4838515 # DTB write hits -system.cpu0.dtb.write_misses 406 # DTB write misses +system.cpu0.dtb.read_hits 7064335 # DTB read hits +system.cpu0.dtb.read_misses 3758 # DTB read misses +system.cpu0.dtb.write_hits 5649339 # DTB write hits +system.cpu0.dtb.write_misses 802 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1387 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 88 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 203 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 5881722 # DTB read accesses -system.cpu0.dtb.write_accesses 4838921 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7068093 # DTB read accesses +system.cpu0.dtb.write_accesses 5650141 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 10718099 # DTB hits -system.cpu0.dtb.misses 2544 # DTB misses -system.cpu0.dtb.accesses 10720643 # DTB accesses +system.cpu0.dtb.hits 12713674 # DTB hits +system.cpu0.dtb.misses 4560 # DTB misses +system.cpu0.dtb.accesses 12718234 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1012,8 +1033,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 24773464 # ITB inst hits -system.cpu0.itb.inst_misses 1350 # ITB inst misses +system.cpu0.itb.inst_hits 29562995 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1022,94 +1043,130 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 963 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 24774814 # ITB inst accesses -system.cpu0.itb.hits 24773464 # DTB hits -system.cpu0.itb.misses 1350 # DTB misses -system.cpu0.itb.accesses 24774814 # DTB accesses -system.cpu0.numCycles 2391604989 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29565200 # ITB inst accesses +system.cpu0.itb.hits 29562995 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29565200 # DTB accesses +system.cpu0.numCycles 2391890520 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 24375312 # Number of instructions committed -system.cpu0.committedOps 31460856 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28085533 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4364 # Number of float alu accesses -system.cpu0.num_func_calls 1070699 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3751745 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28085533 # number of integer instructions -system.cpu0.num_fp_insts 4364 # number of float instructions -system.cpu0.num_int_register_reads 162520351 # number of times the integer registers were read -system.cpu0.num_int_register_writes 30535592 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 384 # number of times the floating registers were written -system.cpu0.num_mem_refs 11309766 # number of memory refs -system.cpu0.num_load_insts 6158982 # Number of load instructions -system.cpu0.num_store_insts 5150784 # Number of store instructions -system.cpu0.num_idle_cycles 2265857607.135565 # Number of idle cycles -system.cpu0.num_busy_cycles 125747381.864435 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052579 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947421 # Percentage of idle cycles -system.cpu0.Branches 4778581 # Number of branches fetched +system.cpu0.committedInsts 28864889 # Number of instructions committed +system.cpu0.committedOps 37190899 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33115613 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1241798 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4372441 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33115613 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 192173380 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36248506 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13380838 # number of memory refs +system.cpu0.num_load_insts 7401595 # Number of load instructions +system.cpu0.num_store_insts 5979243 # Number of store instructions +system.cpu0.num_idle_cycles 2246179687.500122 # Number of idle cycles +system.cpu0.num_busy_cycles 145710832.499878 # Number of busy cycles +system.cpu0.not_idle_fraction 0.060919 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.939081 # Percentage of idle cycles +system.cpu0.Branches 5600259 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14567 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 24478507 64.56% 64.59% # Class of executed instruction +system.cpu0.op_class::IntMult 43773 0.12% 64.71% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 694 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.71% # Class of executed instruction +system.cpu0.op_class::MemRead 7401595 19.52% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 5979243 15.77% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 37918379 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 39137 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 354708 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.352361 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 24418226 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 355220 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 68.741135 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76254991000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.352361 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994829 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994829 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 46956 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 424861 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.353809 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 29137604 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 425373 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 68.498950 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76246574000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.353809 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994832 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994832 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 25128668 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 25128668 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 24418226 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 24418226 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 24418226 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 24418226 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 24418226 # number of overall hits -system.cpu0.icache.overall_hits::total 24418226 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 355221 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 355221 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 355221 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 355221 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 355221 # number of overall misses -system.cpu0.icache.overall_misses::total 355221 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 4963623214 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 4963623214 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 4963623214 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 4963623214 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 4963623214 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 4963623214 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 24773447 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 24773447 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 24773447 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 24773447 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 24773447 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 24773447 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014339 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014339 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014339 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014339 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014339 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014339 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13973.338327 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13973.338327 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13973.338327 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13973.338327 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13973.338327 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 29988352 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 29988352 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29137604 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29137604 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29137604 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29137604 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29137604 # number of overall hits +system.cpu0.icache.overall_hits::total 29137604 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425374 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425374 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425374 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425374 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425374 # number of overall misses +system.cpu0.icache.overall_misses::total 425374 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5893447476 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5893447476 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5893447476 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5893447476 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5893447476 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5893447476 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29562978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29562978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29562978 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29562978 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29562978 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29562978 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014389 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014389 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014389 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014389 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014389 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014389 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13854.743064 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13854.743064 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13854.743064 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13854.743064 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13854.743064 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13854.743064 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1118,126 +1175,128 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 355221 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 355221 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 355221 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 355221 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 355221 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 355221 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4251043786 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4251043786 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4251043786 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4251043786 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4251043786 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4251043786 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 443885000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 443885000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 443885000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 443885000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014339 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014339 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014339 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014339 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11967.321149 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.321149 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11967.321149 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425374 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425374 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425374 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425374 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425374 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425374 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5040497524 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5040497524 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5040497524 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5040497524 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5040497524 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5040497524 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 442131250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 442131250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 442131250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 442131250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014389 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014389 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014389 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014389 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11849.566556 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11849.566556 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11849.566556 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11849.566556 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 278858 # number of replacements -system.cpu0.dcache.tags.tagsinuse 453.142717 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10319958 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 279247 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.956379 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 673996250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.142717 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.885044 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.885044 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 379 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 42855830 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 42855830 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5473702 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5473702 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4567964 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4567964 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 129389 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 129389 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 130155 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 130155 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10041666 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10041666 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10041666 # number of overall hits -system.cpu0.dcache.overall_hits::total 10041666 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191503 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 191503 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 126416 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 126416 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8708 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8708 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7742 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7742 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 317919 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 317919 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 317919 # number of overall misses -system.cpu0.dcache.overall_misses::total 317919 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2845005745 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 2845005745 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5278408391 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 5278408391 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 82648500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 82648500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45599070 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 45599070 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8123414136 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 8123414136 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8123414136 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 8123414136 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5665205 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5665205 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4694380 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4694380 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138097 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 138097 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137897 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 137897 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10359585 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10359585 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10359585 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10359585 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033803 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033803 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026929 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026929 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.063057 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.063057 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056143 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056143 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030688 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.030688 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030688 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.030688 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.194133 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.194133 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41754.274704 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41754.274704 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9491.100138 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9491.100138 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5889.830793 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5889.830793 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25551.835958 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25551.835958 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25551.835958 # average overall miss latency +system.cpu0.dcache.tags.replacements 329701 # number of replacements +system.cpu0.dcache.tags.tagsinuse 455.940244 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12258862 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 330213 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.124105 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 671876250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 455.940244 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.890508 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.890508 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50852546 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50852546 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6594319 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6594319 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5344510 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5344510 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 148000 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 148000 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149609 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149609 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11938829 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11938829 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11938829 # number of overall hits +system.cpu0.dcache.overall_hits::total 11938829 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 227548 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 227548 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141421 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141421 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9358 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9358 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7517 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7517 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 368969 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 368969 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 368969 # number of overall misses +system.cpu0.dcache.overall_misses::total 368969 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3297192496 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3297192496 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5650617511 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5650617511 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92814250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 92814250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44512065 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 44512065 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8947810007 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8947810007 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8947810007 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8947810007 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6821867 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6821867 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5485931 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5485931 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157358 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157358 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157126 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157126 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12307798 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12307798 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12307798 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12307798 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033356 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033356 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025779 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025779 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059469 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059469 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047841 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047841 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029978 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029978 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029978 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029978 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.096577 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.096577 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39956.000247 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39956.000247 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9918.171618 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9918.171618 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5921.519888 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5921.519888 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 24250.844941 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24250.844941 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24250.844941 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1246,62 +1305,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 257140 # number of writebacks -system.cpu0.dcache.writebacks::total 257140 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 191503 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 191503 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 126416 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 126416 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8708 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8708 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7738 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7738 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 317919 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 317919 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 317919 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 317919 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2460118255 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2460118255 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4997663609 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4997663609 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65185500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65185500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30121930 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30121930 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7457781864 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7457781864 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7457781864 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7457781864 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12214482000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12214482000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1164635000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1164635000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13379117000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13379117000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033803 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033803 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026929 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063057 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063057 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056114 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056114 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.030688 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030688 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.030688 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12846.369274 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12846.369274 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39533.473682 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39533.473682 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7485.702802 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7485.702802 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3892.728095 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3892.728095 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23458.119408 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23458.119408 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 305583 # number of writebacks +system.cpu0.dcache.writebacks::total 305583 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227548 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227548 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141421 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141421 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7515 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7515 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 368969 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 368969 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 368969 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 368969 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2840145504 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2840145504 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338354489 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338354489 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 74046750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 74046750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29480935 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29480935 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8178499993 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8178499993 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8178499993 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8178499993 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13564071000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13564071000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1170919500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1170919500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14734990500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14734990500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033356 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033356 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025779 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025779 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059469 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059469 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047828 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047828 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029978 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029978 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029978 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12481.522597 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12481.522597 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37747.961682 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37747.961682 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.668305 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.668305 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3922.945442 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3922.945442 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22165.818790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22165.818790 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1332,25 +1391,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 9507781 # DTB read hits -system.cpu1.dtb.read_misses 5255 # DTB read misses -system.cpu1.dtb.write_hits 6647969 # DTB write hits -system.cpu1.dtb.write_misses 1834 # DTB write misses +system.cpu1.dtb.read_hits 8317790 # DTB read hits +system.cpu1.dtb.read_misses 3645 # DTB read misses +system.cpu1.dtb.write_hits 5833574 # DTB write hits +system.cpu1.dtb.write_misses 1433 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2187 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1863 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 188 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 249 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 9513036 # DTB read accesses -system.cpu1.dtb.write_accesses 6649803 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8321435 # DTB read accesses +system.cpu1.dtb.write_accesses 5835007 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16155750 # DTB hits -system.cpu1.dtb.misses 7089 # DTB misses -system.cpu1.dtb.accesses 16162839 # DTB accesses +system.cpu1.dtb.hits 14151364 # DTB hits +system.cpu1.dtb.misses 5078 # DTB misses +system.cpu1.dtb.accesses 14156442 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1372,8 +1431,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 38008437 # ITB inst hits -system.cpu1.itb.inst_misses 3017 # ITB inst misses +system.cpu1.itb.inst_hits 33205963 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1382,95 +1441,129 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1485 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 38011454 # ITB inst accesses -system.cpu1.itb.hits 38008437 # DTB hits -system.cpu1.itb.misses 3017 # DTB misses -system.cpu1.itb.accesses 38011454 # DTB accesses -system.cpu1.numCycles 2392450295 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 33208134 # ITB inst accesses +system.cpu1.itb.hits 33205963 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 33208134 # DTB accesses +system.cpu1.numCycles 2390414629 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 37097446 # Number of instructions committed -system.cpu1.committedOps 46867102 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 42687988 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5457 # Number of float alu accesses -system.cpu1.num_func_calls 1134316 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4357000 # number of instructions that are conditional controls -system.cpu1.num_int_insts 42687988 # number of integer instructions -system.cpu1.num_fp_insts 5457 # number of float instructions -system.cpu1.num_int_register_reads 248074220 # number of times the integer registers were read -system.cpu1.num_int_register_writes 45509439 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3577 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1884 # number of times the floating registers were written -system.cpu1.num_mem_refs 16770062 # number of memory refs -system.cpu1.num_load_insts 9887948 # Number of load instructions -system.cpu1.num_store_insts 6882114 # Number of store instructions -system.cpu1.num_idle_cycles 1855714829.552449 # Number of idle cycles -system.cpu1.num_busy_cycles 536735465.447551 # Number of busy cycles -system.cpu1.not_idle_fraction 0.224346 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.775654 # Percentage of idle cycles -system.cpu1.Branches 5771094 # Number of branches fetched +system.cpu1.committedInsts 32594861 # Number of instructions committed +system.cpu1.committedOps 41116735 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37639270 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 962738 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3734786 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37639270 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 218315433 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39777331 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14690124 # number of memory refs +system.cpu1.num_load_insts 8639728 # Number of load instructions +system.cpu1.num_store_insts 6050396 # Number of store instructions +system.cpu1.num_idle_cycles 1874297798.309079 # Number of idle cycles +system.cpu1.num_busy_cycles 516116830.690921 # Number of busy cycles +system.cpu1.not_idle_fraction 0.215911 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.784089 # Percentage of idle cycles +system.cpu1.Branches 4947313 # Number of branches fetched +system.cpu1.op_class::No_OpClass 14267 0.03% 0.03% # Class of executed instruction +system.cpu1.op_class::IntAlu 26968126 64.63% 64.67% # Class of executed instruction +system.cpu1.op_class::IntMult 50231 0.12% 64.79% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1470 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.79% # Class of executed instruction +system.cpu1.op_class::MemRead 8639728 20.71% 85.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 6050396 14.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 41724218 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 52097 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 540849 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.554171 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 37467072 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 541361 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.209034 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 94011084500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.554171 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934676 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934676 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 44363 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 469889 # number of replacements +system.cpu1.icache.tags.tagsinuse 478.549875 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32735558 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 470401 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 69.590749 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 93998064500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.549875 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934668 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.934668 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 203 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 38549794 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 38549794 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 37467072 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 37467072 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 37467072 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 37467072 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 37467072 # number of overall hits -system.cpu1.icache.overall_hits::total 37467072 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 541361 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 541361 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 541361 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 541361 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 541361 # number of overall misses -system.cpu1.icache.overall_misses::total 541361 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7383473218 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7383473218 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7383473218 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7383473218 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7383473218 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7383473218 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 38008433 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 38008433 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 38008433 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 38008433 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 38008433 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 38008433 # 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Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.340913 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920588 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920588 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 49486795 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 49486795 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6952689 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6952689 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4832965 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4832965 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 82012 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 82012 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82761 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 82761 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11785654 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11785654 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11785654 # number of overall hits +system.cpu1.dcache.overall_hits::total 11785654 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 170655 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 170655 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 150219 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 150219 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11301 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11301 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10073 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10073 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 320874 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 320874 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 320874 # number of overall misses +system.cpu1.dcache.overall_misses::total 320874 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2212742497 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2212742497 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 6365695527 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 6365695527 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 97206750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 97206750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 52182477 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 52182477 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 8578438024 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8578438024 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8578438024 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8578438024 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7123344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7123344 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4983184 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4983184 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93313 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 93313 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92834 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92834 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12106528 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12106528 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12106528 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12106528 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023957 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.023957 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030145 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.030145 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121109 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121109 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108506 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026504 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.026504 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026504 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.026504 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12966.174428 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12966.174428 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 42376.101072 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 42376.101072 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8601.606053 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8601.606053 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5180.430557 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5180.430557 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26734.599949 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26734.599949 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26734.599949 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 26734.599949 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1608,62 +1700,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 315335 # number of writebacks -system.cpu1.dcache.writebacks::total 315335 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 207066 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 207066 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 165297 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 165297 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11987 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11987 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9883 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 372363 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 372363 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 372363 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 372363 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2282040250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2282040250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6506824958 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6506824958 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 83489000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83489000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31075041 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31075041 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8788865208 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8788865208 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8788865208 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8788865208 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169960243250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169960243250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25194386277 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25194386277 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195154629527 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195154629527 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.024992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028607 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106453 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106453 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.088088 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.088088 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026477 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026477 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026477 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11020.835144 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11020.835144 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39364.446772 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39364.446772 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6964.962042 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6964.962042 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3144.292320 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3144.292320 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23602.949831 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23602.949831 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 265286 # number of writebacks +system.cpu1.dcache.writebacks::total 265286 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170655 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170655 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150219 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150219 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11301 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11301 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10070 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10070 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320874 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320874 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320874 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320874 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1870737503 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1870737503 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6042583473 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6042583473 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74594250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74594250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32041523 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32041523 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7913320976 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7913320976 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7913320976 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7913320976 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168608523750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168608523750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187494163 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187494163 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193796017913 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193796017913 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023957 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023957 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.121109 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.121109 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108473 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108473 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026504 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026504 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026504 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10962.101919 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10962.101919 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40225.161085 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40225.161085 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6600.676931 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6600.676931 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3181.879146 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3181.879146 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24661.770589 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24661.770589 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1687,10 +1779,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 746722879500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 746722879500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 746722879500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 746722879500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745373562750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 745373562750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745373562750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 745373562750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 823848f29..41f066b07 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,134 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616536 # Number of seconds simulated -sim_ticks 2616536215000 # Number of ticks simulated -final_tick 2616536215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616230 # Number of seconds simulated +sim_ticks 2616229847000 # Number of ticks simulated +final_tick 2616229847000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594955 # Simulator instruction rate (inst/s) -host_op_rate 757104 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25859148121 # Simulator tick rate (ticks/s) -host_mem_usage 420956 # Number of bytes of host memory used -host_seconds 101.18 # Real time elapsed on the host -sim_insts 60200059 # Number of instructions simulated -sim_ops 76606878 # Number of ops (including micro ops) simulated +host_inst_rate 375445 # Simulator instruction rate (inst/s) +host_op_rate 477768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 16316419265 # Simulator tick rate (ticks/s) +host_mem_usage 464828 # Number of bytes of host memory used +host_seconds 160.34 # Real time elapsed on the host +sim_insts 60200042 # Number of instructions simulated +sim_ops 76606857 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 703944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9089816 # Number of bytes read from this memory -system.physmem.bytes_read::total 132477600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 703944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 703944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3706240 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 703560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9089944 # Number of bytes read from this memory +system.physmem.bytes_read::total 132477344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 703560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 703560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3706304 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6722312 # Number of bytes written to this memory +system.physmem.bytes_written::total 6722376 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17211 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142064 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494706 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57910 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17205 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142066 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494702 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57911 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811928 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46887710 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811929 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46893201 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3473988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50630906 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1416468 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1152696 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2569165 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1416468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46887710 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 268921 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3474444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50636737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 268921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268921 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1416658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1152831 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2569490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1416658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46893201 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4626685 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53200071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494706 # Number of read requests accepted -system.physmem.writeReqs 811928 # Number of write requests accepted -system.physmem.readBursts 15494706 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811928 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991531648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 129536 # Total number of bytes read from write queue -system.physmem.bytesWritten 6740736 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132477600 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6722312 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2024 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706583 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4515 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 967775 # Per bank write bursts +system.physmem.bw_total::cpu.inst 268921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4627275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53206227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494702 # Number of read requests accepted +system.physmem.writeReqs 811929 # Number of write requests accepted +system.physmem.readBursts 15494702 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811929 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991533248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 127680 # Total number of bytes read from write queue +system.physmem.bytesWritten 6729728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132477344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6722376 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1995 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706751 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 967982 # Per bank write bursts system.physmem.perBankRdBursts::1 967715 # Per bank write bursts -system.physmem.perBankRdBursts::2 967672 # Per bank write bursts -system.physmem.perBankRdBursts::3 967748 # Per bank write bursts -system.physmem.perBankRdBursts::4 974561 # Per bank write bursts -system.physmem.perBankRdBursts::5 968173 # Per bank write bursts -system.physmem.perBankRdBursts::6 967769 # Per bank write bursts -system.physmem.perBankRdBursts::7 967703 # Per bank write bursts -system.physmem.perBankRdBursts::8 968545 # Per bank write bursts +system.physmem.perBankRdBursts::2 967669 # Per bank write bursts +system.physmem.perBankRdBursts::3 967754 # Per bank write bursts +system.physmem.perBankRdBursts::4 974564 # Per bank write bursts +system.physmem.perBankRdBursts::5 968184 # Per bank write bursts +system.physmem.perBankRdBursts::6 967779 # Per bank write bursts +system.physmem.perBankRdBursts::7 967692 # Per bank write bursts +system.physmem.perBankRdBursts::8 968544 # Per bank write bursts system.physmem.perBankRdBursts::9 968137 # Per bank write bursts system.physmem.perBankRdBursts::10 967949 # Per bank write bursts system.physmem.perBankRdBursts::11 967746 # Per bank write bursts system.physmem.perBankRdBursts::12 967851 # Per bank write bursts system.physmem.perBankRdBursts::13 967741 # Per bank write bursts system.physmem.perBankRdBursts::14 967800 # Per bank write bursts -system.physmem.perBankRdBursts::15 967797 # Per bank write bursts -system.physmem.perBankWrBursts::0 6510 # Per bank write bursts -system.physmem.perBankWrBursts::1 6313 # Per bank write bursts -system.physmem.perBankWrBursts::2 6323 # Per bank write bursts -system.physmem.perBankWrBursts::3 6241 # Per bank write bursts -system.physmem.perBankWrBursts::4 6804 # Per bank write bursts -system.physmem.perBankWrBursts::5 6995 # Per bank write bursts -system.physmem.perBankWrBursts::6 6800 # Per bank write bursts -system.physmem.perBankWrBursts::7 6791 # Per bank write bursts -system.physmem.perBankWrBursts::8 7084 # Per bank write bursts -system.physmem.perBankWrBursts::9 6747 # Per bank write bursts -system.physmem.perBankWrBursts::10 6568 # Per bank write bursts -system.physmem.perBankWrBursts::11 6457 # Per bank write bursts -system.physmem.perBankWrBursts::12 6495 # Per bank write bursts -system.physmem.perBankWrBursts::13 6295 # Per bank write bursts -system.physmem.perBankWrBursts::14 6428 # Per bank write bursts -system.physmem.perBankWrBursts::15 6473 # Per bank write bursts +system.physmem.perBankRdBursts::15 967600 # Per bank write bursts +system.physmem.perBankWrBursts::0 6503 # Per bank write bursts +system.physmem.perBankWrBursts::1 6305 # Per bank write bursts +system.physmem.perBankWrBursts::2 6309 # Per bank write bursts +system.physmem.perBankWrBursts::3 6231 # Per bank write bursts +system.physmem.perBankWrBursts::4 6800 # Per bank write bursts +system.physmem.perBankWrBursts::5 6982 # Per bank write bursts +system.physmem.perBankWrBursts::6 6786 # Per bank write bursts +system.physmem.perBankWrBursts::7 6777 # Per bank write bursts +system.physmem.perBankWrBursts::8 7080 # Per bank write bursts +system.physmem.perBankWrBursts::9 6733 # Per bank write bursts +system.physmem.perBankWrBursts::10 6548 # Per bank write bursts +system.physmem.perBankWrBursts::11 6441 # Per bank write bursts +system.physmem.perBankWrBursts::12 6486 # Per bank write bursts +system.physmem.perBankWrBursts::13 6281 # Per bank write bursts +system.physmem.perBankWrBursts::14 6425 # Per bank write bursts +system.physmem.perBankWrBursts::15 6465 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2616531854000 # Total gap between requests +system.physmem.totGap 2616225486000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15335424 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152618 # Read request sizes (log2) +system.physmem.readPktSize::6 152614 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57910 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1116573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 960474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 975907 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 963056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 965451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2812276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2805674 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3709925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 42008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 34639 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 36264 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 33338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 31474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57911 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1126567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 970563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976518 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1090618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 986596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1051326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2724005 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2632042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3421723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 136210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 113171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 104737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 101252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -159,45 +171,45 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4827 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1078 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1070 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1059 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -208,140 +220,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 977394 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1014.625651 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1002.644045 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 87.222028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3543 0.36% 0.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3286 0.34% 0.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1787 0.18% 0.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1165 0.12% 1.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 902 0.09% 1.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 711 0.07% 1.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 580 0.06% 1.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 432 0.04% 1.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 964988 98.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 977394 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4784 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3238.435619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 134294.504205 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 4779 99.90% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.06% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.9129e+06-9.43718e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4784 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4784 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.015886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.524536 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.242033 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2224 46.49% 46.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 36 0.75% 47.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 227 4.74% 51.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1224 25.59% 77.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 8 0.17% 77.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 4 0.08% 77.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 77.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.02% 77.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 945 19.75% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 67 1.40% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 15 0.31% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 31 0.65% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4784 # Writes before turning the bus around for reads -system.physmem.totQLat 588095657500 # Total ticks spent queuing -system.physmem.totMemAccLat 694960871250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77463410000 # Total ticks spent in databus transfers -system.physmem.totBankLat 29401803750 # Total ticks spent accessing banks -system.physmem.avgQLat 37959.58 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1897.79 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 1027354 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.683544 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.447521 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.224200 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22943 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22460 2.19% 4.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8461 0.82% 5.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2563 0.25% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2504 0.24% 5.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1783 0.17% 5.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8706 0.85% 6.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 969 0.09% 6.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 956965 93.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1027354 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6094 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2542.286675 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 118884.715097 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6090 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6094 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6094 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.255005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.227328 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.967528 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2261 37.10% 37.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 29 0.48% 37.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3794 62.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 9 0.15% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6094 # Writes before turning the bus around for reads +system.physmem.totQLat 400062590250 # Total ticks spent queuing +system.physmem.totMemAccLat 690550846500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77463535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25822.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44857.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 378.95 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.63 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44572.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 378.99 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.64 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 29.46 # Average write queue length when enqueuing -system.physmem.readRowHits 14490606 # Number of row buffer hits during reads -system.physmem.writeRowHits 90101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.53 # Row buffer hit rate for writes -system.physmem.avgGap 160458.12 # Average gap between requests -system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 3.85 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54116651 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546597 # Transaction distribution -system.membus.trans_dist::ReadResp 16546597 # Transaction distribution +system.physmem.avgRdQLen 6.59 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing +system.physmem.readRowHits 14482119 # Number of row buffer hits during reads +system.physmem.writeRowHits 88386 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.03 # Row buffer hit rate for writes +system.physmem.avgGap 160439.36 # Average gap between requests +system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2245273695250 # Time in different power states +system.physmem.memoryStateTime::REF 87361560000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 283591722250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 54122917 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546592 # Transaction distribution +system.membus.trans_dist::ReadResp 16546592 # Transaction distribution system.membus.trans_dist::WriteReq 763385 # Transaction distribution system.membus.trans_dist::WriteResp 763385 # Transaction distribution -system.membus.trans_dist::Writeback 57910 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution -system.membus.trans_dist::ReadExReq 132217 # Transaction distribution -system.membus.trans_dist::ReadExResp 132217 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383088 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57911 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 132219 # Transaction distribution +system.membus.trans_dist::ReadExResp 132219 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383090 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893535 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280487 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951338 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390542 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34951335 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390546 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516520 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914786 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16516328 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18914598 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141598178 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141598178 # Total data (bytes) +system.membus.tot_pkt_size::total 141597990 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141597990 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206225000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206224000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3615000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3616500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17911294000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17911182500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4951349139 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4951111812 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38238689000 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.5 # Layer utilization (%) +system.membus.respLayer2.occupancy 37928474750 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47801339 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16518785 # Transaction distribution -system.iobus.trans_dist::ReadResp 16518785 # Transaction distribution +system.iobus.throughput 47806938 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16518786 # Transaction distribution +system.iobus.trans_dist::ReadResp 16518786 # Transaction distribution system.iobus.trans_dist::WriteReq 8183 # Transaction distribution system.iobus.trans_dist::WriteResp 8183 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -363,12 +357,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383090 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33053936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33053938 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -390,14 +384,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390542 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390546 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073934 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073934 # Total data (bytes) +system.iobus.tot_pkt_size::total 125073938 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 125073938 # Total data (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -443,9 +437,9 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374905000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374907000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38265059000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38686102250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -471,25 +465,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996179 # DTB read hits -system.cpu.dtb.read_misses 7337 # DTB read misses -system.cpu.dtb.write_hits 11230334 # DTB write hits -system.cpu.dtb.write_misses 2213 # DTB write misses +system.cpu.dtb.read_hits 14996190 # DTB read hits +system.cpu.dtb.read_misses 7339 # DTB read misses +system.cpu.dtb.write_hits 11230344 # DTB write hits +system.cpu.dtb.write_misses 2214 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3411 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003516 # DTB read accesses -system.cpu.dtb.write_accesses 11232547 # DTB write accesses +system.cpu.dtb.read_accesses 15003529 # DTB read accesses +system.cpu.dtb.write_accesses 11232558 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226513 # DTB hits -system.cpu.dtb.misses 9550 # DTB misses -system.cpu.dtb.accesses 26236063 # DTB accesses +system.cpu.dtb.hits 26226534 # DTB hits +system.cpu.dtb.misses 9553 # DTB misses +system.cpu.dtb.accesses 26236087 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -511,7 +505,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61493932 # ITB inst hits +system.cpu.itb.inst_hits 61493913 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -528,88 +522,123 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61498403 # ITB inst accesses -system.cpu.itb.hits 61493932 # DTB hits +system.cpu.itb.inst_accesses 61498384 # ITB inst accesses +system.cpu.itb.hits 61493913 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61498403 # DTB accesses -system.cpu.numCycles 5233072430 # number of cpu cycles simulated +system.cpu.itb.accesses 61498384 # DTB accesses +system.cpu.numCycles 5232459694 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60200059 # Number of instructions committed -system.cpu.committedOps 76606878 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 69208659 # Number of integer alu accesses +system.cpu.committedInsts 60200042 # Number of instructions committed +system.cpu.committedOps 76606857 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 69208585 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 2140468 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948676 # number of instructions that are conditional controls -system.cpu.num_int_insts 69208659 # number of integer instructions +system.cpu.num_conditional_control_insts 7948679 # number of instructions that are conditional controls +system.cpu.num_int_insts 69208585 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 401368432 # number of times the integer registers were read -system.cpu.num_int_register_writes 74518953 # number of times the integer registers were written +system.cpu.num_int_register_reads 401368270 # number of times the integer registers were read +system.cpu.num_int_register_writes 74518872 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394027 # number of memory refs -system.cpu.num_load_insts 15660244 # Number of load instructions -system.cpu.num_store_insts 11733783 # Number of store instructions -system.cpu.num_idle_cycles 4581664281.608249 # Number of idle cycles -system.cpu.num_busy_cycles 651408148.391751 # Number of busy cycles -system.cpu.not_idle_fraction 0.124479 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875521 # Percentage of idle cycles -system.cpu.Branches 10308791 # Number of branches fetched +system.cpu.num_mem_refs 27394017 # number of memory refs +system.cpu.num_load_insts 15660224 # Number of load instructions +system.cpu.num_store_insts 11733793 # Number of store instructions +system.cpu.num_idle_cycles 4581582300.610249 # Number of idle cycles +system.cpu.num_busy_cycles 650877393.389751 # Number of busy cycles +system.cpu.not_idle_fraction 0.124392 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875608 # Percentage of idle cycles +system.cpu.Branches 10308802 # Number of branches fetched +system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 50389316 64.68% 64.72% # Class of executed instruction +system.cpu.op_class::IntMult 87585 0.11% 64.83% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 64.83% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 2109 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction +system.cpu.op_class::MemRead 15660224 20.10% 84.94% # Class of executed instruction +system.cpu.op_class::MemWrite 11733793 15.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 77901545 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83016 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856277 # number of replacements -system.cpu.icache.tags.tagsinuse 510.865256 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60637143 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856789 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.772551 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 20019652250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.865256 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997784 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997784 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 83017 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 856351 # number of replacements +system.cpu.icache.tags.tagsinuse 510.866135 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60637050 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856863 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.766330 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 20005377250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.866135 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997785 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997785 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 267 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 193 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62350721 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62350721 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60637143 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60637143 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60637143 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60637143 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60637143 # number of overall hits -system.cpu.icache.overall_hits::total 60637143 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856789 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856789 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856789 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856789 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856789 # number of overall misses -system.cpu.icache.overall_misses::total 856789 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768796500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11768796500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11768796500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11768796500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11768796500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11768796500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61493932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61493932 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61493932 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61493932 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61493932 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61493932 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.933234 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13735.933234 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13735.933234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.933234 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13735.933234 # average overall miss latency +system.cpu.icache.tags.tag_accesses 62350776 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62350776 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60637050 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60637050 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60637050 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60637050 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60637050 # number of overall hits +system.cpu.icache.overall_hits::total 60637050 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856863 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856863 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856863 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856863 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856863 # number of overall misses +system.cpu.icache.overall_misses::total 856863 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766560750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11766560750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11766560750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11766560750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11766560750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11766560750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61493913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61493913 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61493913 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61493913 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61493913 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61493913 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013934 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013934 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013934 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013934 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013934 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013934 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13732.137751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13732.137751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13732.137751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13732.137751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13732.137751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -618,186 +647,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856789 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856789 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856789 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856789 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856789 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856789 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051259500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10051259500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051259500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10051259500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051259500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10051259500 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57789.039607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57112.457457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57158.658700 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -901,87 +930,87 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626183 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.875243 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23656065 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626695 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.747333 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 671680250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.875243 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999756 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999756 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 626320 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.875633 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655948 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626832 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.738897 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 669376250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.875633 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 97757735 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 97757735 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13196205 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13196205 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972754 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972754 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236397 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236397 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247778 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247778 # 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number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787211 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027144 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027144 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024470 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024470 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045936 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045936 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025991 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025991 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14721.298983 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14721.298983 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46076.167531 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46076.167531 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13872.012827 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13872.012827 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 27408.213044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 27408.213044 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 27408.213044 # average overall miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046036 # 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average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26978.118107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26978.118107 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26978.118107 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -990,54 +1019,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595273 # number of writebacks -system.cpu.dcache.writebacks::total 595273 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368088 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368088 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250156 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250156 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11382 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11382 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618244 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618244 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618244 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618244 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4680319500 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10721268984 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10721268984 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135458250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135458250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15392937734 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15392937734 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15392937734 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15392937734 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058578250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058578250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242925328 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242925328 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301503578 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301503578 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027144 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027144 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024470 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024470 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045936 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045936 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025991 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025991 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12715.218915 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12715.218915 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43878.025052 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43878.025052 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11867.312423 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11867.312423 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25324.420027 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25324.420027 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046036 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046036 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025995 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025995 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025995 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12687.994302 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12687.994302 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42858.161011 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42858.161011 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11875.010958 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11875.010958 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24893.447164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24893.447164 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1045,37 +1074,37 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52967752 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2454681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2454681 # Transaction distribution +system.cpu.toL2Bus.throughput 52982138 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2454896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2454896 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763385 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763385 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595273 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2931 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247225 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247225 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749577 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12461 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27438 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7514680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54756316 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83620422 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14140 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138425734 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138425734 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166308 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3008713250 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 595396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2928 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2928 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247229 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247229 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725354 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5749970 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12465 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27449 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7515238 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54761180 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83637066 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14156 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138447274 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138447274 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 166176 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3009006000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1295332250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1295477750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533285861 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533767938 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 18724250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 18731500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use @@ -1093,10 +1122,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1763840630000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1763840630000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1763840630000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1759698189250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759698189250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1759698189250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index e35c391b5..203fb6e65 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,103 +4,103 @@ sim_seconds 2.332812 # Nu sim_ticks 2332811899500 # Number of ticks simulated final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1003640 # Simulator instruction rate (inst/s) -host_op_rate 1290613 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38755909714 # Simulator tick rate (ticks/s) -host_mem_usage 421296 # Number of bytes of host memory used -host_seconds 60.19 # Real time elapsed on the host +host_inst_rate 860450 # Simulator instruction rate (inst/s) +host_op_rate 1106481 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33226597982 # Simulator tick rate (ticks/s) +host_mem_usage 465868 # Number of bytes of host memory used +host_seconds 70.21 # Real time elapsed on the host sim_insts 60411489 # Number of instructions simulated sim_ops 77685090 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 492808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6490328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6490264 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 212352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2581740 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2581696 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 492808 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 212352 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3703360 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1405780 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1610064 # Number of bytes written to this memory -system.physmem.bytes_written::total 6719076 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1610036 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719176 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 13912 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 101447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 101446 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 3318 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 40350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118200 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 40339 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57865 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 351445 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 402516 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811824 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 402509 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811819 # Number of write requests responded to by this memory system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 82 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 211251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2782191 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2782163 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 91028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1106707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52062017 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1106688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 211251 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 91028 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587454 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587509 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 602612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 690182 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880248 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587454 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 690170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880291 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587509 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 211251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3384803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3384775 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 91028 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1796889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54942264 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55969745 # Throughput (bytes/s) -system.membus.data_through_bus 130566887 # Total data (bytes) +system.physmem.bw_total::cpu1.data 1796858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942261 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55969742 # Throughput (bytes/s) +system.membus.data_through_bus 130566879 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62244 # number of replacements -system.l2c.tags.tagsinuse 50006.487761 # Cycle average of tags in use -system.l2c.tags.total_refs 1678458 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127629 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.151071 # Average number of references to valid blocks. +system.l2c.tags.replacements 62245 # number of replacements +system.l2c.tags.tagsinuse 50006.493098 # Cycle average of tags in use +system.l2c.tags.total_refs 1678467 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127630 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151038 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.766383 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 36901.760029 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993822 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.inst 4918.263908 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3149.549186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3148.560878 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 2096.452041 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.data 2939.468488 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::writebacks 0.563076 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.075047 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.031989 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.044853 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.763038 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763039 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id @@ -111,19 +111,19 @@ system.l2c.tags.age_task_id_blocks_1024::3 9187 # system.l2c.tags.age_task_id_blocks_1024::4 52391 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17104555 # Number of tag accesses -system.l2c.tags.data_accesses 17104555 # Number of data accesses +system.l2c.tags.tag_accesses 17104618 # Number of tag accesses +system.l2c.tags.data_accesses 17104618 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 9008 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3279 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 473060 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 196973 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 196974 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 4855 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2031 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 365811 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 169795 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1224812 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 592687 # number of Writeback hits -system.l2c.Writeback_hits::total 592687 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.data 169798 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1224816 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592692 # number of Writeback hits +system.l2c.Writeback_hits::total 592692 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits @@ -133,28 +133,28 @@ system.l2c.ReadExReq_hits::total 113738 # nu system.l2c.demand_hits::cpu0.dtb.walker 9008 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3279 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 473060 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 260317 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 260318 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 4855 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2031 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 365811 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 220189 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338550 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 220192 # number of demand (read+write) hits +system.l2c.demand_hits::total 1338554 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 9008 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3279 # number of overall hits system.l2c.overall_hits::cpu0.inst 473060 # number of overall hits -system.l2c.overall_hits::cpu0.data 260317 # number of overall hits +system.l2c.overall_hits::cpu0.data 260318 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 4855 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2031 # number of overall hits system.l2c.overall_hits::cpu1.inst 365811 # number of overall hits -system.l2c.overall_hits::cpu1.data 220189 # number of overall hits -system.l2c.overall_hits::total 1338550 # number of overall hits +system.l2c.overall_hits::cpu1.data 220192 # number of overall hits +system.l2c.overall_hits::total 1338554 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 7286 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5804 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5803 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 3318 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 4068 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20481 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1525 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1394 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses @@ -164,17 +164,17 @@ system.l2c.ReadExReq_misses::total 133474 # nu system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 7286 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 102226 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 102225 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 3318 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 41120 # number of demand (read+write) misses -system.l2c.demand_misses::total 153955 # number of demand (read+write) misses +system.l2c.demand_misses::total 153954 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses system.l2c.overall_misses::cpu0.inst 7286 # number of overall misses -system.l2c.overall_misses::cpu0.data 102226 # number of overall misses +system.l2c.overall_misses::cpu0.data 102225 # number of overall misses system.l2c.overall_misses::cpu1.inst 3318 # number of overall misses system.l2c.overall_misses::cpu1.data 41120 # number of overall misses -system.l2c.overall_misses::total 153955 # number of overall misses +system.l2c.overall_misses::total 153954 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 9010 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3282 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 480346 # number of ReadReq accesses(hits+misses) @@ -182,10 +182,10 @@ system.l2c.ReadReq_accesses::cpu0.data 202777 # nu system.l2c.ReadReq_accesses::cpu1.dtb.walker 4855 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2031 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 369129 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 173863 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1245293 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 592687 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 592687 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 173866 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1245296 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592692 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592692 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1537 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1408 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) @@ -199,8 +199,8 @@ system.l2c.demand_accesses::cpu0.data 362543 # nu system.l2c.demand_accesses::cpu1.dtb.walker 4855 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2031 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 369129 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 261309 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492505 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 261312 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492508 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 9010 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 3282 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.inst 480346 # number of overall (read+write) accesses @@ -208,15 +208,15 @@ system.l2c.overall_accesses::cpu0.data 362543 # nu system.l2c.overall_accesses::cpu1.dtb.walker 4855 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2031 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 369129 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 261309 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492505 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 261312 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492508 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000914 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.015168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.028623 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028618 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.008989 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.023398 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016447 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.023397 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016446 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992193 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990057 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses @@ -226,17 +226,17 @@ system.l2c.ReadExReq_miss_rate::total 0.539917 # mi system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000914 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.015168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.281969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281967 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.008989 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.157362 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103152 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.157360 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103151 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000222 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000914 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.015168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.281969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281967 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.008989 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.157362 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103152 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.157360 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103151 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,8 +245,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57863 # number of writebacks -system.l2c.writebacks::total 57863 # number of writebacks +system.l2c.writebacks::writebacks 57865 # number of writebacks +system.l2c.writebacks::total 57865 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -254,8 +254,8 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59119535 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137914755 # Total data (bytes) +system.toL2Bus.throughput 59119724 # Throughput (bytes/s) +system.toL2Bus.data_through_bus 137915195 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) system.iobus.throughput 48895283 # Throughput (bytes/s) system.iobus.data_through_bus 114063499 # Total data (bytes) @@ -366,6 +366,41 @@ system.cpu0.num_busy_cycles 75843061.764530 # system.cpu0.not_idle_fraction 0.016397 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.983603 # Percentage of idle cycles system.cpu0.Branches 5613326 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16463 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 26898614 64.08% 64.12% # Class of executed instruction +system.cpu0.op_class::IntMult 45874 0.11% 64.23% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.23% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1340 0.00% 64.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 64.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.24% # Class of executed instruction +system.cpu0.op_class::MemRead 8305325 19.79% 84.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 6706507 15.98% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 41974123 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed system.cpu0.icache.tags.replacements 850590 # number of replacements @@ -432,14 +467,14 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623340 # number of replacements +system.cpu0.dcache.tags.replacements 623343 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628946 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623852 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875884 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23628961 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875726 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291431 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705599 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.291422 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.705608 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881429 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118566 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -448,59 +483,59 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 278 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 97635044 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 97635044 # Number of data accesses +system.cpu0.dcache.tags.tag_accesses 97635119 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97635119 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6996051 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6184470 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13180521 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6184476 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13180527 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5775160 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4187066 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9962226 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4187070 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9962230 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139339 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96697 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236036 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 96699 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236038 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 145986 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101232 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247218 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 101235 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits system.cpu0.dcache.demand_hits::cpu0.data 12771211 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10371536 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23142747 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10371546 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 23142757 # number of demand (read+write) hits system.cpu0.dcache.overall_hits::cpu0.data 12771211 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10371536 # number of overall hits -system.cpu0.dcache.overall_hits::total 23142747 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10371546 # number of overall hits +system.cpu0.dcache.overall_hits::total 23142757 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 196129 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 169328 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 365457 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 169330 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 365459 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 161303 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 88854 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 250157 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6648 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4535 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4536 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11184 # number of LoadLockedReq misses system.cpu0.dcache.demand_misses::cpu0.data 357432 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 258182 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 615614 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 258184 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 615616 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 357432 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 258182 # number of overall misses -system.cpu0.dcache.overall_misses::total 615614 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 258184 # number of overall misses +system.cpu0.dcache.overall_misses::total 615616 # number of overall misses system.cpu0.dcache.ReadReq_accesses::cpu0.data 7192180 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353798 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13545978 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6353806 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13545986 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5936463 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275920 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10212383 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4275924 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 145987 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101232 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247219 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 101235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 145986 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101232 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247218 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 101235 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.demand_accesses::cpu0.data 13128643 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10629718 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 23758361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10629730 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23758373 # number of demand (read+write) accesses system.cpu0.dcache.overall_accesses::cpu0.data 13128643 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10629718 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 23758361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10629730 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23758373 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027270 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026650 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses @@ -508,14 +543,14 @@ system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027172 system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020780 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045538 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044798 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044807 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045239 # miss rate for LoadLockedReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027225 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024289 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025911 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027225 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.024289 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.025911 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -524,8 +559,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 592687 # number of writebacks -system.cpu0.dcache.writebacks::total 592687 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 592692 # number of writebacks +system.cpu0.dcache.writebacks::total 592692 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -634,6 +669,41 @@ system.cpu1.num_busy_cycles 69683264.930565 # system.cpu1.not_idle_fraction 0.016273 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.983727 # Percentage of idle cycles system.cpu1.Branches 4685935 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12055 0.03% 0.03% # Class of executed instruction +system.cpu1.op_class::IntAlu 23438937 65.39% 65.42% # Class of executed instruction +system.cpu1.op_class::IntMult 41906 0.12% 65.54% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 777 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.54% # Class of executed instruction +system.cpu1.op_class::MemRead 7334763 20.46% 86.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 5015826 13.99% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 35844264 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 291aa5d2a..07ebe167c 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112126 # Nu sim_ticks 5112126264500 # Number of ticks simulated final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1019778 # Simulator instruction rate (inst/s) -host_op_rate 2087932 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26075321841 # Simulator tick rate (ticks/s) -host_mem_usage 640200 # Number of bytes of host memory used -host_seconds 196.05 # Real time elapsed on the host +host_inst_rate 1285356 # Simulator instruction rate (inst/s) +host_op_rate 2631685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32866027497 # Simulator tick rate (ticks/s) +host_mem_usage 626676 # Number of bytes of host memory used +host_seconds 155.54 # Real time elapsed on the host sim_insts 199929810 # Number of instructions simulated sim_ops 409343850 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -141,6 +141,41 @@ system.cpu.num_busy_cycles 453735690.308166 system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles system.cpu.idle_fraction 0.955622 # Percentage of idle cycles system.cpu.Branches 43125514 # Number of branches fetched +system.cpu.op_class::No_OpClass 175310 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373241321 91.18% 91.22% # Class of executed instruction +system.cpu.op_class::IntMult 144368 0.04% 91.26% # Class of executed instruction +system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction +system.cpu.op_class::MemRead 27238816 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8422097 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 409344880 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu.icache.tags.replacements 790558 # number of replacements diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 03f4934d5..60b3a8779 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.200402 # Number of seconds simulated -sim_ticks 5200402495000 # Number of ticks simulated -final_tick 5200402495000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.200396 # Number of seconds simulated +sim_ticks 5200396150000 # Number of ticks simulated +final_tick 5200396150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1256922 # Simulator instruction rate (inst/s) -host_op_rate 2423033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50949381192 # Simulator tick rate (ticks/s) -host_mem_usage 591984 # Number of bytes of host memory used -host_seconds 102.07 # Real time elapsed on the host -sim_insts 128294014 # Number of instructions simulated -sim_ops 247318948 # Number of ops (including micro ops) simulated +host_inst_rate 778841 # Simulator instruction rate (inst/s) +host_op_rate 1501355 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31560622919 # Simulator tick rate (ticks/s) +host_mem_usage 627712 # Number of bytes of host memory used +host_seconds 164.77 # Real time elapsed on the host +sim_insts 128333376 # Number of instructions simulated +sim_ops 247385531 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 2869888 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 2886336 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 826752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8970624 # Number of bytes read from this memory -system.physmem.bytes_read::total 12667648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 826752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 826752 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8094016 # Number of bytes written to this memory -system.physmem.bytes_written::total 8094016 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 44842 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu.inst 825216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8967296 # Number of bytes read from this memory +system.physmem.bytes_read::total 12679232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 825216 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 825216 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8106560 # Number of bytes written to this memory +system.physmem.bytes_written::total 8106560 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 45099 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12918 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140166 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197932 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126469 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126469 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 551859 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu.inst 12894 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140114 # Number of read requests responded to by this memory +system.physmem.num_reads::total 198113 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126665 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126665 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 555022 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 158978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1724986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2435898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 158978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 158978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1556421 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1556421 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1556421 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 551859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 158683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1724349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2438128 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 158683 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 158683 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1558835 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 555022 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 158978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1724986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3992319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197932 # Number of read requests accepted -system.physmem.writeReqs 126469 # Number of write requests accepted -system.physmem.readBursts 197932 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 126469 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12654528 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 13120 # Total number of bytes read from write queue -system.physmem.bytesWritten 8092032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12667648 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8094016 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 205 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 158683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1724349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3996963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198113 # Number of read requests accepted +system.physmem.writeReqs 126665 # Number of write requests accepted +system.physmem.readBursts 198113 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 126665 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue +system.physmem.bytesWritten 8105536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12679232 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8106560 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1622 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12706 # Per bank write bursts -system.physmem.perBankRdBursts::1 12058 # Per bank write bursts -system.physmem.perBankRdBursts::2 12568 # Per bank write bursts -system.physmem.perBankRdBursts::3 12134 # Per bank write bursts -system.physmem.perBankRdBursts::4 12521 # Per bank write bursts -system.physmem.perBankRdBursts::5 12218 # Per bank write bursts -system.physmem.perBankRdBursts::6 12048 # Per bank write bursts -system.physmem.perBankRdBursts::7 12245 # Per bank write bursts -system.physmem.perBankRdBursts::8 12013 # Per bank write bursts -system.physmem.perBankRdBursts::9 12113 # Per bank write bursts -system.physmem.perBankRdBursts::10 12409 # Per bank write bursts -system.physmem.perBankRdBursts::11 12495 # Per bank write bursts -system.physmem.perBankRdBursts::12 12992 # Per bank write bursts -system.physmem.perBankRdBursts::13 12976 # Per bank write bursts -system.physmem.perBankRdBursts::14 12442 # Per bank write bursts -system.physmem.perBankRdBursts::15 11789 # Per bank write bursts -system.physmem.perBankWrBursts::0 8349 # Per bank write bursts -system.physmem.perBankWrBursts::1 7660 # Per bank write bursts -system.physmem.perBankWrBursts::2 8054 # Per bank write bursts -system.physmem.perBankWrBursts::3 7772 # Per bank write bursts -system.physmem.perBankWrBursts::4 8164 # Per bank write bursts -system.physmem.perBankWrBursts::5 7804 # Per bank write bursts -system.physmem.perBankWrBursts::6 7601 # Per bank write bursts -system.physmem.perBankWrBursts::7 7742 # Per bank write bursts -system.physmem.perBankWrBursts::8 7412 # Per bank write bursts -system.physmem.perBankWrBursts::9 7677 # Per bank write bursts -system.physmem.perBankWrBursts::10 8006 # Per bank write bursts -system.physmem.perBankWrBursts::11 7919 # Per bank write bursts -system.physmem.perBankWrBursts::12 8539 # Per bank write bursts -system.physmem.perBankWrBursts::13 8375 # Per bank write bursts -system.physmem.perBankWrBursts::14 8051 # Per bank write bursts -system.physmem.perBankWrBursts::15 7313 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1623 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12177 # Per bank write bursts +system.physmem.perBankRdBursts::1 12548 # Per bank write bursts +system.physmem.perBankRdBursts::2 13053 # Per bank write bursts +system.physmem.perBankRdBursts::3 12620 # Per bank write bursts +system.physmem.perBankRdBursts::4 12592 # Per bank write bursts +system.physmem.perBankRdBursts::5 12288 # Per bank write bursts +system.physmem.perBankRdBursts::6 11961 # Per bank write bursts +system.physmem.perBankRdBursts::7 12236 # Per bank write bursts +system.physmem.perBankRdBursts::8 11972 # Per bank write bursts +system.physmem.perBankRdBursts::9 11957 # Per bank write bursts +system.physmem.perBankRdBursts::10 12338 # Per bank write bursts +system.physmem.perBankRdBursts::11 12177 # Per bank write bursts +system.physmem.perBankRdBursts::12 12807 # Per bank write bursts +system.physmem.perBankRdBursts::13 12813 # Per bank write bursts +system.physmem.perBankRdBursts::14 12433 # Per bank write bursts +system.physmem.perBankRdBursts::15 12012 # Per bank write bursts +system.physmem.perBankWrBursts::0 7757 # Per bank write bursts +system.physmem.perBankWrBursts::1 8145 # Per bank write bursts +system.physmem.perBankWrBursts::2 8603 # Per bank write bursts +system.physmem.perBankWrBursts::3 8164 # Per bank write bursts +system.physmem.perBankWrBursts::4 8201 # Per bank write bursts +system.physmem.perBankWrBursts::5 7973 # Per bank write bursts +system.physmem.perBankWrBursts::6 7511 # Per bank write bursts +system.physmem.perBankWrBursts::7 7789 # Per bank write bursts +system.physmem.perBankWrBursts::8 7356 # Per bank write bursts +system.physmem.perBankWrBursts::9 7523 # Per bank write bursts +system.physmem.perBankWrBursts::10 7874 # Per bank write bursts +system.physmem.perBankWrBursts::11 7684 # Per bank write bursts +system.physmem.perBankWrBursts::12 8313 # Per bank write bursts +system.physmem.perBankWrBursts::13 8300 # Per bank write bursts +system.physmem.perBankWrBursts::14 7968 # Per bank write bursts +system.physmem.perBankWrBursts::15 7488 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 5200402431500 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 5200396086500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 197932 # Read request sizes (log2) +system.physmem.readPktSize::6 198113 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 126469 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 153822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2836 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4526 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3878 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1775 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 994 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 635 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 30 # What read queue length does an incoming req see +system.physmem.writePktSize::6 126665 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 153621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2695 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 4322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 4544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1028 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 834 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,116 +156,112 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1772 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2266 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4927 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5075 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6999 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7801 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2551 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 2242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1928 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 36378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 449.321238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.022911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 400.116091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9783 26.89% 26.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7520 20.67% 47.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3398 9.34% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1958 5.38% 62.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1470 4.04% 66.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 950 2.61% 68.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 669 1.84% 70.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 516 1.42% 72.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10114 27.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 36378 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6806 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.049956 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 579.203336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6805 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::39 1885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 59433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 349.577642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 202.117781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.932182 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20505 34.50% 34.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13774 23.18% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5765 9.70% 67.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3461 5.82% 73.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2240 3.77% 76.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1591 2.68% 79.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1115 1.88% 81.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 921 1.55% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10061 16.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59433 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6976 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.380447 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 572.057676 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6975 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6806 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6806 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.577432 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.979234 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.072144 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 4358 64.03% 64.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 1673 24.58% 88.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 85 1.25% 89.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 45 0.66% 90.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 78 1.15% 91.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 127 1.87% 93.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 53 0.78% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 38 0.56% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 25 0.37% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 74 1.09% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 52 0.76% 97.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 16 0.24% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 72 1.06% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 19 0.28% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 28 0.41% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 13 0.19% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-49 8 0.12% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 5 0.07% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 7 0.10% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 5 0.07% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-57 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::58-59 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-61 1 0.01% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::62-63 5 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-65 13 0.19% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-69 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::74-75 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6806 # Writes before turning the bus around for reads -system.physmem.totQLat 5807464000 # Total ticks spent queuing -system.physmem.totMemAccLat 9465482750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 988635000 # Total ticks spent in databus transfers -system.physmem.totBankLat 2669383750 # Total ticks spent accessing banks -system.physmem.avgQLat 29371.12 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 13500.35 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6976 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6976 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.154960 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.623474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.583584 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 4785 68.59% 68.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 1454 20.84% 89.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 33 0.47% 89.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 125 1.79% 91.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 57 0.82% 92.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 47 0.67% 93.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 75 1.08% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 59 0.85% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 41 0.59% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 19 0.27% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 30 0.43% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 56 0.80% 97.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 145 2.08% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 17 0.24% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-45 4 0.06% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 11 0.16% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-49 3 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::50-51 3 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::54-55 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-69 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6976 # Writes before turning the bus around for reads +system.physmem.totQLat 5514862500 # Total ticks spent queuing +system.physmem.totMemAccLat 9227062500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27855.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47871.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 46605.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s @@ -273,99 +269,103 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.17 # Average write queue length when enqueuing -system.physmem.readRowHits 167067 # Number of row buffer hits during reads -system.physmem.writeRowHits 99118 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.49 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.37 # Row buffer hit rate for writes -system.physmem.avgGap 16030784.22 # Average gap between requests -system.physmem.pageHitRate 82.11 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.28 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 4355532 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623246 # Transaction distribution -system.membus.trans_dist::ReadResp 623246 # Transaction distribution +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing +system.physmem.readRowHits 166366 # Number of row buffer hits during reads +system.physmem.writeRowHits 98833 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes +system.physmem.avgGap 16012156.26 # Average gap between requests +system.physmem.pageHitRate 81.69 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4979189621500 # Time in different power states +system.physmem.memoryStateTime::REF 173652440000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 47553973500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 4356964 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 623381 # Transaction distribution +system.membus.trans_dist::ReadResp 623381 # Transaction distribution system.membus.trans_dist::WriteReq 13777 # Transaction distribution system.membus.trans_dist::WriteResp 13777 # Transaction distribution -system.membus.trans_dist::Writeback 126469 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2149 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1640 # Transaction distribution -system.membus.trans_dist::ReadExReq 159500 # Transaction distribution -system.membus.trans_dist::ReadExResp 159500 # Transaction distribution +system.membus.trans_dist::Writeback 126665 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1641 # Transaction distribution +system.membus.trans_dist::ReadExReq 159285 # Transaction distribution +system.membus.trans_dist::ReadExResp 159285 # Transaction distribution system.membus.trans_dist::MessageReq 1656 # Transaction distribution system.membus.trans_dist::MessageResp 1656 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 139069 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1723230 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580900 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 139322 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1723534 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420233 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14905088 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16571765 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5856576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 5856576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22434965 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22434965 # Total data (bytes) -system.membus.snoop_data_through_bus 215552 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 256796000 # Layer occupancy (ticks) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14912768 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16579445 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5873024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 5873024 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 22459093 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 22459093 # Total data (bytes) +system.membus.snoop_data_through_bus 198848 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 256797000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 359324000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3312000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1349763000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1351243000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2610332746 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2609486505 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 429200500 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 429020250 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47505 # number of replacements -system.iocache.tags.tagsinuse 0.134382 # Cycle average of tags in use +system.iocache.tags.replacements 47501 # number of replacements +system.iocache.tags.tagsinuse 0.128246 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47521 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5049788540000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.134382 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008399 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.008399 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5049779388000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128246 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008015 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.008015 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428040 # Number of tag accesses -system.iocache.tags.data_accesses 428040 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 840 # number of ReadReq misses -system.iocache.ReadReq_misses::total 840 # number of ReadReq misses +system.iocache.tags.tag_accesses 428004 # Number of tag accesses +system.iocache.tags.data_accesses 428004 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses +system.iocache.ReadReq_misses::total 836 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::pc.south_bridge.ide 47560 # number of demand (read+write) misses -system.iocache.demand_misses::total 47560 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 47560 # number of overall misses -system.iocache.overall_misses::total 47560 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 142383686 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 142383686 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12484793248 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 12484793248 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 12627176934 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 12627176934 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 12627176934 # number of overall miss cycles -system.iocache.overall_miss_latency::total 12627176934 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 840 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 840 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses +system.iocache.demand_misses::total 47556 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses +system.iocache.overall_misses::total 47556 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140309686 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 140309686 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12229393602 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 12229393602 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 12369703288 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 12369703288 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 12369703288 # number of overall miss cycles +system.iocache.overall_miss_latency::total 12369703288 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 47560 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 47560 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 47560 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 47560 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -374,40 +374,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 169504.388095 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 169504.388095 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267225.882877 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 267225.882877 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265499.935534 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 265499.935534 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265499.935534 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 265499.935534 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 224342 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167834.552632 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167834.552632 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 261759.280865 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 261759.280865 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 260108.152242 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 260108.152242 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 207651 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 18183 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 17427 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 12.338008 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.915476 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 840 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 840 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 47560 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 47560 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 47560 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 47560 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98678186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 98678186 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10053057748 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 10053057748 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10151735934 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 10151735934 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10151735934 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 10151735934 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96812686 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96812686 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9797946102 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 9797946102 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9894758788 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9894758788 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -416,14 +416,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117474.030952 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 117474.030952 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215176.749743 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 215176.749743 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 213451.134020 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213451.134020 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 213451.134020 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115804.648325 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115804.648325 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 209716.312115 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 209716.312115 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -437,9 +437,9 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 630784 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230145 # Transaction distribution -system.iobus.trans_dist::ReadResp 230145 # Transaction distribution +system.iobus.throughput 630779 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 230141 # Transaction distribution +system.iobus.trans_dist::ReadResp 230141 # Transaction distribution system.iobus.trans_dist::WriteReq 57579 # Transaction distribution system.iobus.trans_dist::WriteResp 57579 # Transaction distribution system.iobus.trans_dist::MessageReq 1656 # Transaction distribution @@ -463,11 +463,11 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578760 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 578752 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -487,13 +487,13 @@ system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280332 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280332 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3953400 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 3280300 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 3280300 # Total data (bytes) +system.iobus.reqLayer0.occupancy 3954900 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -529,98 +529,133 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 425604434 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 424640038 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 53343500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 53686750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10400804990 # number of cpu cycles simulated +system.cpu.numCycles 10400792300 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128294014 # Number of instructions committed -system.cpu.committedOps 247318948 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231911784 # Number of integer alu accesses +system.cpu.committedInsts 128333376 # Number of instructions committed +system.cpu.committedOps 247385531 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231978349 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299833 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23159249 # number of instructions that are conditional controls -system.cpu.num_int_insts 231911784 # number of integer instructions +system.cpu.num_func_calls 2299991 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23168967 # number of instructions that are conditional controls +system.cpu.num_int_insts 231978349 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434400113 # number of times the integer registers were read -system.cpu.num_int_register_writes 197801183 # number of times the integer registers were written +system.cpu.num_int_register_reads 434511356 # number of times the integer registers were read +system.cpu.num_int_register_writes 197852349 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132752064 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95494911 # number of times the CC registers were written -system.cpu.num_mem_refs 22235692 # number of memory refs -system.cpu.num_load_insts 13875118 # Number of load instructions -system.cpu.num_store_insts 8360574 # Number of store instructions -system.cpu.num_idle_cycles 9794078774.998117 # Number of idle cycles -system.cpu.num_busy_cycles 606726215.001883 # Number of busy cycles -system.cpu.not_idle_fraction 0.058335 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.941665 # Percentage of idle cycles -system.cpu.Branches 26297154 # Number of branches fetched +system.cpu.num_cc_register_reads 132811982 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95533715 # number of times the CC registers were written +system.cpu.num_mem_refs 22244872 # number of memory refs +system.cpu.num_load_insts 13879055 # Number of load instructions +system.cpu.num_store_insts 8365817 # Number of store instructions +system.cpu.num_idle_cycles 9793794512.998117 # Number of idle cycles +system.cpu.num_busy_cycles 606997787.001883 # Number of busy cycles +system.cpu.not_idle_fraction 0.058361 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.941639 # Percentage of idle cycles +system.cpu.Branches 26307123 # Number of branches fetched +system.cpu.op_class::No_OpClass 174810 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224704553 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 139755 0.06% 90.96% # Class of executed instruction +system.cpu.op_class::IntDiv 123089 0.05% 91.01% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction +system.cpu.op_class::MemRead 13879055 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8365817 3.38% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 247387079 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 791422 # number of replacements -system.cpu.icache.tags.tagsinuse 510.352385 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144521518 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791934 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.491872 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161455178250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.352385 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996782 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996782 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 791030 # number of replacements +system.cpu.icache.tags.tagsinuse 510.352813 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144579864 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791542 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.655960 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161437750250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.352813 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996783 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996783 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146105400 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146105400 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144521518 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144521518 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144521518 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144521518 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144521518 # number of overall hits -system.cpu.icache.overall_hits::total 144521518 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791941 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791941 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791941 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791941 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791941 # number of overall misses -system.cpu.icache.overall_misses::total 791941 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11119349759 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11119349759 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11119349759 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11119349759 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11119349759 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11119349759 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145313459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145313459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145313459 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145313459 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145313459 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145313459 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005450 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005450 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005450 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005450 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005450 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14040.628985 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14040.628985 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14040.628985 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14040.628985 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14040.628985 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14040.628985 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146162962 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146162962 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144579864 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144579864 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144579864 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144579864 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144579864 # number of overall hits +system.cpu.icache.overall_hits::total 144579864 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 791549 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 791549 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 791549 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 791549 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 791549 # number of overall misses +system.cpu.icache.overall_misses::total 791549 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108553755 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11108553755 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11108553755 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11108553755 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11108553755 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11108553755 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145371413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145371413 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145371413 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145371413 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145371413 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145371413 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005445 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005445 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005445 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005445 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005445 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005445 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14033.943262 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14033.943262 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14033.943262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14033.943262 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -629,88 +664,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791941 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 791941 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 791941 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 791941 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 791941 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 791941 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9530763241 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9530763241 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9530763241 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9530763241 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9530763241 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9530763241 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005450 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005450 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005450 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12034.688494 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12034.688494 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12034.688494 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12034.688494 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12034.688494 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12034.688494 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791549 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 791549 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 791549 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 791549 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 791549 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 791549 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9520697745 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9520697745 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9520697745 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9520697745 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9520697745 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9520697745 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005445 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005445 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005445 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.932251 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.932251 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3448 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.074851 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7916 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3460 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.287861 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5178780288000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.074851 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192178 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.192178 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3407 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.079507 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7935 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3418 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.321533 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5169623666000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.079507 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192469 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.192469 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28763 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28763 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7916 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7916 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28718 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28718 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7937 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7937 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7918 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7918 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7918 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4309 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4309 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4309 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4309 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4309 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4309 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42842750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42842750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42842750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 42842750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42842750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 42842750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7939 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7939 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7939 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7939 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4280 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4280 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4280 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4280 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4280 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4280 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42457500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42457500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42457500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 42457500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42457500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 42457500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352474 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352474 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352417 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.352417 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352417 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.352417 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9942.620097 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9942.620097 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9942.620097 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9942.620097 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9942.620097 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9942.620097 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.350332 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.350332 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.350274 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.350274 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.350274 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.350274 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9919.976636 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9919.976636 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9919.976636 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9919.976636 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -719,86 +754,86 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 776 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 776 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4309 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4309 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4309 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4309 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4309 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4309 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34223750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34223750 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34223750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34223750 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34223750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34223750 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352474 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352474 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352417 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352417 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352417 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352417 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7942.388025 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7942.388025 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7942.388025 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7942.388025 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7942.388025 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7942.388025 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 704 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 704 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4280 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4280 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4280 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4280 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4280 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4280 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33895500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33895500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33895500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33895500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33895500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33895500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.350332 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.350332 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.350274 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.350274 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7919.509346 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 8116 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.061830 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12619 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 8130 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.552153 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5165732872000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061830 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316364 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316364 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 7502 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.061351 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 13282 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7516 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.767163 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5167976228000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061351 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316334 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316334 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 53134 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 53134 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12626 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12626 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12626 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12626 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12626 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12626 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9294 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 9294 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9294 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 9294 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9294 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 9294 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 98603000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 98603000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 98603000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 98603000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 98603000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 98603000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21920 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21920 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21920 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21920 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21920 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21920 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.423996 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.423996 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.423996 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.423996 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.423996 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.423996 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10609.317839 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10609.317839 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10609.317839 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10609.317839 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10609.317839 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10609.317839 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 52668 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52668 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13284 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 13284 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13284 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 13284 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13284 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 13284 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8700 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 8700 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8700 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 8700 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8700 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 8700 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92345000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92345000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92345000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 92345000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92345000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 92345000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21984 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21984 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21984 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21984 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21984 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21984 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395742 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395742 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395742 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395742 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395742 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395742 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10614.367816 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10614.367816 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10614.367816 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10614.367816 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -807,98 +842,98 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 3085 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 3085 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9294 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9294 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9294 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 9294 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9294 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 9294 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 80015000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 80015000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 80015000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 80015000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 80015000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 80015000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.423996 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.423996 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.423996 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.423996 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.423996 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.423996 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8609.317839 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8609.317839 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8609.317839 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8609.317839 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8609.317839 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8609.317839 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3054 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3054 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8700 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8700 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8700 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8700 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8700 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8700 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74944500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74944500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74944500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74944500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74944500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74944500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395742 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395742 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395742 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8614.310345 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1620672 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997242 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20026945 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1621184 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.353283 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 51279250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997242 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1620643 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997078 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20036158 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1621155 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.359187 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997078 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88213750 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88213750 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11989262 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11989262 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8035472 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8035472 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 20024734 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20024734 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20024734 # number of overall hits -system.cpu.dcache.overall_hits::total 20024734 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1308613 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1308613 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 314792 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 314792 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1623405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1623405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1623405 # number of overall misses -system.cpu.dcache.overall_misses::total 1623405 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18824282553 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18824282553 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10745506942 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10745506942 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29569789495 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29569789495 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29569789495 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29569789495 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13297875 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13297875 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8350264 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8350264 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21648139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21648139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21648139 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21648139 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098408 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098408 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037698 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037698 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074991 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074991 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074991 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074991 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14384.911775 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14384.911775 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34135.260559 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34135.260559 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18214.671936 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18214.671936 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18214.671936 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18214.671936 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 88250512 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88250512 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11993410 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11993410 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8040535 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8040535 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 20033945 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20033945 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20033945 # number of overall hits +system.cpu.dcache.overall_hits::total 20033945 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1308416 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1308416 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 314973 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 314973 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1623389 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1623389 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1623389 # number of overall misses +system.cpu.dcache.overall_misses::total 1623389 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18840132304 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18840132304 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10814294936 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10814294936 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29654427240 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29654427240 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29654427240 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29654427240 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13301826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13301826 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8355508 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8355508 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21657334 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21657334 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21657334 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21657334 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098364 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098364 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037696 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037696 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074958 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074958 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074958 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074958 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.191315 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.191315 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.037952 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.037952 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18266.987912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18266.987912 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -907,46 +942,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537729 # number of writebacks -system.cpu.dcache.writebacks::total 1537729 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308613 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26262549505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26262549505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26262549505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26262549505 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 1537613 # number of writebacks +system.cpu.dcache.writebacks::total 1537613 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308416 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1308416 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314973 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 314973 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1623389 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1623389 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623389 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623389 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16214330696 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16214330696 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10132215064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10132215064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26346545760 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 26346545760 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26346545760 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26346545760 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537739500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537739500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752412000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752412000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098408 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098408 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037698 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074991 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12378.291708 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12378.291708 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31970.812657 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31970.812657 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16177.447713 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16177.447713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16177.447713 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16177.447713 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537738000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537738000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752410500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752410500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098364 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098364 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037696 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037696 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.074958 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074958 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12392.335997 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12392.335997 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32168.519410 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32168.519410 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -954,184 +989,184 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49161645 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2696443 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2695917 # Transaction distribution +system.cpu.toL2Bus.throughput 49146383 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2695227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2694701 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13777 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13777 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1541590 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 359301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 312590 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583869 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5973994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7897 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19197 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7584957 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203806901 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 229632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 633792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 255353717 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255333045 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 327296 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3831359500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 1541371 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2213 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 359480 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 312780 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583085 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5973901 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7764 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18139 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7582889 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50658304 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203802165 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 222976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 604096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 255287541 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 255266421 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 314240 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3830515500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 484500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1190263759 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1189702505 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3051445995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3051756740 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6464000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6421000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13941000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13050250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 86417 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64729.830083 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3490254 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151212 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.081859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 86651 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64733.611120 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3487942 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151340 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.047060 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50287.594494 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027550 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141486 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3384.035479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11058.031076 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.767328 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50209.763854 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027833 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141473 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3434.458363 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11089.219598 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.766140 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.051636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.168732 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64795 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2818 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4824 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56981 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.988693 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32189031 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32189031 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6817 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2807 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 779009 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1279777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2068410 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1541590 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1541590 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 307 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 307 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 199552 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 199552 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6817 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2807 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 779009 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1479329 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2267962 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6817 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2807 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 779009 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1479329 # number of overall hits -system.cpu.l2cache.overall_hits::total 2267962 # number of overall hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052406 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.169208 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987757 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64689 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2880 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4787 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56896 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987076 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32180689 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32180689 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6384 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2775 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 778641 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1279470 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2067270 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1541371 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1541371 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 305 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 199944 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 199944 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6384 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 2775 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 778641 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1479414 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2267214 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6384 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 2775 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 778641 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1479414 # number of overall hits +system.cpu.l2cache.overall_hits::total 2267214 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12919 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28035 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 40960 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1395 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1395 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113025 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113025 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12895 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28198 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41099 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1394 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1394 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 112812 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 112812 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12919 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 141060 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 153985 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12895 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141010 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 153911 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12919 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 141060 # number of overall misses -system.cpu.l2cache.overall_misses::total 153985 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 75000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 347500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 948719241 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2091207947 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3040349688 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16786842 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16786842 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7717314435 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7717314435 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 75000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 347500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 948719241 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9808522382 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10757664123 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 75000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 347500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 948719241 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9808522382 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10757664123 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6818 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2812 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 791928 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1307812 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2109370 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1541590 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1541590 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1702 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1702 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000147 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001778 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016313 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021437 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019418 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.819624 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.819624 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361591 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361591 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000147 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001778 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016313 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087053 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063579 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000147 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001778 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016313 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087053 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063579 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60908.410790 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62075.942679 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61707.087695 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10669.445878 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10669.445878 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55774.355806 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55774.355806 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60908.410790 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57026.766043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57352.462103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60908.410790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57026.766043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57352.462103 # average overall mshr miss latency +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371075000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371075000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026944000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026944000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021564 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019493 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820483 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820483 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360703 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360703 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063570 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063570 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.682435 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62319.324207 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61773.596900 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10666.338594 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10666.338594 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56470.916746 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56470.916746 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 813f51271..8539a1890 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu sim_ticks 200409284500 # Number of ticks simulated final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 22333008 # Simulator instruction rate (inst/s) -host_op_rate 22332995 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8544906534 # Simulator tick rate (ticks/s) -host_mem_usage 473604 # Number of bytes of host memory used -host_seconds 23.45 # Real time elapsed on the host +host_inst_rate 14275836 # Simulator instruction rate (inst/s) +host_op_rate 14275831 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5462126987 # Simulator tick rate (ticks/s) +host_mem_usage 513712 # Number of bytes of host memory used +host_seconds 36.69 # Real time elapsed on the host sim_insts 523790075 # Number of instructions simulated sim_ops 523790075 # Number of ops (including micro ops) simulated testsys.voltage_domain.voltage 1 # Voltage in Volts @@ -113,6 +113,41 @@ testsys.cpu.num_busy_cycles 20262547.637842 # testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles testsys.cpu.Branches 2929848 # Number of branches fetched +testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction +testsys.cpu.op_class::IntAlu 12147340 59.95% 63.47% # Class of executed instruction +testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction +testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatAdd 4653 0.02% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatDiv 922 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction +testsys.cpu.op_class::MemRead 4230637 20.88% 84.48% # Class of executed instruction +testsys.cpu.op_class::MemWrite 2319552 11.45% 95.93% # Class of executed instruction +testsys.cpu.op_class::IprAccess 824102 4.07% 100.00% # Class of executed instruction +testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +testsys.cpu.op_class::total 20261680 # Class of executed instruction testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed @@ -336,6 +371,41 @@ drivesys.cpu.num_busy_cycles 19051473.772069 # drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles drivesys.cpu.Branches 2793313 # Number of branches fetched +drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction +drivesys.cpu.op_class::IntAlu 11538630 60.57% 63.84% # Class of executed instruction +drivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction +drivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatAdd 138 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatDiv 23 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdAdd 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdAlu 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdCmp 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdCvt 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdMisc 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdMult 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdShift 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.95% # Class of executed instruction +drivesys.cpu.op_class::MemRead 4026028 21.13% 85.08% # Class of executed instruction +drivesys.cpu.op_class::MemWrite 2085021 10.94% 96.02% # Class of executed instruction +drivesys.cpu.op_class::IprAccess 757336 3.98% 100.00% # Class of executed instruction +drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +drivesys.cpu.op_class::total 19051393 # Class of executed instruction drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.quiesce 19876 # number of quiesce instructions executed drivesys.cpu.kern.inst.hwrei 143591 # number of hwrei instructions executed @@ -455,11 +525,11 @@ sim_seconds 0.000407 # Nu sim_ticks 407341500 # Number of ticks simulated final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 6913599452 # Simulator instruction rate (inst/s) -host_op_rate 6911980937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5373353780 # Simulator tick rate (ticks/s) -host_mem_usage 524140 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 7312019890 # Simulator instruction rate (inst/s) +host_op_rate 7310591323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5683411932 # Simulator tick rate (ticks/s) +host_mem_usage 513712 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 523862353 # Number of instructions simulated sim_ops 523862353 # Number of ops (including micro ops) simulated testsys.voltage_domain.voltage 1 # Voltage in Volts @@ -561,6 +631,41 @@ testsys.cpu.num_busy_cycles 36406.828108 # Nu testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles testsys.cpu.Branches 5238 # Number of branches fetched +testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction +testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction +testsys.cpu.op_class::IntMult 44 0.12% 63.58% # Class of executed instruction +testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatAdd 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatCmp 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatCvt 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatMult 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatDiv 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::FloatSqrt 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdAdd 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdAddAcc 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdAlu 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdCmp 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdCvt 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdMisc 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdMult 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdMultAcc 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdShift 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdShiftAcc 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdSqrt 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatAdd 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatAlu 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatCmp 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatCvt 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatDiv 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.58% # Class of executed instruction +testsys.cpu.op_class::MemRead 7674 21.24% 84.82% # Class of executed instruction +testsys.cpu.op_class::MemWrite 3938 10.90% 95.72% # Class of executed instruction +testsys.cpu.op_class::IprAccess 1545 4.28% 100.00% # Class of executed instruction +testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +testsys.cpu.op_class::total 36126 # Class of executed instruction testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.quiesce 40 # number of quiesce instructions executed testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed @@ -735,6 +840,41 @@ drivesys.cpu.num_busy_cycles 36082.640939 # Nu drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles drivesys.cpu.Branches 5243 # Number of branches fetched +drivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction +drivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction +drivesys.cpu.op_class::IntMult 44 0.12% 63.60% # Class of executed instruction +drivesys.cpu.op_class::IntDiv 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatAdd 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatCmp 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatDiv 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::FloatSqrt 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdAdd 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdAddAcc 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdAlu 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdCmp 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdCvt 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdMisc 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdMult 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdMultAcc 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdShift 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdShiftAcc 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdSqrt 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatAdd 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatAlu 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatCmp 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatCvt 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatDiv 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction +drivesys.cpu.op_class::MemRead 7678 21.24% 84.84% # Class of executed instruction +drivesys.cpu.op_class::MemWrite 3936 10.89% 95.73% # Class of executed instruction +drivesys.cpu.op_class::IprAccess 1545 4.27% 100.00% # Class of executed instruction +drivesys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +drivesys.cpu.op_class::total 36152 # Class of executed instruction drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed |