diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
| commit | b63631536d974f31cf99ee280271dc0f7b4c746f (patch) | |
| tree | ff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/quick/fs | |
| parent | 646c4a23ca44aab5468c896034288151c89be782 (diff) | |
| download | gem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz | |
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
Diffstat (limited to 'tests/quick/fs')
11 files changed, 2308 insertions, 2589 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 59af5be58..101a67dc8 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1416644 # To system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42102082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 7cff7197d..ee54d11d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 469015 # To system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 900001468..b46274bd4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.961841 # Nu sim_ticks 1961841175000 # Number of ticks simulated final_tick 1961841175000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1094895 # Simulator instruction rate (inst/s) -host_op_rate 1094895 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36191186298 # Simulator tick rate (ticks/s) -host_mem_usage 308248 # Number of bytes of host memory used -host_seconds 54.21 # Real time elapsed on the host +host_inst_rate 1272238 # Simulator instruction rate (inst/s) +host_op_rate 1272238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42053157352 # Simulator tick rate (ticks/s) +host_mem_usage 308880 # Number of bytes of host memory used +host_seconds 46.65 # Real time elapsed on the host sim_insts 59351715 # Number of instructions simulated sim_ops 59351715 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 831360 # Number of bytes read from this memory @@ -48,14 +48,15 @@ system.physmem.bw_total::tsunami.ide 1351188 # To system.physmem.bw_total::cpu1.inst 16409 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 146703 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18586263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 448702 # Total number of read requests seen -system.physmem.writeReqs 121037 # Total number of write requests seen -system.physmem.cpureqs 572905 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 448702 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 121037 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 448702 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 121037 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 28716928 # Total number of bytes read from memory system.physmem.bytesWritten 7746368 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28716928 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7746368 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 73 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 3165 # Reqs where no action is needed system.physmem.perBankRdReqs::0 27842 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28115 # Track reads on a per bank basis @@ -332,16 +333,12 @@ system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 902644 system.membus.pkt_count_system.l2c.mem_side::total 941836 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124669 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 39192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1027313 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1066505 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31155200 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::total 31223794 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5308096 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5308096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 68594 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 36463296 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 36531890 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 36531890 # Total data (bytes) system.membus.snoop_data_through_bus 36736 # Total snoop data (bytes) @@ -353,23 +350,23 @@ system.membus.respLayer1.occupancy 3812357322 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 376257250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.l2c.tags.replacements 341780 # number of replacements -system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use -system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy +system.l2c.tags.replacements 341780 # number of replacements +system.l2c.tags.tagsinuse 65282.130402 # Cycle average of tags in use +system.l2c.tags.total_refs 2491702 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406958 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.122750 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8422138750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55415.399962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4783.359658 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4905.357732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 160.897835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 17.115216 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.845572 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.072988 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.074850 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996126 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 908184 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 776732 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 79667 # number of ReadReq hits @@ -652,15 +649,15 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41698 # number of replacements -system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.564923 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1754539957000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.564923 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035308 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035308 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -941,16 +938,16 @@ system.toL2Bus.trans_dist::SCUpgradeReq 894 # Tr system.toL2Bus.trans_dist::UpgradeResp 5142 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 348581 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 307031 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1842377 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 3534341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 160357 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 115223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 5652298 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 58955328 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 137106504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 5131392 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 4050090 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 205243314 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1842377 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3534341 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 160357 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 115223 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5652298 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58955328 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 137106504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 5131392 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4050090 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 205243314 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.data_through_bus 205232754 # Total data (bytes) system.toL2Bus.snoop_data_through_bus 908800 # Total snoop data (bytes) system.toL2Bus.reqLayer0.occupancy 4911962990 # Layer occupancy (ticks) @@ -985,19 +982,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.pkt_count_system.bridge.master::total 39192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 10582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 122652 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) @@ -1014,19 +998,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.tot_pkt_size_system.bridge.master::total 68594 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 42328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 2730242 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2730242 # Total data (bytes) system.iobus.reqLayer0.occupancy 9937000 # Layer occupancy (ticks) @@ -1059,15 +1030,15 @@ system.iobus.respLayer0.occupancy 26795000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 43124750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 920572 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 920572 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.501962 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 53689788 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 921084 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 58.289785 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 39101383250 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.501962 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993168 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.993168 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 53689788 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 53689788 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 53689788 # number of demand (read+write) hits @@ -1137,15 +1108,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 12037.609635 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12037.609635 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 12037.609635 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1349865 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 1349865 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.612721 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13528796 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1350377 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 10.018533 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 105754250 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.612721 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.989478 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 7507195 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7507195 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 5646858 # number of WriteReq hits @@ -1411,15 +1382,15 @@ system.cpu1.kern.mode_ticks::kernel 2892019000 0.15% 0.15% # nu system.cpu1.kern.mode_ticks::user 1487213000 0.08% 0.22% # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 1955685685000 99.78% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 284 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 79630 # number of replacements -system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.replacements 79630 # number of replacements +system.cpu1.icache.tags.tagsinuse 421.213832 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 4672446 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 80140 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 58.303544 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1959882431000 # Cycle when the warmup percentage was hit. system.cpu1.icache.tags.occ_blocks::cpu1.inst 421.213832 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.822683 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.822683 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 4672446 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 4672446 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 4672446 # number of demand (read+write) hits @@ -1489,15 +1460,15 @@ system.cpu1.icache.demand_avg_mshr_miss_latency::total 11492.510608 system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11492.510608 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::total 11492.510608 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 40890 # number of replacements -system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.replacements 40890 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.865345 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 1457107 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 41228 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.342655 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1941571028000 # Cycle when the warmup percentage was hit. system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.865345 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.814190 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.814190 # Average percentage of cache occupancy system.cpu1.dcache.ReadReq_hits::cpu1.data 917421 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 917421 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 531046 # number of WriteReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index fef6394c6..0de871519 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.918473 # Nu sim_ticks 1918473094000 # Number of ticks simulated final_tick 1918473094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 813863 # Simulator instruction rate (inst/s) -host_op_rate 813863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27788392408 # Simulator tick rate (ticks/s) -host_mem_usage 306196 # Number of bytes of host memory used -host_seconds 69.04 # Real time elapsed on the host +host_inst_rate 948634 # Simulator instruction rate (inst/s) +host_op_rate 948634 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 32389976926 # Simulator tick rate (ticks/s) +host_mem_usage 304780 # Number of bytes of host memory used +host_seconds 59.23 # Real time elapsed on the host sim_insts 56188014 # Number of instructions simulated sim_ops 56188014 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory @@ -38,14 +38,15 @@ system.physmem.bw_total::cpu.inst 443419 # To system.physmem.bw_total::cpu.data 12951700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1382533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 18629615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 442977 # Total number of read requests seen -system.physmem.writeReqs 115467 # Total number of write requests seen -system.physmem.cpureqs 558574 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 442977 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 115467 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 442977 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 115467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 28350528 # Total number of bytes read from memory system.physmem.bytesWritten 7389888 # Total number of bytes written to memory system.physmem.bytesConsumedRd 28350528 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 7389888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 50 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 50 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 130 # Reqs where no action is needed system.physmem.perBankRdReqs::0 27963 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 28090 # Track reads on a per bank basis @@ -329,16 +330,12 @@ system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 8 system.membus.pkt_count_system.cpu.l2cache.mem_side::total 910714 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124680 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 1002236 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1035394 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30431296 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30475852 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5309120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 35740416 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 35784972 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 35784972 # Total data (bytes) system.membus.snoop_data_through_bus 35392 # Total snoop data (bytes) @@ -350,15 +347,15 @@ system.membus.respLayer1.occupancy 3745756604 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 376206000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy +system.iocache.tags.replacements 41685 # number of replacements +system.iocache.tags.tagsinuse 1.345474 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 1752558313000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.345474 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084092 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084092 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -644,19 +641,6 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.pkt_count_system.bridge.master::total 33158 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) @@ -673,19 +657,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 2706164 # Total data (bytes) system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) @@ -718,15 +689,15 @@ system.iobus.respLayer0.occupancy 23509000 # La system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 43091000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 928665 # number of replacements -system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928665 # number of replacements +system.cpu.icache.tags.tagsinuse 508.413691 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55270512 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 929176 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.483362 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 38814414250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.413691 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992995 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992995 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 55270512 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 55270512 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 55270512 # number of demand (read+write) hits @@ -796,19 +767,19 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.051020 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.051020 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.051020 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336065 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 336065 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65300.870394 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2448301 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401226 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.102050 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6580892750 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 55613.136753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4759.199410 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4928.534231 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.848589 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072620 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.075203 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996412 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 916024 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 814969 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1730993 # number of ReadReq hits @@ -966,15 +937,15 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390866 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1390866 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.979110 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14050029 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391378 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.097924 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 105729250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.979110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 7815067 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7815067 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 5852671 # number of WriteReq hits @@ -1112,12 +1083,12 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 346045 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 304495 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1858652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3651517 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 5510169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 59476224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 142569036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 202045260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1858652 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3651517 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5510169 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59476224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142569036 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 202045260 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 202035148 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 11392 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 2426591000 # Layer occupancy (ticks) diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 29541c768..ee810dcc9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -66,14 +66,15 @@ system.physmem.bw_total::cpu1.dtb.walker 211 # To system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 486d98045..44e286527 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -49,14 +49,15 @@ system.physmem.bw_total::cpu.itb.walker 82 # To system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 7e08761d9..643b5e070 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,147 +1,148 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194911 # Number of seconds simulated -sim_ticks 1194911360500 # Number of ticks simulated -final_tick 1194911360500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.194884 # Number of seconds simulated +sim_ticks 1194883580500 # Number of ticks simulated +final_tick 1194883580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 773513 # Simulator instruction rate (inst/s) -host_op_rate 985724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15060857671 # Simulator tick rate (ticks/s) -host_mem_usage 403580 # Number of bytes of host memory used -host_seconds 79.34 # Real time elapsed on the host -sim_insts 61369589 # Number of instructions simulated -sim_ops 78206230 # Number of ops (including micro ops) simulated +host_inst_rate 298011 # Simulator instruction rate (inst/s) +host_op_rate 379758 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5802481089 # Simulator tick rate (ticks/s) +host_mem_usage 399660 # Number of bytes of host memory used +host_seconds 205.93 # Real time elapsed on the host +sim_insts 61368273 # Number of instructions simulated +sim_ops 78202205 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 464036 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6626228 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 463716 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6626292 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 256092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2904304 # Number of bytes read from this memory -system.physmem.bytes_read::total 62155620 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 464036 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 2904240 # Number of bytes read from this memory +system.physmem.bytes_read::total 62155300 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 463716 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 256092 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 720128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4136576 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 719808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4136384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 3027304 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7163920 # Number of bytes written to this memory +system.physmem.bytes_written::total 7163728 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13469 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 103607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 103608 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 4083 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 45406 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64634 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 45405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654631 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64631 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 756826 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821470 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43437960 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821467 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43438970 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 388343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 5545372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 388085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 5545554 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 214319 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2430560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52016930 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 388343 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 214319 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 602662 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3461827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 2533497 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 214324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2430563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52017871 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 388085 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 214324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 602408 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3461746 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 2533556 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 33 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5995357 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3461827 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43437960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 5995336 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3461746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43438970 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 388343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 8078869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 388085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 8079110 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 214319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2430594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58012286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654636 # Total number of read requests seen -system.physmem.writeReqs 821470 # Total number of write requests seen -system.physmem.cpureqs 235013 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425896704 # Total number of bytes read from memory -system.physmem.bytesWritten 52574080 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62155620 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7163920 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 138 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 10632 # Reqs where no action is needed +system.physmem.bw_total::cpu1.inst 214324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2430597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58013207 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654631 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 821467 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 6654631 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 821467 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 425896384 # Total number of bytes read from memory +system.physmem.bytesWritten 52573888 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62155300 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7163728 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 531 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 10643 # Reqs where no action is needed system.physmem.perBankRdReqs::0 415730 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 415559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 414961 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 414958 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 415336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 422399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415419 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415520 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415301 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 415351 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 422327 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415446 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 415350 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 415631 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 415270 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 414902 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 414743 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 415547 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 416081 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 415729 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50036 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49924 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51325 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51581 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51435 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51646 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51467 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51592 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51318 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51082 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51567 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51738 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51696 # Track writes on a per bank basis +system.physmem.perBankRdReqs::13 416088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415759 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 415731 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7326 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7216 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6699 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6873 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7393 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6968 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7176 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6994 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 6995 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7264 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6985 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6704 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7238 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 7541 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7391 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7368 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1194906959500 # Total gap between requests +system.physmem.totGap 1194879167500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159747 # Categorize read packet sizes +system.physmem.readPktSize::6 159742 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 64634 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 581277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 421174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 435266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1590102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1186915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1183214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1164468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 10448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 15751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 21053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 15489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4068 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64631 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 586175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 426728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 441027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1598520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1190036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1186243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1162812 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 12576 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17869 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 704 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,31 +157,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see @@ -188,302 +189,282 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 34668 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 13801.223030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 734.240341 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 27780.651463 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 7945 22.92% 22.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 4005 11.55% 34.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2676 7.72% 42.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1963 5.66% 47.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1415 4.08% 51.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1138 3.28% 55.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 895 2.58% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 859 2.48% 60.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 666 1.92% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 565 1.63% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 463 1.34% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 439 1.27% 66.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 280 0.81% 67.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 254 0.73% 67.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 189 0.55% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 312 0.90% 69.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 134 0.39% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 136 0.39% 70.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 130 0.37% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 99 0.29% 70.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 89 0.26% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 164 0.47% 71.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 949 2.74% 74.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 269 0.78% 75.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 135 0.39% 75.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 116 0.33% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 100 0.29% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 85 0.25% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 65 0.19% 76.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 50 0.14% 76.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 50 0.14% 76.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 59 0.17% 77.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 33 0.10% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 32 0.09% 77.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 20 0.06% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 23 0.07% 77.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 11 0.03% 77.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 23 0.07% 77.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 27 0.08% 77.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 12 0.03% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 11 0.03% 77.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 15 0.04% 77.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 7 0.02% 77.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 13 0.04% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 8 0.02% 77.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 13 0.04% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 9 0.03% 77.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 14 0.04% 77.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 9 0.03% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 16 0.05% 77.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 6 0.02% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 9 0.03% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 7 0.02% 77.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 9 0.03% 77.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 6 0.02% 77.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 6 0.02% 77.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 8 0.02% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 9 0.03% 78.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 8 0.02% 78.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 6 0.02% 78.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 7 0.02% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 9 0.03% 78.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 6 0.02% 78.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 45 0.13% 78.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 6 0.02% 78.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 9 0.03% 78.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 2 0.01% 78.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 4 0.01% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 6 0.02% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 78.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 4 0.01% 78.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 3 0.01% 78.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 78.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 5 0.01% 78.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 2 0.01% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 8 0.02% 78.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 3 0.01% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 2 0.01% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 1 0.00% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 1 0.00% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 5 0.01% 78.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 6 0.02% 78.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5823 1 0.00% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 1 0.00% 78.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 6 0.02% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 6 0.02% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 180 0.52% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 1 0.00% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 4 0.01% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6399 1 0.00% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 5 0.01% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 1 0.00% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 1 0.00% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 3 0.01% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 2 0.01% 79.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 21 0.06% 79.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 2 0.01% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 79.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 2 0.01% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7167 2 0.01% 79.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 6 0.02% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 1 0.00% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 1 0.00% 79.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 3 0.01% 79.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 1 0.00% 79.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 3 0.01% 79.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 6 0.02% 79.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 6 0.02% 79.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 7 0.02% 79.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 5 0.01% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 319 0.92% 80.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8511 2 0.01% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-9023 1 0.00% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 2 0.01% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 80.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9535 1 0.00% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9600-9663 1 0.00% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 2 0.01% 80.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 18 0.05% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 2 0.01% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 2 0.01% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11583 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11839 1 0.00% 80.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 2 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12991 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 3 0.01% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 80.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14784-14847 1 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15167 2 0.01% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 3 0.01% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 80.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16703 2 0.01% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16832-16895 1 0.00% 80.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16959 2 0.01% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 2 0.01% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17727 1 0.00% 80.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 2 0.01% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 1 0.00% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18815 1 0.00% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19328-19391 1 0.00% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 4 0.01% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 1 0.00% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20287 1 0.00% 80.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 13 0.04% 80.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-21055 2 0.01% 80.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 2 0.01% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 2 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 2 0.01% 80.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 1 0.00% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 80.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 4 0.01% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24383 2 0.01% 80.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 4 0.01% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25407 1 0.00% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 3 0.01% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25919 1 0.00% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 2 0.01% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 3 0.01% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 2 0.01% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 1 0.00% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29375 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29504-29567 1 0.00% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 3 0.01% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 80.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 2 0.01% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30400-30463 1 0.00% 80.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 3 0.01% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 6 0.02% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31295 2 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 3 0.01% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 2 0.01% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31872-31935 1 0.00% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 80.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 80.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 16 0.05% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33151 1 0.00% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33215 2 0.01% 80.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 36 0.10% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34367 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35584-35647 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35903 1 0.00% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38207 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38463 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39551 1 0.00% 80.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41279 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41344-41407 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 80.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43584-43647 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44607 1 0.00% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45119 1 0.00% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45887 1 0.00% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48703 2 0.01% 80.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50495 2 0.01% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51520-51583 1 0.00% 80.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52287 4 0.01% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52800-52863 1 0.00% 80.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 2 0.01% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55359 1 0.00% 80.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56127 1 0.00% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 2 0.01% 80.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61696-61759 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62080-62143 1 0.00% 81.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62271 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62976-63039 1 0.00% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 2 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64575 2 0.01% 81.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64832-64895 1 0.00% 81.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 6 0.02% 81.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65216-65279 1 0.00% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 1 0.00% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 6196 17.87% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::72768-72831 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::73920-73983 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::75008-75071 1 0.00% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::82944-83007 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::84480-84543 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::85376-85439 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::85568-85631 1 0.00% 98.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::94656-94719 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::95552-95615 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::98944-99007 1 0.00% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::99520-99583 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109120-109183 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109696-109759 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::110080-110143 1 0.00% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::117440-117503 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::117952-118015 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120256-120319 1 0.00% 98.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120640-120703 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121152-121215 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 336 0.97% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196160-196223 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 34155 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 12682.337813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 707.328285 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 25224.390929 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 7803 22.85% 22.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 4015 11.76% 34.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2702 7.91% 42.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1928 5.64% 48.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1397 4.09% 52.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1203 3.52% 55.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 946 2.77% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 826 2.42% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 667 1.95% 62.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 557 1.63% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 438 1.28% 65.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 432 1.26% 67.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 317 0.93% 68.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 252 0.74% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 181 0.53% 69.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 297 0.87% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 146 0.43% 70.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 131 0.38% 70.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 122 0.36% 71.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 99 0.29% 71.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 97 0.28% 71.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 161 0.47% 72.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 728 2.13% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 239 0.70% 75.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 168 0.49% 75.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 146 0.43% 76.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 103 0.30% 76.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 87 0.25% 76.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 68 0.20% 76.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 55 0.16% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 40 0.12% 77.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 46 0.13% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 38 0.11% 77.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 21 0.06% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 23 0.07% 77.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 20 0.06% 77.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 20 0.06% 77.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 20 0.06% 77.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 23 0.07% 77.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 12 0.04% 77.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 19 0.06% 77.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 8 0.02% 77.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 17 0.05% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 10 0.03% 77.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 5 0.01% 78.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 13 0.04% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 2 0.01% 78.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 15 0.04% 78.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 7 0.02% 78.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 12 0.04% 78.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 12 0.04% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 8 0.02% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 8 0.02% 78.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 11 0.03% 78.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 11 0.03% 78.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 6 0.02% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 9 0.03% 78.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 4 0.01% 78.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 5 0.01% 78.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 11 0.03% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 7 0.02% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 32 0.09% 78.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 4 0.01% 78.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 3 0.01% 78.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 5 0.01% 78.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 6 0.02% 78.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 3 0.01% 78.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 3 0.01% 78.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 8 0.02% 78.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 7 0.02% 78.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 5 0.01% 78.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 2 0.01% 78.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 4 0.01% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 4 0.01% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 6 0.02% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 4 0.01% 78.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 78.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 5 0.01% 78.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 2 0.01% 78.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 1 0.00% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 4 0.01% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 2 0.01% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 78.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 3 0.01% 78.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5887 4 0.01% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 1 0.00% 78.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 2 0.01% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 4 0.01% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 5 0.01% 78.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 1 0.00% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 2 0.01% 78.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 2 0.01% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6463 1 0.00% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 2 0.01% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 78.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 4 0.01% 78.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 1 0.00% 78.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 22 0.06% 78.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 3 0.01% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6975 1 0.00% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 5 0.01% 78.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 7 0.02% 78.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7359 3 0.01% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 79.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 79.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 3 0.01% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 3 0.01% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 2 0.01% 79.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 6 0.02% 79.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 7 0.02% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 1 0.00% 79.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 3 0.01% 79.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 9 0.03% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 6 0.02% 79.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 323 0.95% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8319 1 0.00% 80.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 25 0.07% 80.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8575 138 0.40% 80.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 174 0.51% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 2 0.01% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 1 0.00% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8896-8959 1 0.00% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9408-9471 1 0.00% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10047 3 0.01% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 1 0.00% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10815 2 0.01% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 1 0.00% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11327 4 0.01% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11839 2 0.01% 81.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12351 2 0.01% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12607 1 0.00% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12863 3 0.01% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 1 0.00% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 3 0.01% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13631 1 0.00% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14143 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14271 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14911 3 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15167 2 0.01% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15423 5 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15679 1 0.00% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16703 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16959 1 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 4 0.01% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 1 0.00% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 3 0.01% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18751 1 0.00% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-19007 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19199 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 81.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19391 1 0.00% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 3 0.01% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19775 2 0.01% 81.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-20031 2 0.01% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 4 0.01% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21055 1 0.00% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21311 3 0.01% 81.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21567 5 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 1 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 2 0.01% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 3 0.01% 81.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 2 0.01% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25151 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 3 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 2 0.01% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26431 1 0.00% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27199 3 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 4 0.01% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 2 0.01% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 3 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28991 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29503 1 0.00% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 4 0.01% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 3 0.01% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 3 0.01% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 2 0.01% 81.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 3 0.01% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 4 0.01% 81.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 11 0.03% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 42 0.12% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33855 1 0.00% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34111 1 0.00% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34112-34175 1 0.00% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35135 1 0.00% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36927 1 0.00% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37183 1 0.00% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37951 2 0.01% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38207 1 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38975 1 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41535 1 0.00% 81.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42303 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44095 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44863 1 0.00% 81.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45119 2 0.01% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45631 1 0.00% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45887 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46208-46271 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48959 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49215 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49471 1 0.00% 81.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50239 2 0.01% 81.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50688-50751 1 0.00% 81.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51391 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52480-52543 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53055 1 0.00% 81.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53311 2 0.01% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55552-55615 1 0.00% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56128-56191 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57088-57151 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58112-58175 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58431 1 0.00% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59455 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60928-60991 1 0.00% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61503 2 0.01% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61952-62015 1 0.00% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62527 1 0.00% 81.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62720-62783 1 0.00% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63680-63743 1 0.00% 81.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 39 0.11% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 1 0.00% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 6180 18.09% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66880-66943 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::66944-67007 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::67904-67967 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74111 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74175 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 34668 # Bytes accessed per row activation -system.physmem.totQLat 132807422500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 174630638750 # Sum of mem lat for all requests -system.physmem.totBusLat 33272490000 # Total cycles spent in databus access -system.physmem.totBankLat 8550726250 # Total cycles spent in bank access -system.physmem.avgQLat 19957.54 # Average queueing delay per request -system.physmem.avgBankLat 1284.95 # Average bank access latency per request +system.physmem.bytesPerActivate::total 34155 # Bytes accessed per row activation +system.physmem.totQLat 126519681500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 168380906500 # Sum of mem lat for all requests +system.physmem.totBusLat 33270500000 # Total cycles spent in databus access +system.physmem.totBankLat 8590725000 # Total cycles spent in bank access +system.physmem.avgQLat 19013.79 # Average queueing delay per request +system.physmem.avgBankLat 1291.04 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26242.50 # Average memory access latency +system.physmem.avgMemAccLat 25304.84 # Average memory access latency system.physmem.avgRdBW 356.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 44.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 52.02 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.13 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 11.97 # Average write queue length over time -system.physmem.readRowHits 6636574 # Number of row buffer hits during reads -system.physmem.writeRowHits 804724 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.14 # Average read queue length over time +system.physmem.avgWrQLen 14.04 # Average write queue length over time +system.physmem.readRowHits 6636405 # Number of row buffer hits during reads +system.physmem.writeRowHits 97666 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.96 # Row buffer hit rate for writes -system.physmem.avgGap 159830.13 # Average gap between requests +system.physmem.writeRowHitRate 11.89 # Row buffer hit rate for writes +system.physmem.avgGap 159826.58 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -502,298 +483,286 @@ system.realview.nvmem.bw_inst_read::total 57 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60028739 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703151 # Transaction distribution -system.membus.trans_dist::ReadResp 7703151 # Transaction distribution -system.membus.trans_dist::WriteReq 767201 # Transaction distribution -system.membus.trans_dist::WriteResp 767201 # Transaction distribution -system.membus.trans_dist::Writeback 64634 # Transaction distribution -system.membus.trans_dist::UpgradeReq 27614 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16407 # Transaction distribution -system.membus.trans_dist::UpgradeResp 10632 # Transaction distribution -system.membus.trans_dist::ReadExReq 137758 # Transaction distribution +system.membus.throughput 60029719 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7703148 # Transaction distribution +system.membus.trans_dist::ReadResp 7703148 # Transaction distribution +system.membus.trans_dist::WriteReq 767203 # Transaction distribution +system.membus.trans_dist::WriteResp 767203 # Transaction distribution +system.membus.trans_dist::Writeback 64631 # Transaction distribution +system.membus.trans_dist::UpgradeReq 27692 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 16414 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10643 # Transaction distribution +system.membus.trans_dist::ReadExReq 137763 # Transaction distribution system.membus.trans_dist::ReadExResp 137302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382562 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8866 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4358923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1966647 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4359019 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382564 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14942687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 8856 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17335051 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 17335147 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389878 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17415028 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 17732 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19824510 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17414516 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19824014 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2389882 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 69319540 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 17712 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71729022 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71729022 # Total data (bytes) +system.membus.tot_pkt_size::total 71728526 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 71728526 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1208299500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1208318500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9149149500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 7960500 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 7968000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 776500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 777000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 5034294617 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 9149406000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 5034563338 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 14663453747 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 14646378749 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 69629 # number of replacements -system.l2c.tags.tagsinuse 53155.534639 # Cycle average of tags in use -system.l2c.tags.total_refs 1651678 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134776 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.254986 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40041.185718 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667860 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4638.655043 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5789.348152 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001660 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1927.060090 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 756.614595 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.610980 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.070780 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.088338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.011545 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.811089 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1507 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 482925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 242050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 3554 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1806 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 372304 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 110721 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1219492 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 576641 # number of Writeback hits -system.l2c.Writeback_hits::total 576641 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1408 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 418 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1826 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 257 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 96 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65574 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 45429 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 111003 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1507 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 482925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 307624 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 3554 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1806 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 372304 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 156150 # number of demand (read+write) hits -system.l2c.demand_hits::total 1330495 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4625 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1507 # number of overall hits -system.l2c.overall_hits::cpu0.inst 482925 # number of overall hits -system.l2c.overall_hits::cpu0.data 307624 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 3554 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1806 # number of overall hits -system.l2c.overall_hits::cpu1.inst 372304 # number of overall hits -system.l2c.overall_hits::cpu1.data 156150 # number of overall hits -system.l2c.overall_hits::total 1330495 # number of overall hits +system.l2c.tags.replacements 69624 # number of replacements +system.l2c.tags.tagsinuse 53154.717455 # Cycle average of tags in use +system.l2c.tags.total_refs 1650852 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 134785 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 12.248039 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 40039.692381 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.667893 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001521 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4638.680952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5789.816440 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001659 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1927.067698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 756.788910 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.610957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.070781 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.088346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.011548 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.811077 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4524 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1438 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 483013 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 241892 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 3782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1869 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 372280 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 110462 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1219260 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 576006 # number of Writeback hits +system.l2c.Writeback_hits::total 576006 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1292 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 416 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1708 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 100 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 65542 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 45349 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 110891 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4524 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 1438 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 483013 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 307434 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 3782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 372280 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 155811 # number of demand (read+write) hits +system.l2c.demand_hits::total 1330151 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4524 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 1438 # number of overall hits +system.l2c.overall_hits::cpu0.inst 483013 # number of overall hits +system.l2c.overall_hits::cpu0.data 307434 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 3782 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1869 # number of overall hits +system.l2c.overall_hits::cpu1.inst 372280 # number of overall hits +system.l2c.overall_hits::cpu1.data 155811 # number of overall hits +system.l2c.overall_hits::total 1330151 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6837 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9715 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6832 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9716 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 3996 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1891 # number of ReadReq misses -system.l2c.ReadReq_misses::total 22446 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 3988 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu1.data 1890 # number of ReadReq misses +system.l2c.ReadReq_misses::total 22441 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3974 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 3371 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7359 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 387 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 473 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 860 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 95120 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 44595 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139715 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::total 7345 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 385 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 476 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 861 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 95136 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 44603 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139739 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6837 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 104835 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6832 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 104852 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 3996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 46486 # number of demand (read+write) misses -system.l2c.demand_misses::total 162161 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 46493 # number of demand (read+write) misses +system.l2c.demand_misses::total 162180 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6837 # number of overall misses -system.l2c.overall_misses::cpu0.data 104835 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6832 # number of overall misses +system.l2c.overall_misses::cpu0.data 104852 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses system.l2c.overall_misses::cpu1.inst 3996 # number of overall misses -system.l2c.overall_misses::cpu1.data 46486 # number of overall misses -system.l2c.overall_misses::total 162161 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 395750 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.data 46493 # number of overall misses +system.l2c.overall_misses::total 162180 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 687750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 122500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 486019750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 691389999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 482771250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 688091749 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 89250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 282135750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 152148250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1612301249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11489505 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12402970 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 23892475 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1837921 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1069454 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2907375 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6199806193 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2820905645 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9020711838 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 395750 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 282183750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 151111000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1605057249 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 11611000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 12427970 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 24038970 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1906918 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1117452 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3024370 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6193599427 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 2824169884 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9017769311 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 687750 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 122500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 486019750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6891196192 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 482771250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6881691176 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 89250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 282135750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2973053895 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 10633013087 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 395750 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 282183750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2975280884 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 10622826560 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 687750 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 122500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 486019750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6891196192 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 482771250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6881691176 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 89250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 282135750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2973053895 # number of overall miss cycles -system.l2c.overall_miss_latency::total 10633013087 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4629 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 1509 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 489762 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 251765 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 3554 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1807 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 376300 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 112612 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1241938 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 576641 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 576641 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 5396 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3789 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 9185 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 644 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 569 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1213 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 160694 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 90024 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250718 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4629 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 1509 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 489762 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 412459 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 3554 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1807 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 376300 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 202636 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492656 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4629 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 1509 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 489762 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 412459 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 3554 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1807 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 376300 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 202636 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492656 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013960 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038588 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000553 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.016792 # miss rate for ReadReq accesses +system.l2c.overall_miss_latency::cpu1.inst 282183750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2975280884 # number of overall miss cycles +system.l2c.overall_miss_latency::total 10622826560 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1440 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 489845 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 251608 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 3782 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1870 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 376276 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 112352 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1241701 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 576006 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 576006 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3787 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 9053 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 640 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 576 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1216 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 160678 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 89952 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250630 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4528 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1440 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 489845 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 412286 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 3782 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1870 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 376276 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 202304 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492331 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4528 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1440 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 489845 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 412286 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 3782 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1870 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 376276 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 202304 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492331 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001389 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.013947 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038616 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000535 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010620 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.016822 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.018073 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.739066 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.889681 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.801198 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.600932 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.831283 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.708986 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.591932 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.495368 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.557260 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001325 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013960 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.254171 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000553 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010619 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.229406 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.108639 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001325 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013960 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.254171 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000553 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010619 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.229406 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.108639 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 98937.500000 # average ReadReq miss latency +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754652 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.890151 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.811333 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.601562 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.826389 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.708059 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.592091 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.495853 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.557551 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001389 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.013947 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.254319 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000535 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010620 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.229818 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.108676 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000883 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001389 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.013947 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.254319 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000535 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010620 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.229818 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.108676 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 61250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 71086.697382 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 71167.267010 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 70663.239169 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 70820.476431 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70604.542042 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 80459.148599 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71830.225831 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2881.019308 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3679.314743 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 3246.701318 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4749.149871 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2261.002114 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3380.668605 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65178.786722 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63256.096984 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 64565.092066 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 98937.500000 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 70616.554054 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79952.910053 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 71523.428056 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 2921.741319 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3686.730940 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3272.834581 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4953.033766 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2347.588235 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3512.624855 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 65102.583953 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 63317.935655 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 64532.945785 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 71086.697382 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 65733.735794 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 70604.542042 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 63955.898443 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 65570.717293 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 98937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 65500.225429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 171937.500000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 61250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 71086.697382 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 65733.735794 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 70663.239169 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 65632.426430 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 70604.542042 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 63955.898443 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 65570.717293 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 70616.554054 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 63994.168671 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 65500.225429 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -802,8 +771,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 64634 # number of writebacks -system.l2c.writebacks::total 64634 # number of writebacks +system.l2c.writebacks::writebacks 64631 # number of writebacks +system.l2c.writebacks::total 64631 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits @@ -812,149 +781,149 @@ system.l2c.overall_mshr_hits::cpu0.inst 1 # nu system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6836 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9715 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6831 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 9716 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.inst 3996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1891 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 22445 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 3988 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1890 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 22440 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3974 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 3371 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 7359 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 387 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 473 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 860 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 95120 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 44595 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 139715 # number of ReadExReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7345 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 385 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 476 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 861 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 95136 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 44603 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139739 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6836 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 104835 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6831 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 104852 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.inst 3996 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 46486 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 162160 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 46493 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 162179 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6836 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 104835 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6831 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 104852 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.inst 3996 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 46486 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 162160 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 344250 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.data 46493 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 162179 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 635750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 399672500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 568184999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 396501000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 564859249 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 76250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 231686750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 128101750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1328163999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39911983 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33802856 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 73714839 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3872886 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4731473 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 8604359 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5007372803 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2261009853 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7268382656 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 344250 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 231739250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 127085000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1320993999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 39771967 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 33821856 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 73593823 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3851884 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4768975 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 8620859 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5000986069 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 2264195114 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7265181183 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 635750 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 399672500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5575557802 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 396501000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5565845318 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 231686750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2389111603 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 8596546655 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 344250 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 231739250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2391280114 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 8586175182 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 635750 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 97500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 399672500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5575557802 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 396501000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5565845318 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 76250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 231686750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2389111603 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 8596546655 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 340200250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647628243 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 231739250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2391280114 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 8586175182 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 323836500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12647640494 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4849500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070714500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167063392493 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272290763 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486202500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 16758493263 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 340200250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919919006 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154070543500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167046869994 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 16272049535 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 486218500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16758268035 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 323836500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 28919690029 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4849500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556917000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 183821885756 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038588 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016792 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018073 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.739066 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.889681 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.801198 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.600932 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.831283 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708986 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.591932 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495368 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.557260 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.108639 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000864 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001325 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013958 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.254171 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000553 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010619 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.229406 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.108639 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 154556762000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 183805138029 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038616 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.016822 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018072 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754652 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.890151 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.811333 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.601562 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826389 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.708059 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.592091 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.495853 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.557551 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108675 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000883 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001389 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.254319 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000535 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010620 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.229818 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108675 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58485.331858 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 58137.016159 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67742.860920 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59174.159011 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.019809 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.545535 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10016.964126 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10007.457364 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.114165 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10005.068605 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52642.691369 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50700.972149 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 52022.922779 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67240.740741 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 58867.825267 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10008.044036 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.181845 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10019.581076 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.893506 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.855042 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.612079 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 52566.705233 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50763.292021 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 51991.077530 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86062.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 158937.500000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58465.842598 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53184.125550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58044.356610 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53082.872220 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57979.667167 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51394.217678 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 53012.744542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57992.805305 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51433.121416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52942.583084 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -975,62 +944,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 118431561 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2504925 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2504925 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767201 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767201 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 576641 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27027 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 16760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 43787 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 262499 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 262499 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 993555 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2951402 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 5905 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 15026 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 753554 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 2880607 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 6133 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 11768 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7617950 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 31371320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 53730420 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 6036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 18516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 24083596 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 27977862 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 7228 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 14216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 137209194 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 137209194 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4306024 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4767819743 # Layer occupancy (ticks) +system.toL2Bus.throughput 118384606 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2504676 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2504676 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767203 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767203 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 576006 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 26963 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 16769 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 43732 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 262452 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 262452 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 993712 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2951029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5836 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 14921 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 753525 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2879302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6196 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 11995 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7616516 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 31376632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53718524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 5760 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 18112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24082060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 27916814 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7480 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15128 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 137140510 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 137140510 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4315312 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4764811697 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2217282985 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2217607730 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2471819696 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2471552710 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer2.occupancy 4396500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 10398000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 10394000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1697865710 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 1697838714 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 2215426419 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 2214012427 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) system.toL2Bus.respLayer6.occupancy 4326250 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 8214499 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 8213499 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45438010 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671400 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671400 # Transaction distribution +system.iobus.throughput 45439063 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7671399 # Transaction distribution +system.iobus.trans_dist::ReadResp 7671399 # Transaction distribution system.iobus.trans_dist::WriteReq 7946 # Transaction distribution system.iobus.trans_dist::WriteResp 7946 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8060 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -1052,36 +1021,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382564 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382562 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 8062 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358692 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 15358690 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16120 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1103,38 +1048,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389882 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389878 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 16124 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294394 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294394 # Total data (bytes) +system.iobus.tot_pkt_size::total 54294390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 54294390 # Total data (bytes) system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4037000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4036000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1180,15 +1101,15 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374618000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374616000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17765827253 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17783069251 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9651794 # DTB read hits -system.cpu0.dtb.read_misses 3741 # DTB read misses -system.cpu0.dtb.write_hits 7596285 # DTB write hits +system.cpu0.dtb.read_hits 9653247 # DTB read hits +system.cpu0.dtb.read_misses 3738 # DTB read misses +system.cpu0.dtb.write_hits 7597488 # DTB write hits system.cpu0.dtb.write_misses 1585 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -1196,16 +1117,16 @@ system.cpu0.dtb.flush_tlb_mva_asid 1439 # Nu system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1811 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9655535 # DTB read accesses -system.cpu0.dtb.write_accesses 7597870 # DTB write accesses +system.cpu0.dtb.read_accesses 9656985 # DTB read accesses +system.cpu0.dtb.write_accesses 7599073 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17248079 # DTB hits -system.cpu0.dtb.misses 5326 # DTB misses -system.cpu0.dtb.accesses 17253405 # DTB accesses -system.cpu0.itb.inst_hits 43295611 # ITB inst hits +system.cpu0.dtb.hits 17250735 # DTB hits +system.cpu0.dtb.misses 5323 # DTB misses +system.cpu0.dtb.accesses 17256058 # DTB accesses +system.cpu0.itb.inst_hits 43297764 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1222,79 +1143,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 43297816 # ITB inst accesses -system.cpu0.itb.hits 43295611 # DTB hits +system.cpu0.itb.inst_accesses 43299969 # ITB inst accesses +system.cpu0.itb.hits 43297764 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 43297816 # DTB accesses -system.cpu0.numCycles 2389822721 # number of cpu cycles simulated +system.cpu0.itb.accesses 43299969 # DTB accesses +system.cpu0.numCycles 2389767161 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 42568710 # Number of instructions committed -system.cpu0.committedOps 53298123 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 48055390 # Number of integer alu accesses +system.cpu0.committedInsts 42570861 # Number of instructions committed +system.cpu0.committedOps 53303375 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 48060351 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1403445 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5582451 # number of instructions that are conditional controls -system.cpu0.num_int_insts 48055390 # number of integer instructions +system.cpu0.num_func_calls 1403492 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5582702 # number of instructions that are conditional controls +system.cpu0.num_int_insts 48060351 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 272420788 # number of times the integer registers were read -system.cpu0.num_int_register_writes 52266741 # number of times the integer registers were written +system.cpu0.num_int_register_reads 272449792 # number of times the integer registers were read +system.cpu0.num_int_register_writes 52270848 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 18017454 # number of memory refs -system.cpu0.num_load_insts 10035613 # Number of load instructions -system.cpu0.num_store_insts 7981841 # Number of store instructions -system.cpu0.num_idle_cycles 2150296210.870201 # Number of idle cycles -system.cpu0.num_busy_cycles 239526510.129800 # Number of busy cycles -system.cpu0.not_idle_fraction 0.100228 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.899772 # Percentage of idle cycles +system.cpu0.num_mem_refs 18020156 # number of memory refs +system.cpu0.num_load_insts 10037111 # Number of load instructions +system.cpu0.num_store_insts 7983045 # Number of store instructions +system.cpu0.num_idle_cycles 2150298949.878201 # Number of idle cycles +system.cpu0.num_busy_cycles 239468211.121800 # Number of busy cycles +system.cpu0.not_idle_fraction 0.100206 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.899794 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 51308 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 490004 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.392438 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 42805077 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 490516 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 87.265404 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 76030513250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.392438 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994907 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.994907 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 42805077 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 42805077 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 42805077 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 42805077 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 42805077 # number of overall hits -system.cpu0.icache.overall_hits::total 42805077 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 490517 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 490517 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 490517 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 490517 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 490517 # number of overall misses -system.cpu0.icache.overall_misses::total 490517 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6812396235 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6812396235 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6812396235 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6812396235 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6812396235 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6812396235 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 43295594 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 43295594 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 43295594 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 43295594 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 43295594 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 43295594 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011329 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011329 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011329 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011329 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011329 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011329 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13888.195995 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13888.195995 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13888.195995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13888.195995 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13888.195995 # average overall miss latency +system.cpu0.kern.inst.quiesce 51312 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 490078 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.399401 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 42807156 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 490590 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 87.256479 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 76013480250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.399401 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994921 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994921 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 42807156 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 42807156 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 42807156 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 42807156 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 42807156 # number of overall hits +system.cpu0.icache.overall_hits::total 42807156 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 490591 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 490591 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 490591 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 490591 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 490591 # number of overall misses +system.cpu0.icache.overall_misses::total 490591 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6809993230 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6809993230 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6809993230 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6809993230 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6809993230 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6809993230 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 43297747 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 43297747 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 43297747 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 43297747 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 43297747 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 43297747 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011331 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011331 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011331 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011331 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011331 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011331 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13881.202937 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13881.202937 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13881.202937 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13881.202937 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13881.202937 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1303,120 +1224,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490517 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 490517 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 490517 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 490517 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 490517 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 490517 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5828002765 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5828002765 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5828002765 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5828002765 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5828002765 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5828002765 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 431776750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 431776750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 431776750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 431776750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011329 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011329 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011329 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011329 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11881.347160 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11881.347160 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11881.347160 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 490591 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 490591 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 490591 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 490591 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 490591 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 490591 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5825469770 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5825469770 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5825469770 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5825469770 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5825469770 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5825469770 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 415499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 415499500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 415499500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 415499500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011331 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011331 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011331 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011331 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11874.391846 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11874.391846 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11874.391846 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 406612 # number of replacements -system.cpu0.dcache.tags.tagsinuse 470.882465 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 15965290 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 407124 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 39.214809 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 659626250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.882465 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.919692 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.919692 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 9135819 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 9135819 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6493762 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6493762 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156506 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156506 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 158999 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 158999 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 15629581 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 15629581 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 15629581 # number of overall hits -system.cpu0.dcache.overall_hits::total 15629581 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 263761 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 263761 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 176647 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 176647 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9920 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9920 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7375 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7375 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 440408 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 440408 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 440408 # number of overall misses -system.cpu0.dcache.overall_misses::total 440408 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3882137498 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3882137498 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7549327791 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7549327791 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98498000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 98498000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40527887 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 40527887 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11431465289 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11431465289 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11431465289 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11431465289 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 9399580 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 9399580 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6670409 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6670409 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166426 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 166426 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 16069989 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 16069989 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 16069989 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 16069989 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028061 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.028061 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026482 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.026482 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059606 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059606 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044328 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044328 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027406 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027406 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027406 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.027406 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14718.390884 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14718.390884 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42736.801593 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42736.801593 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9929.233871 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9929.233871 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5495.306712 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5495.306712 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25956.534143 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25956.534143 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25956.534143 # average overall miss latency +system.cpu0.dcache.tags.replacements 406634 # number of replacements +system.cpu0.dcache.tags.tagsinuse 471.214045 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 15967998 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 407146 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 39.219341 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 643231250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.214045 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920340 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.920340 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 9137347 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 9137347 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6494912 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6494912 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156532 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 156532 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159004 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 159004 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 15632259 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 15632259 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 15632259 # number of overall hits +system.cpu0.dcache.overall_hits::total 15632259 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 263669 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 263669 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 176685 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 176685 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9910 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9910 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7384 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7384 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 440354 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 440354 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 440354 # number of overall misses +system.cpu0.dcache.overall_misses::total 440354 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3876875497 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3876875497 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7541622539 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7541622539 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 98733750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 98733750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 40506385 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 40506385 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11418498036 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11418498036 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11418498036 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11418498036 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 9401016 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 9401016 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6671597 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6671597 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 166442 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 166442 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166388 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 166388 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16072613 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16072613 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16072613 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16072613 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028047 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028047 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.026483 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.026483 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059540 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059540 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044378 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044378 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027398 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027398 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027398 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.027398 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14703.569616 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14703.569616 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42683.999994 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42683.999994 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9963.042381 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9963.042381 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5485.696777 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5485.696777 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25930.269819 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25930.269819 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25930.269819 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1425,66 +1346,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 376581 # number of writebacks -system.cpu0.dcache.writebacks::total 376581 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263761 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 263761 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176647 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176647 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9920 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9920 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7371 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7371 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 440408 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 440408 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 440408 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 440408 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3349960502 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3349960502 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7149928209 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7149928209 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78594000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78594000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25787113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25787113 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499888711 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10499888711 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499888711 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10499888711 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764207250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764207250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807935730 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807935730 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39572142980 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39572142980 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028061 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028061 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026482 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026482 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059606 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059606 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044304 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044304 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027406 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027406 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027406 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12700.742346 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12700.742346 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40475.797545 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40475.797545 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7922.782258 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7922.782258 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3498.455162 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3498.455162 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 376568 # number of writebacks +system.cpu0.dcache.writebacks::total 376568 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 263669 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 263669 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176685 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 176685 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9910 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9910 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7379 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7379 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 440354 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 440354 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 440354 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 440354 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3344880503 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3344880503 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7142186461 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7142186461 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 78848250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 78848250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 25751615 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 25751615 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10487066964 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10487066964 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10487066964 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10487066964 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13764220500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13764220500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 25807115461 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 25807115461 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 39571335961 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 39571335961 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.028047 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026483 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026483 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059540 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059540 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044348 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044348 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027398 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027398 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12685.907342 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12685.907342 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40423.275666 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40423.275666 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7956.432896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7956.432896 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3489.851606 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3489.851606 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23841.276069 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23841.276069 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23815.082783 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23815.082783 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1494,26 +1415,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5707792 # DTB read hits -system.cpu1.dtb.read_misses 3579 # DTB read misses -system.cpu1.dtb.write_hits 3874264 # DTB write hits -system.cpu1.dtb.write_misses 643 # DTB write misses +system.cpu1.dtb.read_hits 5705173 # DTB read hits +system.cpu1.dtb.read_misses 3576 # DTB read misses +system.cpu1.dtb.write_hits 3872049 # DTB write hits +system.cpu1.dtb.write_misses 645 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1989 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5711371 # DTB read accesses -system.cpu1.dtb.write_accesses 3874907 # DTB write accesses +system.cpu1.dtb.read_accesses 5708749 # DTB read accesses +system.cpu1.dtb.write_accesses 3872694 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9582056 # DTB hits -system.cpu1.dtb.misses 4222 # DTB misses -system.cpu1.dtb.accesses 9586278 # DTB accesses -system.cpu1.itb.inst_hits 19381456 # ITB inst hits +system.cpu1.dtb.hits 9577222 # DTB hits +system.cpu1.dtb.misses 4221 # DTB misses +system.cpu1.dtb.accesses 9581443 # DTB accesses +system.cpu1.itb.inst_hits 19377969 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1530,79 +1451,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 19383627 # ITB inst accesses -system.cpu1.itb.hits 19381456 # DTB hits +system.cpu1.itb.inst_accesses 19380140 # ITB inst accesses +system.cpu1.itb.hits 19377969 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 19383627 # DTB accesses -system.cpu1.numCycles 2388389320 # number of cpu cycles simulated +system.cpu1.itb.accesses 19380140 # DTB accesses +system.cpu1.numCycles 2388332817 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 18800879 # Number of instructions committed -system.cpu1.committedOps 24908107 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22271769 # Number of integer alu accesses +system.cpu1.committedInsts 18797412 # Number of instructions committed +system.cpu1.committedOps 24898830 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22263010 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 796713 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2514831 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22271769 # number of integer instructions +system.cpu1.num_func_calls 796668 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2514459 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22263010 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 130796956 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23323418 # number of times the integer registers were written +system.cpu1.num_int_register_reads 130745617 # number of times the integer registers were read +system.cpu1.num_int_register_writes 23316317 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 10017504 # number of memory refs -system.cpu1.num_load_insts 5984439 # Number of load instructions -system.cpu1.num_store_insts 4033065 # Number of store instructions -system.cpu1.num_idle_cycles 1968748229.220572 # Number of idle cycles -system.cpu1.num_busy_cycles 419641090.779428 # Number of busy cycles -system.cpu1.not_idle_fraction 0.175700 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.824300 # Percentage of idle cycles +system.cpu1.num_mem_refs 10012651 # number of memory refs +system.cpu1.num_load_insts 5981805 # Number of load instructions +system.cpu1.num_store_insts 4030846 # Number of store instructions +system.cpu1.num_idle_cycles 1968708722.646828 # Number of idle cycles +system.cpu1.num_busy_cycles 419624094.353172 # Number of busy cycles +system.cpu1.not_idle_fraction 0.175697 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.824303 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 39064 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 376544 # number of replacements -system.cpu1.icache.tags.tagsinuse 474.938465 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19004396 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 377056 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 50.402052 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 327017678500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.938465 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927614 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.927614 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19004396 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19004396 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19004396 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19004396 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19004396 # number of overall hits -system.cpu1.icache.overall_hits::total 19004396 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 377056 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 377056 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 377056 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 377056 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 377056 # number of overall misses -system.cpu1.icache.overall_misses::total 377056 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154731460 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5154731460 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5154731460 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5154731460 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5154731460 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5154731460 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19381452 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19381452 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19381452 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19381452 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19381452 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19381452 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019454 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.019454 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019454 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.019454 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019454 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.019454 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13670.997040 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13670.997040 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13670.997040 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13670.997040 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13670.997040 # average overall miss latency +system.cpu1.kern.inst.quiesce 39053 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 376539 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.945138 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19000914 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 377051 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 50.393485 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 327002273500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.945138 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927627 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927627 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 19000914 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19000914 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19000914 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19000914 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19000914 # number of overall hits +system.cpu1.icache.overall_hits::total 19000914 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 377051 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 377051 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 377051 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 377051 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 377051 # number of overall misses +system.cpu1.icache.overall_misses::total 377051 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5154764964 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5154764964 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5154764964 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5154764964 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5154764964 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5154764964 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 19377965 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 19377965 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 19377965 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 19377965 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 19377965 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 19377965 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.019458 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.019458 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.019458 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.019458 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.019458 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.019458 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13671.267187 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13671.267187 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13671.267187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13671.267187 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13671.267187 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1611,120 +1532,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377056 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 377056 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 377056 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 377056 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 377056 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 377056 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398633040 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398633040 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398633040 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4398633040 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398633040 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4398633040 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 377051 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 377051 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 377051 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 377051 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 377051 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 377051 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4398685536 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4398685536 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4398685536 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4398685536 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4398685536 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4398685536 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6184500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6184500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6184500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 6184500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019454 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.019454 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019454 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.019454 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11665.728804 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11665.728804 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11665.728804 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019458 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019458 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019458 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019458 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11666.022729 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11666.022729 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11666.022729 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 220840 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.619758 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8232994 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 221207 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.218506 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 106228428000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.619758 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921132 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.921132 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 4390579 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4390579 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3674302 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3674302 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73464 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 73464 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73742 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 73742 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8064881 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8064881 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8064881 # number of overall hits -system.cpu1.dcache.overall_hits::total 8064881 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 133951 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 133951 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 112879 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 112879 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9745 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 9745 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9392 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9392 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 246830 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 246830 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 246830 # number of overall misses -system.cpu1.dcache.overall_misses::total 246830 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1653824236 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1653824236 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3737179210 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3737179210 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 78087000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 78087000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49049473 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 49049473 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5391003446 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5391003446 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5391003446 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5391003446 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4524530 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4524530 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3787181 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3787181 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83209 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 83209 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83134 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83134 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 8311711 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 8311711 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 8311711 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 8311711 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029606 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.029606 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029806 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.029806 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117115 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117115 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112974 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112974 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029697 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029697 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029697 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.029697 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12346.486670 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12346.486670 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33107.834141 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 33107.834141 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8013.032324 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8013.032324 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5222.473701 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5222.473701 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 21840.957120 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21840.957120 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21840.957120 # average overall miss latency +system.cpu1.dcache.tags.replacements 220336 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.526784 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8228665 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 220703 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.283884 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 106211109000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.526784 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.920951 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.920951 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 4388185 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4388185 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3672248 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3672248 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 73451 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 73451 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73727 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 73727 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8060433 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8060433 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8060433 # number of overall hits +system.cpu1.dcache.overall_hits::total 8060433 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 133748 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 133748 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 112730 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 112730 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9735 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 9735 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9394 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 9394 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 246478 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 246478 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 246478 # number of overall misses +system.cpu1.dcache.overall_misses::total 246478 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1649486235 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1649486235 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3739097468 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3739097468 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 77937249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 77937249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 49168975 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 49168975 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5388583703 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5388583703 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5388583703 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5388583703 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4521933 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4521933 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3784978 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3784978 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 83186 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 83186 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 83121 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83121 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8306911 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8306911 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8306911 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8306911 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029578 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029578 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029784 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029784 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117027 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117027 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113016 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113016 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029671 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029671 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.029671 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.029671 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12332.791780 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12332.791780 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33168.610556 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33168.610556 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8005.880740 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8005.880740 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5234.082925 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5234.082925 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21862.331336 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21862.331336 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21862.331336 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1733,66 +1654,66 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 200060 # number of writebacks -system.cpu1.dcache.writebacks::total 200060 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133951 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 133951 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112879 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 112879 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9745 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9745 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9391 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 246830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 246830 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 246830 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 246830 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1384995764 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1384995764 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3490409790 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3490409790 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30268527 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30268527 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 199438 # number of writebacks +system.cpu1.dcache.writebacks::total 199438 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 133748 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 133748 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 112730 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 112730 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9735 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9735 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9393 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9393 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 246478 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 246478 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 246478 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 246478 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1381071765 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1381071765 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3492633532 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3492633532 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 58449751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 58449751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 30384025 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 30384025 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4875405554 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4875405554 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4875405554 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4875405554 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372273000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372273000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531015000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531015000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903288000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903288000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029606 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029606 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029806 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029806 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117115 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117115 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112962 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112962 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029697 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029697 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.029697 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10339.570171 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10339.570171 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30921.693052 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30921.693052 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6011.287840 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6011.287840 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3223.142051 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3223.142051 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4873705297 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4873705297 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4873705297 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4873705297 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168372112000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168372112000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531034000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 531034000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 168903146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 168903146000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029578 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029784 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029784 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.117027 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.117027 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.113004 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.113004 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.029671 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.029671 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.029671 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10325.924612 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10325.924612 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30982.289825 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30982.289825 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6004.083308 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6004.083308 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3234.751943 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3234.751943 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19752.078572 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19752.078572 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19773.388688 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19773.388688 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1800,12 +1721,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1814,10 +1735,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 624927975253 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 624927975253 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 624927975253 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 624927975253 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 618710198251 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 618710198251 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 618710198251 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 618710198251 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 955e513bb..efd49eb78 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,105 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.615733 # Number of seconds simulated -sim_ticks 2615733285000 # Number of ticks simulated -final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.615716 # Number of seconds simulated +sim_ticks 2615716222000 # Number of ticks simulated +final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250012 # Simulator instruction rate (inst/s) -host_op_rate 318151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10863402189 # Simulator tick rate (ticks/s) -host_mem_usage 396412 # Number of bytes of host memory used -host_seconds 240.78 # Real time elapsed on the host -sim_insts 60198861 # Number of instructions simulated -sim_ops 76605713 # Number of ops (including micro ops) simulated +host_inst_rate 250038 # Simulator instruction rate (inst/s) +host_op_rate 318184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10864403710 # Simulator tick rate (ticks/s) +host_mem_usage 394540 # Number of bytes of host memory used +host_seconds 240.76 # Real time elapsed on the host +sim_insts 60199078 # Number of instructions simulated +sim_ops 76605946 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory -system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494770 # Total number of read requests seen -system.physmem.writeReqs 811989 # Total number of write requests seen -system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991665280 # Total number of bytes read from memory +system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 991665344 # Total number of bytes read from memory system.physmem.bytesWritten 51967296 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2615728912000 # Total gap between requests +system.physmem.totGap 2615711849000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152694 # Categorize read packet sizes +system.physmem.readPktSize::6 152695 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes @@ -107,23 +108,23 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 57971 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1007328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3775576 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2827750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2822812 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2787859 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 21456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 18919 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 32464 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 45819 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 32079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 4562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 4458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -139,346 +140,300 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 3 0.01% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 9 0.02% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 2 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 9 0.02% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8639 1 0.00% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 5 0.01% 59.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9919 1 0.00% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10175 2 0.01% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 20 0.05% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10687 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11071 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 2 0.01% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12607 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12735 1 0.00% 59.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13696-13759 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13887 1 0.00% 59.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 2 0.01% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14399 3 0.01% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15423 4 0.01% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18751 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 2 0.01% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20159 1 0.00% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20351 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 1 0.00% 60.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22335 2 0.01% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22463 1 0.00% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22591 3 0.01% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23103 2 0.01% 60.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23424-23487 1 0.00% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 2 0.01% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 2 0.01% 60.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 2 0.01% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25151 2 0.01% 60.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25216-25279 1 0.00% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25407 2 0.01% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25727 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25792-25855 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26175 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26240-26303 1 0.00% 60.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26431 2 0.01% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 1 0.00% 60.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27711 3 0.01% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 2 0.01% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29247 1 0.00% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29312-29375 1 0.00% 60.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29632-29695 1 0.00% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29759 2 0.01% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30272-30335 1 0.00% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30783 4 0.01% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30848-30911 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31487 1 0.00% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31807 3 0.01% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33088-33151 1 0.00% 60.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33152-33215 24 0.06% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33343 16 0.04% 60.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35135 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39231 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39487 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40767 1 0.00% 60.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-41023 1 0.00% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 2 0.01% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42559 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42815 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 1 0.00% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44992-45055 1 0.00% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47167 2 0.01% 60.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47679 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49983 1 0.00% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50495 1 0.00% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51519 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52736-52799 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55359 1 0.00% 60.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56383 2 0.01% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62527 1 0.00% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64000-64063 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64768-64831 1 0.00% 60.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 14794 38.44% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::76928-76991 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::81536-81599 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::95680-95743 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::96064-96127 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::98880-98943 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::103488-103551 1 0.00% 99.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::106240-106303 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::106624-106687 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::109440-109503 1 0.00% 99.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::111232-111295 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::114048-114111 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::117184-117247 1 0.00% 99.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::118272-118335 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::120000-120063 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::121792-121855 1 0.00% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::124608-124671 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::125696-125759 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128832-128895 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130560-130623 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::156992-157055 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::193280-193343 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196096-196159 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 16 0.04% 57.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 6 0.02% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 5 0.01% 57.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 5 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 6 0.02% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 6 0.02% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 9 0.02% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 42 0.11% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 2 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 4 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 8 0.02% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 4 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 5 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 6 0.02% 58.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 2 0.01% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 1 0.00% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 6 0.02% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 1 0.00% 58.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 10 0.03% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 2 0.01% 58.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 5 0.01% 58.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 2 0.01% 58.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 3 0.01% 58.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 3 0.01% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5823 3 0.01% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 1 0.00% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-6015 2 0.01% 58.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 2 0.01% 58.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 2 0.01% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 1 0.00% 58.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 4 0.01% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 1 0.00% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 1 0.00% 58.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 6 0.02% 58.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 16 0.04% 58.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 4 0.01% 58.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 4 0.01% 58.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 4 0.01% 58.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 2 0.01% 58.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 2 0.01% 58.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 5 0.01% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 2 0.01% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 7 0.02% 58.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 6 0.02% 58.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 8 0.02% 58.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 8 0.02% 58.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 328 0.86% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8511 24 0.06% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8575 141 0.37% 59.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8639 169 0.44% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8831 1 0.00% 60.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8832-8895 2 0.01% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-9023 3 0.01% 60.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9535 1 0.00% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12095 2 0.01% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13887 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-14015 1 0.00% 60.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14399 4 0.01% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14976-15039 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16703 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17471 3 0.01% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18239 2 0.01% 60.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18495 5 0.01% 60.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18624-18687 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19328-19391 1 0.00% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20352-20415 1 0.00% 60.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 2 0.01% 60.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22144-22207 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22335 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23103 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23168-23231 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 4 0.01% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24255 1 0.00% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24383 3 0.01% 60.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25151 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25407 1 0.00% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25728-25791 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation -system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests -system.physmem.totBusLat 77472355000 # Total cycles spent in databus access -system.physmem.totBankLat 16272657500 # Total cycles spent in bank access -system.physmem.avgQLat 19568.21 # Average queueing delay per request -system.physmem.avgBankLat 1050.22 # Average bank access latency per request +system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation +system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests +system.physmem.totBusLat 77465575000 # Total cycles spent in databus access +system.physmem.totBankLat 16358058750 # Total cycles spent in bank access +system.physmem.avgQLat 19154.87 # Average queueing delay per request +system.physmem.avgBankLat 1055.83 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25618.44 # Average memory access latency +system.physmem.avgMemAccLat 25210.70 # Average memory access latency system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s @@ -486,12 +441,12 @@ system.physmem.avgConsumedWrBW 2.57 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.12 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time -system.physmem.avgWrQLen 10.84 # Average write queue length over time -system.physmem.readRowHits 15469547 # Number of row buffer hits during reads -system.physmem.writeRowHits 798405 # Number of row buffer hits during writes +system.physmem.avgWrQLen 13.76 # Average write queue length over time +system.physmem.readRowHits 15468398 # Number of row buffer hits during reads +system.physmem.writeRowHits 93875 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes -system.physmem.avgGap 160407.65 # Average gap between requests +system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes +system.physmem.avgGap 160406.60 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -504,9 +459,9 @@ system.realview.nvmem.bw_inst_read::cpu.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54136540 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546595 # Transaction distribution -system.membus.trans_dist::ReadResp 16546595 # Transaction distribution +system.membus.throughput 54136917 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16546596 # Transaction distribution +system.membus.trans_dist::ReadResp 16546596 # Transaction distribution system.membus.trans_dist::WriteReq 763368 # Transaction distribution system.membus.trans_dist::WriteResp 763368 # Transaction distribution system.membus.trans_dist::Writeback 57971 # Transaction distribution @@ -516,47 +471,37 @@ system.membus.trans_dist::ReadExReq 132250 # Tr system.membus.trans_dist::ReadExResp 132250 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141606749 # Total data (bytes) +system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141606813 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -564,7 +509,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47815955 # Throughput (bytes/s) +system.iobus.throughput 47816267 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution system.iobus.trans_dist::WriteReq 8166 # Transaction distribution @@ -595,30 +540,6 @@ system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 1 system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) @@ -646,30 +567,6 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 125073785 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) @@ -722,30 +619,30 @@ system.iobus.reqLayer25.occupancy 15335424000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42022039000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14996132 # DTB read hits -system.cpu.dtb.read_misses 7340 # DTB read misses -system.cpu.dtb.write_hits 11230462 # DTB write hits -system.cpu.dtb.write_misses 2218 # DTB write misses +system.cpu.dtb.read_hits 14996146 # DTB read hits +system.cpu.dtb.read_misses 7341 # DTB read misses +system.cpu.dtb.write_hits 11230467 # DTB write hits +system.cpu.dtb.write_misses 2217 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 197 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15003472 # DTB read accesses -system.cpu.dtb.write_accesses 11232680 # DTB write accesses +system.cpu.dtb.read_accesses 15003487 # DTB read accesses +system.cpu.dtb.write_accesses 11232684 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226594 # DTB hits +system.cpu.dtb.hits 26226613 # DTB hits system.cpu.dtb.misses 9558 # DTB misses -system.cpu.dtb.accesses 26236152 # DTB accesses -system.cpu.itb.inst_hits 61492700 # ITB inst hits +system.cpu.dtb.accesses 26236171 # DTB accesses +system.cpu.itb.inst_hits 61492923 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -762,79 +659,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61497171 # ITB inst accesses -system.cpu.itb.hits 61492700 # DTB hits +system.cpu.itb.inst_accesses 61497394 # ITB inst accesses +system.cpu.itb.hits 61492923 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61497171 # DTB accesses -system.cpu.numCycles 5231466570 # number of cpu cycles simulated +system.cpu.itb.accesses 61497394 # DTB accesses +system.cpu.numCycles 5231432444 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60198861 # Number of instructions committed -system.cpu.committedOps 76605713 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68872503 # Number of integer alu accesses +system.cpu.committedInsts 60199078 # Number of instructions committed +system.cpu.committedOps 76605946 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68872726 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2140458 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7948408 # number of instructions that are conditional controls -system.cpu.num_int_insts 68872503 # number of integer instructions +system.cpu.num_func_calls 2140465 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7948429 # number of instructions that are conditional controls +system.cpu.num_int_insts 68872726 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394778081 # number of times the integer registers were read -system.cpu.num_int_register_writes 74182147 # number of times the integer registers were written +system.cpu.num_int_register_reads 394779183 # number of times the integer registers were read +system.cpu.num_int_register_writes 74182470 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27394052 # number of memory refs -system.cpu.num_load_insts 15660178 # Number of load instructions -system.cpu.num_store_insts 11733874 # Number of store instructions -system.cpu.num_idle_cycles 4581968820.612248 # Number of idle cycles -system.cpu.num_busy_cycles 649497749.387752 # Number of busy cycles -system.cpu.not_idle_fraction 0.124152 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.875848 # Percentage of idle cycles +system.cpu.num_mem_refs 27394080 # number of memory refs +system.cpu.num_load_insts 15660200 # Number of load instructions +system.cpu.num_store_insts 11733880 # Number of store instructions +system.cpu.num_idle_cycles 4581975478.612248 # Number of idle cycles +system.cpu.num_busy_cycles 649456965.387752 # Number of busy cycles +system.cpu.not_idle_fraction 0.124145 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.875855 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 856294 # number of replacements -system.cpu.icache.tags.tagsinuse 510.881133 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60635894 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856806 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.769689 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19815360250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.881133 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997815 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635894 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635894 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635894 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635894 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635894 # number of overall hits -system.cpu.icache.overall_hits::total 60635894 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856806 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856806 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856806 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856806 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856806 # number of overall misses -system.cpu.icache.overall_misses::total 856806 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768628750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11768628750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11768628750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11768628750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11768628750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11768628750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61492700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61492700 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61492700 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61492700 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61492700 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61492700 # number of overall (read+write) accesses +system.cpu.icache.tags.replacements 856273 # number of replacements +system.cpu.icache.tags.tagsinuse 510.884220 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60636138 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856785 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.771708 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19799760250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.884220 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997821 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 60636138 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60636138 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60636138 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60636138 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60636138 # number of overall hits +system.cpu.icache.overall_hits::total 60636138 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856785 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856785 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856785 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856785 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856785 # number of overall misses +system.cpu.icache.overall_misses::total 856785 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11770019500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11770019500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11770019500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11770019500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11770019500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11770019500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61492923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61492923 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61492923 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61492923 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61492923 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61492923 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.464913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13735.464913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13735.464913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13735.464913 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13737.424792 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13737.424792 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13737.424792 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13737.424792 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -843,174 +740,174 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856806 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856806 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856806 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856806 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856806 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856806 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049829250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10049829250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049829250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10049829250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049829250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10049829250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 430705250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 430705250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 430705250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 430705250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856785 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 856785 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 856785 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 856785 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 856785 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 856785 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051263500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10051263500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051263500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10051263500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051263500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10051263500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 414413750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 414413750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11729.410450 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11729.410450 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.371931 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.371931 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 62586 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50732.763816 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1683068 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 127970 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.152051 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2564920911000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37695.858347 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884553 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 62587 # number of replacements +system.cpu.l2cache.tags.tagsinuse 50733.810806 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1683077 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 127973 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 13.151813 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2564904211000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37696.862224 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884576 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6997.437473 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6035.582751 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.575193 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6998.396772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6034.666541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.575208 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106772 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.092096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.774121 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106787 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092082 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.774137 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 844565 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 370151 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1226971 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 595786 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 595786 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 844543 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 370162 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1226960 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 595785 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 595785 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113434 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113434 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113425 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113425 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 8720 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3535 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 844565 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 483585 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1340405 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 844543 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 483587 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1340385 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 8720 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3535 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 844565 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 483585 # number of overall hits -system.cpu.l2cache.overall_hits::total 1340405 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 844543 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 483587 # number of overall hits +system.cpu.l2cache.overall_hits::total 1340385 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 10600 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 10601 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 9837 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 20444 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 20445 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 133893 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 133893 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 10600 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 10601 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 143730 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 154337 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154338 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 10600 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 10601 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 143730 # number of overall misses -system.cpu.l2cache.overall_misses::total 154337 # number of overall misses +system.cpu.l2cache.overall_misses::total 154338 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 390500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 745731750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 700197500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1446442250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8609650357 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8609650357 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747407000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 696870750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1444790750 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 470980 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 470980 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8609068107 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8609068107 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 390500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 745731750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9309847857 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10056092607 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 747407000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9305938857 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10053858857 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 390500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 745731750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9309847857 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10056092607 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 747407000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9305938857 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10053858857 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8725 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3537 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 855165 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 379988 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1247415 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 595786 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 595786 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 855144 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 379999 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1247405 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 595785 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 595785 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247327 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247327 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247318 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247318 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8725 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3537 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 855165 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 627315 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1494742 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 855144 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 627317 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1494723 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8725 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3537 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 855165 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 627315 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1494742 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 855144 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 627317 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1494723 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012395 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.016389 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012397 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025887 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.016390 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541360 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541360 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541380 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541380 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012395 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012397 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.229119 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103253 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103255 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012395 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012397 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.229119 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103253 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103255 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78100 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70352.051887 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71179.983735 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70751.430738 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.642061 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.642061 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64302.468068 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64302.468068 # average ReadExReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70503.443071 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70841.796279 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 70667.192468 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.990251 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.990251 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64298.119446 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64298.119446 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70352.051887 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64773.170925 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65156.719432 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 65141.824159 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.051887 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64773.170925 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65156.719432 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 65141.824159 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1023,88 +920,88 @@ system.cpu.l2cache.writebacks::writebacks 57971 # n system.cpu.l2cache.writebacks::total 57971 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10600 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10601 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9837 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 20444 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 20445 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133893 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 133893 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10600 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10601 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 143730 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 154337 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154338 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10600 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10601 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 143730 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 154337 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154338 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 326500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 612276250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 575969500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1188669750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28722872 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28722872 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6933953143 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6933953143 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 613945500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 572634250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1187003750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28725872 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28725872 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6933351393 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6933351393 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 326500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 612276250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7509922643 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8122622893 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 613945500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7505985643 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8120355143 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 326500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 612276250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7509922643 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8122622893 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 339357750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657272750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996630500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702868810 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702868810 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339357750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183360141560 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183699499310 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 613945500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7505985643 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8120355143 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 322980250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657157250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166980137500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702542535 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702542535 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 322980250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359699785 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183682680035 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025888 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016389 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025887 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016390 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541360 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541360 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541380 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541380 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103253 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.103255 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.103253 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.103255 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57761.910377 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58551.336790 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58142.719135 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51787.271500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51787.271500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57913.923215 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58212.285250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58058.388359 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.044568 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.044568 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51782.777240 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51782.777240 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1114,79 +1011,79 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 626803 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.877792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 23655579 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 627315 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.709251 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 657281250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.877792 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999761 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13195771 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13195771 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972807 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972807 # number of WriteReq hits +system.cpu.dcache.tags.replacements 626805 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.881003 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 23655596 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 627317 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.709158 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 640871250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.881003 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999768 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13195774 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195774 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972821 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972821 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23168578 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23168578 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23168578 # number of overall hits -system.cpu.dcache.overall_hits::total 23168578 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368488 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368488 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250225 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250225 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 23168595 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168595 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168595 # number of overall hits +system.cpu.dcache.overall_hits::total 23168595 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368499 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368499 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250216 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250216 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618713 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618713 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618713 # number of overall misses -system.cpu.dcache.overall_misses::total 618713 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5386574000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5386574000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10624198015 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10624198015 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 159892750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 159892750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16010772015 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16010772015 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16010772015 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16010772015 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13564259 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13564259 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10223032 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10223032 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 618715 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 618715 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 618715 # number of overall misses +system.cpu.dcache.overall_misses::total 618715 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5384538000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5384538000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10623511265 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10623511265 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158750500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 158750500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16008049265 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16008049265 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16008049265 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16008049265 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564273 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223037 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223037 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23787291 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23787291 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23787291 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23787291 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027166 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.027166 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024477 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024477 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 23787310 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787310 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787310 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787310 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027167 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.027167 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024476 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024476 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25877.542601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25877.542601 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14612.083072 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14612.083072 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42457.361899 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42457.361899 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13804.391304 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25873.058298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1195,54 +1092,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 595786 # number of writebacks -system.cpu.dcache.writebacks::total 595786 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250225 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250225 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 595785 # number of writebacks +system.cpu.dcache.writebacks::total 595785 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250216 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250216 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618713 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618713 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618713 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618713 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4644879500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4644879500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10059088985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10059088985 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136816250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136816250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14703968485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14703968485 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14703968485 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 14703968485 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050953750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050953750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234980190 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234980190 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208285933940 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10058410735 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135673500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135673500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14701227235 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14701227235 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1250,44 +1147,44 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution +system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1296,10 +1193,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index b5f8111f8..31f47079e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.332810 # Nu sim_ticks 2332810264000 # Number of ticks simulated final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 662335 # Simulator instruction rate (inst/s) -host_op_rate 851722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25577480180 # Simulator tick rate (ticks/s) -host_mem_usage 396424 # Number of bytes of host memory used -host_seconds 91.21 # Real time elapsed on the host +host_inst_rate 691261 # Simulator instruction rate (inst/s) +host_op_rate 888919 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26694508777 # Simulator tick rate (ticks/s) +host_mem_usage 395580 # Number of bytes of host memory used +host_seconds 87.39 # Real time elapsed on the host sim_insts 60408639 # Number of instructions simulated sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory @@ -62,14 +62,15 @@ system.physmem.bw_total::cpu0.data 3386724 # To system.physmem.bw_total::cpu1.inst 91056 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1794913 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 54942145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -223,27 +224,27 @@ system.realview.nvmem.bw_total::total 9 # To system.membus.throughput 55969561 # Throughput (bytes/s) system.membus.data_through_bus 130566366 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.l2c.tags.replacements 62242 # number of replacements -system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use -system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy +system.l2c.tags.replacements 62242 # number of replacements +system.l2c.tags.tagsinuse 50006.300222 # Cycle average of tags in use +system.l2c.tags.total_refs 1678485 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127627 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.151488 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36900.571453 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993823 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4917.298419 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3152.525311 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2097.421525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2936.495759 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.075032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044807 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.763036 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 9005 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3277 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 473134 # number of ReadReq hits @@ -450,23 +451,23 @@ system.cpu0.num_fp_register_writes 1428 # nu system.cpu0.num_mem_refs 15013057 # number of memory refs system.cpu0.num_load_insts 8304661 # Number of load instructions system.cpu0.num_store_insts 6708396 # Number of store instructions -system.cpu0.num_idle_cycles 186586201.060505 # Number of idle cycles -system.cpu0.num_busy_cycles 4447003463.939495 # Number of busy cycles -system.cpu0.not_idle_fraction 0.959732 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.040268 # Percentage of idle cycles +system.cpu0.num_idle_cycles 4555625120.147407 # Number of idle cycles +system.cpu0.num_busy_cycles 77964544.852593 # Number of busy cycles +system.cpu0.not_idle_fraction 0.016826 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.983174 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 850590 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.replacements 850590 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60583498 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 444.510252 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_blocks::cpu1.inst 67.168341 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.868184 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.131188 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 32064735 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 28518763 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60583498 # number of ReadReq hits @@ -512,17 +513,17 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623334 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.replacements 623334 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23628284 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623846 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.875187 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. system.cpu0.dcache.tags.occ_blocks::cpu0.data 451.298938 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_blocks::cpu1.data 60.698093 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.881443 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.118551 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 6995590 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6184430 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13180020 # number of ReadReq hits @@ -660,18 +661,18 @@ system.cpu1.num_fp_register_writes 1352 # nu system.cpu1.num_mem_refs 12348580 # number of memory refs system.cpu1.num_load_insts 7334866 # Number of load instructions system.cpu1.num_store_insts 5013714 # Number of store instructions -system.cpu1.num_idle_cycles 8315278901.051629 # Number of idle cycles -system.cpu1.num_busy_cycles -4035324022.051629 # Number of busy cycles -system.cpu1.not_idle_fraction -0.942843 # Percentage of non-idle cycles -system.cpu1.idle_fraction 1.942843 # Percentage of idle cycles +system.cpu1.num_idle_cycles 4217653381.679553 # Number of idle cycles +system.cpu1.num_busy_cycles 62301497.320448 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014557 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985443 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 56bd99bdd..4e0947e27 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112102 # Nu sim_ticks 5112102211000 # Number of ticks simulated final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 878832 # Simulator instruction rate (inst/s) -host_op_rate 1799374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 22473674513 # Simulator tick rate (ticks/s) -host_mem_usage 586256 # Number of bytes of host memory used -host_seconds 227.47 # Real time elapsed on the host +host_inst_rate 856407 # Simulator instruction rate (inst/s) +host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21900233108 # Simulator tick rate (ticks/s) +host_mem_usage 584104 # Number of bytes of host memory used +host_seconds 233.43 # Real time elapsed on the host sim_insts 199908396 # Number of instructions simulated sim_ops 409304707 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory @@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 63 # To system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 0 # Total number of read requests seen -system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 0 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis @@ -195,15 +196,15 @@ system.physmem.avgGap nan # Av system.membus.throughput 9632725 # Throughput (bytes/s) system.membus.data_through_bus 49243475 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 47569 # number of replacements +system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses system.iocache.ReadReq_misses::total 904 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -277,15 +278,15 @@ system.cpu.not_idle_fraction 0.044374 # Pe system.cpu.idle_fraction 0.955626 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 790522 # number of replacements -system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 790522 # number of replacements +system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits @@ -320,10 +321,10 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit. system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy @@ -368,10 +369,10 @@ system.cpu.itb_walker_cache.writebacks::writebacks 526 system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit. system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy @@ -411,15 +412,15 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622027 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1622027 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits @@ -466,23 +467,23 @@ system.cpu.dcache.no_allocate_misses 0 # Nu system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s) system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) -system.cpu.l2cache.tags.replacements 105931 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.replacements 105931 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index bb1dca70a..c9dd91320 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.196173 # Nu sim_ticks 5196173457000 # Number of ticks simulated final_tick 5196173457000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766970 # Simulator instruction rate (inst/s) -host_op_rate 1478526 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31067837744 # Simulator tick rate (ticks/s) -host_mem_usage 586132 # Number of bytes of host memory used -host_seconds 167.25 # Real time elapsed on the host +host_inst_rate 457062 # Simulator instruction rate (inst/s) +host_op_rate 881101 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18514311716 # Simulator tick rate (ticks/s) +host_mem_usage 585140 # Number of bytes of host memory used +host_seconds 280.66 # Real time elapsed on the host sim_insts 128277551 # Number of instructions simulated sim_ops 247287193 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2879808 # Number of bytes read from this memory @@ -46,14 +46,15 @@ system.physmem.bw_total::cpu.itb.walker 62 # To system.physmem.bw_total::cpu.inst 159034 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1730209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4005815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198391 # Total number of read requests seen -system.physmem.writeReqs 126842 # Total number of write requests seen -system.physmem.cpureqs 326873 # Reqs generatd by CPU via cache - shady +system.physmem.readReqs 198391 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 126842 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 198391 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 126842 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts system.physmem.bytesRead 12697024 # Total number of bytes read from memory system.physmem.bytesWritten 8117888 # Total number of bytes written to memory system.physmem.bytesConsumedRd 12697024 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 8117888 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q +system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by write Q system.physmem.neitherReadNorWrite 1638 # Reqs where no action is needed system.physmem.perBankRdReqs::0 12755 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 12192 # Track reads on a per bank basis @@ -358,39 +359,31 @@ system.membus.trans_dist::MessageReq 1655 # Tr system.membus.trans_dist::MessageResp 1655 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391390 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139223 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 139223 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 530613 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 480072 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1724109 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14948416 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16614957 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5866496 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 5866496 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 20814912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 246316 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::total 22488073 # Cumulative packet size per connected master and slave (bytes) system.membus.data_through_bus 22488073 # Total data (bytes) system.membus.snoop_data_through_bus 205568 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1351024000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 256571500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 256571500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 359320500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 359320500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3310000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1351024000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) @@ -532,26 +525,6 @@ system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.com_1.pio 26980 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 578500 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) @@ -576,26 +549,6 @@ system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_sid system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.com_1.pio 13490 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::total 3280192 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 3280192 # Total data (bytes) system.iobus.reqLayer0.occupancy 3949164 # Layer occupancy (ticks) @@ -1032,16 +985,16 @@ system.cpu.toL2Bus.trans_dist::UpgradeReq 2190 # T system.cpu.toL2Bus.trans_dist::UpgradeResp 2190 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 359066 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 312361 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1584265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5972620 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side 8122 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side 18187 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7583194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 50696064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 203753837 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side 242368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side 606720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 255298989 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584265 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5972620 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8122 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18187 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7583194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50696064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203753837 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 242368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 606720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 255298989 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.data_through_bus 255278509 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 309568 # Total snoop data (bytes) system.cpu.toL2Bus.reqLayer0.occupancy 3830199000 # Layer occupancy (ticks) |