diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/quick/fs | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/quick/fs')
12 files changed, 9638 insertions, 7528 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 87d1939f2..973b187d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -1,188 +1,221 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.870335 # Number of seconds simulated -sim_ticks 1870335131500 # Number of ticks simulated -final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.869358 # Number of seconds simulated +sim_ticks 1869357988000 # Number of ticks simulated +final_tick 1869357988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1824221 # Simulator instruction rate (inst/s) -host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 54024573563 # Simulator tick rate (ticks/s) -host_mem_usage 318368 # Number of bytes of host memory used -host_seconds 34.62 # Real time elapsed on the host -sim_insts 63154606 # Number of instructions simulated -sim_ops 63154606 # Number of ops (including micro ops) simulated +host_inst_rate 2868261 # Simulator instruction rate (inst/s) +host_op_rate 2868259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 82489350498 # Simulator tick rate (ticks/s) +host_mem_usage 370556 # Number of bytes of host memory used +host_seconds 22.66 # Real time elapsed on the host +sim_insts 64999904 # Number of instructions simulated +sim_ops 64999904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 765760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 66552064 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory -system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 106560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 771648 # Number of bytes read from this memory +system.physmem.bytes_read::total 68196992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 765760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 106560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 872320 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5174080 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7833408 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 11965 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 1039876 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12057 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1065578 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80845 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 40739369 # Throughput (bytes/s) -system.membus.data_through_bus 76196274 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.num_writes::total 122397 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 409638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 35601562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 57004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 412788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 36481505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 409638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 57004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2767838 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1422589 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4190427 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2767838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 409638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 35601562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1423102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 57004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 412788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40671931 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 948901 # Transaction distribution +system.membus.trans_dist::ReadResp 948901 # Transaction distribution +system.membus.trans_dist::WriteReq 14588 # Transaction distribution +system.membus.trans_dist::WriteResp 14588 # Transaction distribution +system.membus.trans_dist::Writeback 80845 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 19618 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 14179 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8160 # Transaction distribution +system.membus.trans_dist::ReadExReq 126515 # Transaction distribution +system.membus.trans_dist::ReadExResp 124290 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 44074 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2256153 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 2300227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2383689 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 86162 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 73370112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 73456274 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2670784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 76127058 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1224161 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1224161 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1224161 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 1000624 # number of replacements -system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use -system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks. +system.l2c.tags.replacements 999765 # number of replacements +system.l2c.tags.tagsinuse 65320.982867 # Cycle average of tags in use +system.l2c.tags.total_refs 2387620 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1064815 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.242286 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997649 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 32109770 # Number of tag accesses -system.l2c.tags.data_accesses 32109770 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits -system.l2c.Writeback_hits::total 816663 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955345 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 873092 # number of overall hits -system.l2c.overall_hits::cpu0.data 929323 # number of overall hits -system.l2c.overall_hits::cpu1.inst 101902 # number of overall hits -system.l2c.overall_hits::cpu1.data 51028 # number of overall hits -system.l2c.overall_hits::total 1955345 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses -system.l2c.ReadReq_misses::total 941295 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 100 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 165 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses -system.l2c.demand_misses::total 1066663 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 11892 # number of overall misses -system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses -system.l2c.overall_misses::cpu1.data 10570 # number of overall misses -system.l2c.overall_misses::total 1066663 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses +system.l2c.tags.occ_blocks::writebacks 56016.884833 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4834.504330 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4176.028554 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 178.991920 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 114.573230 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.854750 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.073769 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.063721 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.002731 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001748 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996719 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65050 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 768 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 3271 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5934 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48949 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.992584 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 31465722 # Number of tag accesses +system.l2c.tags.data_accesses 31465722 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 606953 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 626726 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 379523 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 129013 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1742215 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 777631 # number of Writeback hits +system.l2c.Writeback_hits::total 777631 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 116 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 577 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 693 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 37 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 13 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 50 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 111430 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56603 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 168033 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 606953 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 738156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 379523 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 185616 # number of demand (read+write) hits +system.l2c.demand_hits::total 1910248 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 606953 # number of overall hits +system.l2c.overall_hits::cpu0.data 738156 # number of overall hits +system.l2c.overall_hits::cpu1.inst 379523 # number of overall hits +system.l2c.overall_hits::cpu1.data 185616 # number of overall hits +system.l2c.overall_hits::total 1910248 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 11965 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 926610 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1665 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1033 # number of ReadReq misses +system.l2c.ReadReq_misses::total 941273 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 3006 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2175 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 5181 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1175 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1110 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2285 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 113916 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 11068 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124984 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 11965 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1040526 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1665 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12101 # number of demand (read+write) misses +system.l2c.demand_misses::total 1066257 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 11965 # number of overall misses +system.l2c.overall_misses::cpu0.data 1040526 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1665 # number of overall misses +system.l2c.overall_misses::cpu1.data 12101 # number of overall misses +system.l2c.overall_misses::total 1066257 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.inst 618918 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1553336 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 381188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 130046 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2683488 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 777631 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 777631 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3122 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2752 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5874 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1212 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1123 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2335 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 225346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 67671 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 293017 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 618918 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1778682 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 381188 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 197717 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2976505 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 618918 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1778682 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 381188 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 197717 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2976505 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.019332 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.596529 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.007943 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.350765 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.962844 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790334 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.882022 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.969472 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.988424 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.978587 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.505516 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.163556 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.426542 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.019332 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.584998 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004368 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.061204 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.358224 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.019332 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.584998 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004368 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.061204 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.358224 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -191,39 +224,39 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81314 # number of writebacks -system.l2c.writebacks::total 81314 # number of writebacks +system.l2c.writebacks::writebacks 80845 # number of writebacks +system.l2c.writebacks::total 80845 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 41695 # number of replacements -system.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use +system.iocache.tags.replacements 41699 # number of replacements +system.iocache.tags.tagsinuse 0.434096 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1685787163517 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.434096 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.027131 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.027131 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375543 # Number of tag accesses -system.iocache.tags.data_accesses 375543 # Number of data accesses +system.iocache.tags.tag_accesses 375579 # Number of tag accesses +system.iocache.tags.data_accesses 375579 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses -system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses -system.iocache.demand_misses::total 175 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 175 # number of overall misses -system.iocache.overall_misses::total 175 # number of overall misses -system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses +system.iocache.ReadReq_misses::total 179 # number of ReadReq misses +system.iocache.demand_misses::tsunami.ide 179 # number of demand (read+write) misses +system.iocache.demand_misses::total 179 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 179 # number of overall misses +system.iocache.overall_misses::total 179 # number of overall misses +system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 179 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 179 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 179 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 179 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses @@ -255,22 +288,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9154569 # DTB read hits -system.cpu0.dtb.read_misses 7079 # DTB read misses +system.cpu0.dtb.read_hits 7758808 # DTB read hits +system.cpu0.dtb.read_misses 7155 # DTB read misses system.cpu0.dtb.read_acv 152 # DTB read access violations -system.cpu0.dtb.read_accesses 508987 # DTB read accesses -system.cpu0.dtb.write_hits 5936918 # DTB write hits -system.cpu0.dtb.write_misses 726 # DTB write misses -system.cpu0.dtb.write_acv 99 # DTB write access violations -system.cpu0.dtb.write_accesses 189050 # DTB write accesses -system.cpu0.dtb.data_hits 15091487 # DTB hits -system.cpu0.dtb.data_misses 7805 # DTB misses -system.cpu0.dtb.data_acv 251 # DTB access violations -system.cpu0.dtb.data_accesses 698037 # DTB accesses -system.cpu0.itb.fetch_hits 3855534 # ITB hits -system.cpu0.itb.fetch_misses 3485 # ITB misses +system.cpu0.dtb.read_accesses 531148 # DTB read accesses +system.cpu0.dtb.write_hits 4740251 # DTB write hits +system.cpu0.dtb.write_misses 732 # DTB write misses +system.cpu0.dtb.write_acv 102 # DTB write access violations +system.cpu0.dtb.write_accesses 201714 # DTB write accesses +system.cpu0.dtb.data_hits 12499059 # DTB hits +system.cpu0.dtb.data_misses 7887 # DTB misses +system.cpu0.dtb.data_acv 254 # DTB access violations +system.cpu0.dtb.data_accesses 732862 # DTB accesses +system.cpu0.itb.fetch_hits 3525726 # ITB hits +system.cpu0.itb.fetch_misses 3572 # ITB misses system.cpu0.itb.fetch_acv 127 # ITB acv -system.cpu0.itb.fetch_accesses 3859019 # ITB accesses +system.cpu0.itb.fetch_accesses 3529298 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -283,154 +316,154 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3740670264 # number of cpu cycles simulated +system.cpu0.numCycles 3738722771 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 57222643 # Number of instructions committed -system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses -system.cpu0.num_func_calls 1399593 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls -system.cpu0.num_int_insts 53250480 # number of integer instructions -system.cpu0.num_fp_insts 299810 # number of float instructions -system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written -system.cpu0.num_mem_refs 15135573 # number of memory refs -system.cpu0.num_load_insts 9184516 # Number of load instructions -system.cpu0.num_store_insts 5951057 # Number of store instructions -system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles -system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles -system.cpu0.Branches 8650822 # Number of branches fetched -system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction -system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction -system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction -system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatDiv 2221 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction -system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction -system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction -system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction +system.cpu0.committedInsts 49477745 # Number of instructions committed +system.cpu0.committedOps 49477745 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 46201705 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 197598 # Number of float alu accesses +system.cpu0.num_func_calls 1124633 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 6043603 # number of instructions that are conditional controls +system.cpu0.num_int_insts 46201705 # number of integer instructions +system.cpu0.num_fp_insts 197598 # number of float instructions +system.cpu0.num_int_register_reads 64003225 # number of times the integer registers were read +system.cpu0.num_int_register_writes 34834421 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 97440 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 98967 # number of times the floating registers were written +system.cpu0.num_mem_refs 12536107 # number of memory refs +system.cpu0.num_load_insts 7783754 # Number of load instructions +system.cpu0.num_store_insts 4752353 # Number of store instructions +system.cpu0.num_idle_cycles 3689239788.666409 # Number of idle cycles +system.cpu0.num_busy_cycles 49482982.333591 # Number of busy cycles +system.cpu0.not_idle_fraction 0.013235 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.986765 # Percentage of idle cycles +system.cpu0.Branches 7530826 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2589816 5.23% 5.23% # Class of executed instruction +system.cpu0.op_class::IntAlu 33436017 67.57% 72.80% # Class of executed instruction +system.cpu0.op_class::IntMult 50540 0.10% 72.90% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 72.90% # Class of executed instruction +system.cpu0.op_class::FloatAdd 27840 0.06% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatDiv 2233 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 72.96% # Class of executed instruction +system.cpu0.op_class::MemRead 7945590 16.06% 89.02% # Class of executed instruction +system.cpu0.op_class::MemWrite 4758292 9.62% 98.63% # Class of executed instruction +system.cpu0.op_class::IprAccess 675558 1.37% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 57230699 # Class of executed instruction +system.cpu0.op_class::total 49485886 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 150435 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 51398 40.00% 40.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 243 0.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1907 1.48% 41.67% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 514 0.40% 42.07% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 74446 57.93% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 128508 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 51050 48.97% 48.97% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 243 0.23% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1907 1.83% 51.03% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 514 0.49% 51.52% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 50536 48.48% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 104250 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1853222721000 99.14% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 82001000 0.00% 99.14% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 57621500 0.00% 99.15% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 15975327000 0.85% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1869357780500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.993229 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed -system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed -system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed -system.cpu0.kern.syscall::6 32 14.16% 26.11% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.44% 26.55% # number of syscalls executed -system.cpu0.kern.syscall::15 1 0.44% 26.99% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.98% 30.97% # number of syscalls executed -system.cpu0.kern.syscall::19 8 3.54% 34.51% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.65% 37.17% # number of syscalls executed -system.cpu0.kern.syscall::23 2 0.88% 38.05% # number of syscalls executed -system.cpu0.kern.syscall::24 4 1.77% 39.82% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.10% 42.92% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.88% 43.81% # number of syscalls executed -system.cpu0.kern.syscall::45 37 16.37% 60.18% # number of syscalls executed -system.cpu0.kern.syscall::47 4 1.77% 61.95% # number of syscalls executed -system.cpu0.kern.syscall::48 8 3.54% 65.49% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.42% 69.91% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.44% 70.35% # number of syscalls executed -system.cpu0.kern.syscall::59 4 1.77% 72.12% # number of syscalls executed -system.cpu0.kern.syscall::71 30 13.27% 85.40% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.33% 86.73% # number of syscalls executed -system.cpu0.kern.syscall::74 8 3.54% 90.27% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.44% 90.71% # number of syscalls executed -system.cpu0.kern.syscall::90 2 0.88% 91.59% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.98% 95.58% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.88% 96.46% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.88% 97.35% # number of syscalls executed -system.cpu0.kern.syscall::132 2 0.88% 98.23% # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.678828 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811234 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 6 2.63% 2.63% # number of syscalls executed +system.cpu0.kern.syscall::3 20 8.77% 11.40% # number of syscalls executed +system.cpu0.kern.syscall::4 2 0.88% 12.28% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.04% 26.32% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.44% 26.75% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.44% 27.19% # number of syscalls executed +system.cpu0.kern.syscall::17 9 3.95% 31.14% # number of syscalls executed +system.cpu0.kern.syscall::19 8 3.51% 34.65% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.63% 37.28% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.88% 38.16% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.75% 39.91% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.07% 42.98% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.88% 43.86% # number of syscalls executed +system.cpu0.kern.syscall::45 37 16.23% 60.09% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.75% 61.84% # number of syscalls executed +system.cpu0.kern.syscall::48 8 3.51% 65.35% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.39% 69.74% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.44% 70.18% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.19% 72.37% # number of syscalls executed +system.cpu0.kern.syscall::71 30 13.16% 85.53% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.32% 86.84% # number of syscalls executed +system.cpu0.kern.syscall::74 8 3.51% 90.35% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.44% 90.79% # number of syscalls executed +system.cpu0.kern.syscall::90 2 0.88% 91.67% # number of syscalls executed +system.cpu0.kern.syscall::92 9 3.95% 95.61% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.88% 96.49% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.88% 97.37% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.88% 98.25% # number of syscalls executed system.cpu0.kern.syscall::144 2 0.88% 99.12% # number of syscalls executed system.cpu0.kern.syscall::147 2 0.88% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 226 # number of syscalls executed +system.cpu0.kern.syscall::total 228 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 110 0.06% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed -system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed -system.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed -system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed -system.cpu0.kern.callpal::rdusp 7 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.18% # number of callpals executed -system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed -system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 183289 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches +system.cpu0.kern.callpal::wripir 616 0.45% 0.45% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.46% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.46% # number of callpals executed +system.cpu0.kern.callpal::swpctx 2743 2.02% 2.47% # number of callpals executed +system.cpu0.kern.callpal::tbi 39 0.03% 2.50% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed +system.cpu0.kern.callpal::swpipl 121668 89.51% 92.02% # number of callpals executed +system.cpu0.kern.callpal::rdps 6149 4.52% 96.54% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.54% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.54% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.01% 96.55% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.55% # number of callpals executed +system.cpu0.kern.callpal::rti 4175 3.07% 99.62% # number of callpals executed +system.cpu0.kern.callpal::callsys 369 0.27% 99.89% # number of callpals executed +system.cpu0.kern.callpal::imb 146 0.11% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 135929 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6593 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1155 -system.cpu0.kern.mode_good::user 1156 +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.177764 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.301957 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1868349152500 99.95% 99.95% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1008627000 0.05% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3763 # number of times the context was actually changed +system.cpu0.kern.swap_context 2744 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -462,51 +495,117 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 133353257 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 246745714 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes) -system.iobus.throughput 1460501 # Throughput (bytes/s) -system.iobus.data_through_bus 2731626 # Total data (bytes) -system.cpu0.icache.tags.replacements 884408 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy +system.toL2Bus.trans_dist::ReadReq 2732156 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2732156 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14588 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 777631 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 19617 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 14229 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 33846 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295242 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295242 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1237878 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 4301883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 762376 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 627158 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6929295 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39612096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 155765243 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 24396032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357911 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 243131282 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41895 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3873157 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.010774 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.103239 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3831426 98.92% 98.92% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3873157 # Request fanout histogram +system.iobus.trans_dist::ReadReq 7628 # Transaction distribution +system.iobus.trans_dist::ReadResp 7628 # Transaction distribution +system.iobus.trans_dist::WriteReq 56140 # Transaction distribution +system.iobus.trans_dist::WriteResp 14588 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14686 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18036 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 44074 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 127536 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 58744 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9018 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 86162 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2747818 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.icache.tags.replacements 618292 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.240644 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 48866947 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 618804 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 78.969992 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9786048500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.240644 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998517 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 116 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 333 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits -system.cpu0.icache.overall_hits::total 56345695 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses -system.cpu0.icache.overall_misses::total 885004 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015464 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015464 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 50104825 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 50104825 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 48866947 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 48866947 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 48866947 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 48866947 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 48866947 # number of overall hits +system.cpu0.icache.overall_hits::total 48866947 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 618939 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 618939 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 618939 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 618939 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 618939 # number of overall misses +system.cpu0.icache.overall_misses::total 618939 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 49485886 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 49485886 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 49485886 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 49485886 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 49485886 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.012507 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012507 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.012507 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012507 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.012507 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,70 +615,70 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1978697 # number of replacements -system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1781371 # number of replacements +system.cpu0.dcache.tags.tagsinuse 506.187328 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10705763 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1781883 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 6.008118 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.187328 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988647 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988647 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 446 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits -system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses -system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049754 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085785 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003811 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133696 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.133696 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133696 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.133696 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 51822042 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51822042 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6068881 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6068881 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4360082 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4360082 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 127592 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 127592 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 132846 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 132846 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10428963 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10428963 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10428963 # number of overall hits +system.cpu0.dcache.overall_hits::total 10428963 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1560069 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1560069 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 236541 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 236541 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 12626 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 12626 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6924 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6924 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1796610 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1796610 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1796610 # number of overall misses +system.cpu0.dcache.overall_misses::total 1796610 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7628950 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4596623 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 140218 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 140218 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 139770 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 139770 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12225573 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12225573 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.204493 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051460 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051460 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.090046 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049539 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049539 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.146955 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146955 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.146955 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146955 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -588,29 +687,29 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks -system.cpu0.dcache.writebacks::total 775643 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 633103 # number of writebacks +system.cpu0.dcache.writebacks::total 633103 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1163439 # DTB read hits -system.cpu1.dtb.read_misses 3277 # DTB read misses +system.cpu1.dtb.read_hits 2831559 # DTB read hits +system.cpu1.dtb.read_misses 3191 # DTB read misses system.cpu1.dtb.read_acv 58 # DTB read access violations -system.cpu1.dtb.read_accesses 220342 # DTB read accesses -system.cpu1.dtb.write_hits 751446 # DTB write hits -system.cpu1.dtb.write_misses 415 # DTB write misses -system.cpu1.dtb.write_acv 58 # DTB write access violations -system.cpu1.dtb.write_accesses 103280 # DTB write accesses -system.cpu1.dtb.data_hits 1914885 # DTB hits -system.cpu1.dtb.data_misses 3692 # DTB misses -system.cpu1.dtb.data_acv 116 # DTB access violations -system.cpu1.dtb.data_accesses 323622 # DTB accesses -system.cpu1.itb.fetch_hits 1468399 # ITB hits -system.cpu1.itb.fetch_misses 1539 # ITB misses +system.cpu1.dtb.read_accesses 198160 # DTB read accesses +system.cpu1.dtb.write_hits 2101673 # DTB write hits +system.cpu1.dtb.write_misses 412 # DTB write misses +system.cpu1.dtb.write_acv 55 # DTB write access violations +system.cpu1.dtb.write_accesses 90619 # DTB write accesses +system.cpu1.dtb.data_hits 4933232 # DTB hits +system.cpu1.dtb.data_misses 3603 # DTB misses +system.cpu1.dtb.data_acv 113 # DTB access violations +system.cpu1.dtb.data_accesses 288779 # DTB accesses +system.cpu1.itb.fetch_hits 1950883 # ITB hits +system.cpu1.itb.fetch_misses 1451 # ITB misses system.cpu1.itb.fetch_acv 57 # ITB acv -system.cpu1.itb.fetch_accesses 1469938 # ITB accesses +system.cpu1.itb.fetch_accesses 1952334 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -623,175 +722,176 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3740248099 # number of cpu cycles simulated +system.cpu1.numCycles 3738296587 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 5931963 # Number of instructions committed -system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses -system.cpu1.num_func_calls 182742 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls -system.cpu1.num_int_insts 5550581 # number of integer instructions -system.cpu1.num_fp_insts 28590 # number of float instructions -system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read -system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written -system.cpu1.num_mem_refs 1926244 # number of memory refs -system.cpu1.num_load_insts 1170888 # Number of load instructions -system.cpu1.num_store_insts 755356 # Number of store instructions -system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles -system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles -system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles -system.cpu1.Branches 836749 # Number of branches fetched -system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction -system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction -system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1421 0.02% 63.88% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.88% # Class of executed instruction -system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Class of executed instruction -system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction -system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction +system.cpu1.committedInsts 15522159 # Number of instructions committed +system.cpu1.committedOps 15522159 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 14295544 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 198941 # Number of float alu accesses +system.cpu1.num_func_calls 493140 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1540068 # number of instructions that are conditional controls +system.cpu1.num_int_insts 14295544 # number of integer instructions +system.cpu1.num_fp_insts 198941 # number of float instructions +system.cpu1.num_int_register_reads 19514289 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10457600 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 101734 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 104129 # number of times the floating registers were written +system.cpu1.num_mem_refs 4961786 # number of memory refs +system.cpu1.num_load_insts 2849090 # Number of load instructions +system.cpu1.num_store_insts 2112696 # Number of store instructions +system.cpu1.num_idle_cycles 3722773649.474793 # Number of idle cycles +system.cpu1.num_busy_cycles 15522937.525207 # Number of busy cycles +system.cpu1.not_idle_fraction 0.004152 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.995848 # Percentage of idle cycles +system.cpu1.Branches 2214163 # Number of branches fetched +system.cpu1.op_class::No_OpClass 856043 5.51% 5.51% # Class of executed instruction +system.cpu1.op_class::IntAlu 9156766 58.98% 64.49% # Class of executed instruction +system.cpu1.op_class::IntMult 25065 0.16% 64.65% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.65% # Class of executed instruction +system.cpu1.op_class::FloatAdd 12426 0.08% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.73% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1409 0.01% 64.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.74% # Class of executed instruction +system.cpu1.op_class::MemRead 2937016 18.92% 83.66% # Class of executed instruction +system.cpu1.op_class::MemWrite 2113897 13.62% 97.27% # Class of executed instruction +system.cpu1.op_class::IprAccess 423253 2.73% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 5935771 # Class of executed instruction +system.cpu1.op_class::total 15525875 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 110 0.36% 40.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 18518 60.00% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 30863 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 10318 45.77% 45.77% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2704 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 92290 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 31964 39.34% 39.34% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1906 2.35% 41.68% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 616 0.76% 42.44% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 46769 57.56% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 81255 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 30935 48.51% 48.51% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1906 2.99% 51.49% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 616 0.97% 52.46% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 30319 47.54% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 63776 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1856123490500 99.30% 99.30% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 81958000 0.00% 99.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 70736500 0.00% 99.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 12870743500 0.69% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1869146928500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967808 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.551247 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.730422 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::2 2 2.00% 2.00% # number of syscalls executed -system.cpu1.kern.syscall::3 11 11.00% 13.00% # number of syscalls executed -system.cpu1.kern.syscall::4 2 2.00% 15.00% # number of syscalls executed -system.cpu1.kern.syscall::6 10 10.00% 25.00% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.00% 31.00% # number of syscalls executed -system.cpu1.kern.syscall::19 2 2.00% 33.00% # number of syscalls executed -system.cpu1.kern.syscall::23 2 2.00% 35.00% # number of syscalls executed -system.cpu1.kern.syscall::24 2 2.00% 37.00% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.00% 41.00% # number of syscalls executed -system.cpu1.kern.syscall::45 17 17.00% 58.00% # number of syscalls executed -system.cpu1.kern.syscall::47 2 2.00% 60.00% # number of syscalls executed -system.cpu1.kern.syscall::48 2 2.00% 62.00% # number of syscalls executed -system.cpu1.kern.syscall::59 3 3.00% 65.00% # number of syscalls executed -system.cpu1.kern.syscall::71 24 24.00% 89.00% # number of syscalls executed -system.cpu1.kern.syscall::74 8 8.00% 97.00% # number of syscalls executed -system.cpu1.kern.syscall::90 1 1.00% 98.00% # number of syscalls executed -system.cpu1.kern.syscall::132 2 2.00% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 100 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.648271 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.784887 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 2 2.04% 2.04% # number of syscalls executed +system.cpu1.kern.syscall::3 10 10.20% 12.24% # number of syscalls executed +system.cpu1.kern.syscall::4 2 2.04% 14.29% # number of syscalls executed +system.cpu1.kern.syscall::6 10 10.20% 24.49% # number of syscalls executed +system.cpu1.kern.syscall::17 6 6.12% 30.61% # number of syscalls executed +system.cpu1.kern.syscall::19 2 2.04% 32.65% # number of syscalls executed +system.cpu1.kern.syscall::23 2 2.04% 34.69% # number of syscalls executed +system.cpu1.kern.syscall::24 2 2.04% 36.73% # number of syscalls executed +system.cpu1.kern.syscall::33 4 4.08% 40.82% # number of syscalls executed +system.cpu1.kern.syscall::45 17 17.35% 58.16% # number of syscalls executed +system.cpu1.kern.syscall::47 2 2.04% 60.20% # number of syscalls executed +system.cpu1.kern.syscall::48 2 2.04% 62.24% # number of syscalls executed +system.cpu1.kern.syscall::59 2 2.04% 64.29% # number of syscalls executed +system.cpu1.kern.syscall::71 24 24.49% 88.78% # number of syscalls executed +system.cpu1.kern.syscall::74 8 8.16% 96.94% # number of syscalls executed +system.cpu1.kern.syscall::90 1 1.02% 97.96% # number of syscalls executed +system.cpu1.kern.syscall::132 2 2.04% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 98 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 8 0.02% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 470 1.46% 1.50% # number of callpals executed -system.cpu1.kern.callpal::tbi 15 0.05% 1.54% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.02% 1.57% # number of callpals executed -system.cpu1.kern.callpal::swpipl 26238 81.66% 83.22% # number of callpals executed -system.cpu1.kern.callpal::rdps 2576 8.02% 91.24% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 91.25% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::rdusp 2 0.01% 91.26% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 91.27% # number of callpals executed -system.cpu1.kern.callpal::rti 2607 8.11% 99.39% # number of callpals executed -system.cpu1.kern.callpal::callsys 158 0.49% 99.88% # number of callpals executed -system.cpu1.kern.callpal::imb 38 0.12% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 514 0.61% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.61% # number of callpals executed +system.cpu1.kern.callpal::swpctx 2506 2.96% 3.58% # number of callpals executed +system.cpu1.kern.callpal::tbi 14 0.02% 3.59% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.60% # number of callpals executed +system.cpu1.kern.callpal::swpipl 74617 88.26% 91.86% # number of callpals executed +system.cpu1.kern.callpal::rdps 2575 3.05% 94.91% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.91% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.00% 94.91% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 94.91% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.92% # number of callpals executed +system.cpu1.kern.callpal::rti 4115 4.87% 99.79% # number of callpals executed +system.cpu1.kern.callpal::callsys 146 0.17% 99.96% # number of callpals executed +system.cpu1.kern.callpal::imb 34 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 32131 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1033 # number of protection mode switches -system.cpu1.kern.mode_switch::user 580 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 612 -system.cpu1.kern.mode_good::user 580 -system.cpu1.kern.mode_good::idle 32 -system.cpu1.kern.mode_switch_good::kernel 0.592449 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 84542 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2548 # number of protection mode switches +system.cpu1.kern.mode_switch::user 564 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 3056 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 1106 +system.cpu1.kern.mode_good::user 564 +system.cpu1.kern.mode_good::idle 542 +system.cpu1.kern.mode_switch_good::kernel 0.434066 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 471 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 103097 # number of replacements -system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy +system.cpu1.kern.mode_switch_good::idle 0.177356 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.358625 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 5986368000 0.32% 0.32% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 456602000 0.02% 0.34% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1862102404500 99.66% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 2507 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 380647 # number of replacements +system.cpu1.icache.tags.tagsinuse 453.133719 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 15144687 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 381159 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.733253 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1859777157500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 453.133719 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.885027 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.885027 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits -system.cpu1.icache.overall_hits::total 5832135 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses -system.cpu1.icache.overall_misses::total 103636 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 15907063 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15907063 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 15144687 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 15144687 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 15144687 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 15144687 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 15144687 # number of overall hits +system.cpu1.icache.overall_hits::total 15144687 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 381188 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 381188 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 381188 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 381188 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 381188 # number of overall misses +system.cpu1.icache.overall_misses::total 381188 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 15525875 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 15525875 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 15525875 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 15525875 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 15525875 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024552 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024552 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024552 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024552 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024552 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -801,69 +901,69 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 62047 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits -system.cpu1.dcache.overall_hits::total 1816974 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses -system.cpu1.dcache.overall_misses::total 67296 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses +system.cpu1.dcache.tags.replacements 201757 # number of replacements +system.cpu1.dcache.tags.tagsinuse 497.601960 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4718401 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 202065 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.350907 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 15869420000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 497.601960 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.971879 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.601562 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 20020608 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 20020608 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2632688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2632688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1954642 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1954642 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 61098 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 61098 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 64210 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 64210 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 4587330 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 4587330 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 4587330 # number of overall hits +system.cpu1.dcache.overall_hits::total 4587330 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 140885 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 140885 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 78318 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 78318 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11000 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11000 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 7305 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 7305 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 219203 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 219203 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 219203 # number of overall misses +system.cpu1.dcache.overall_misses::total 219203 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2773573 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2032960 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2032960 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72098 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 72098 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 71515 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 71515 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4806533 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4806533 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.050795 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.050795 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.038524 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.038524 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.152570 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102146 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102146 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.045605 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.045605 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.045605 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.045605 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,8 +972,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks -system.cpu1.dcache.writebacks::total 41020 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 144528 # number of writebacks +system.cpu1.dcache.writebacks::total 144528 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 8a7bfd4c1..d02473de7 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -1,58 +1,90 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.829332 # Number of seconds simulated -sim_ticks 1829332049000 # Number of ticks simulated -final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1829331993500 # Number of ticks simulated +final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2314619 # Simulator instruction rate (inst/s) -host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 70524837278 # Simulator tick rate (ticks/s) -host_mem_usage 315304 # Number of bytes of host memory used -host_seconds 25.94 # Real time elapsed on the host -sim_insts 60038433 # Number of instructions simulated -sim_ops 60038433 # Number of ops (including micro ops) simulated +host_inst_rate 2920462 # Simulator instruction rate (inst/s) +host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88984410684 # Simulator tick rate (ticks/s) +host_mem_usage 366200 # Number of bytes of host memory used +host_seconds 20.56 # Real time elapsed on the host +sim_insts 60038469 # Number of instructions simulated +sim_ops 60038469 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory +system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory +system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory +system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 41099809 # Throughput (bytes/s) -system.membus.data_through_bus 75185198 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 948404 # Transaction distribution +system.membus.trans_dist::ReadResp 948404 # Transaction distribution +system.membus.trans_dist::WriteReq 9838 # Transaction distribution +system.membus.trans_dist::WriteResp 9838 # Transaction distribution +system.membus.trans_dist::Writeback 74279 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 132 # Transaction distribution +system.membus.trans_dist::UpgradeResp 132 # Transaction distribution +system.membus.trans_dist::ReadExReq 116985 # Transaction distribution +system.membus.trans_dist::ReadExResp 116985 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 1174168 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 1174168 # Request fanout histogram system.iocache.tags.replacements 41686 # number of replacements -system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -108,15 +140,15 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9710428 # DTB read hits +system.cpu.dtb.read_hits 9710423 # DTB read hits system.cpu.dtb.read_misses 10329 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations system.cpu.dtb.read_accesses 728856 # DTB read accesses -system.cpu.dtb.write_hits 6352498 # DTB write hits +system.cpu.dtb.write_hits 6352496 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations system.cpu.dtb.write_accesses 291931 # DTB write accesses -system.cpu.dtb.data_hits 16062926 # DTB hits +system.cpu.dtb.data_hits 16062919 # DTB hits system.cpu.dtb.data_misses 11471 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020787 # DTB accesses @@ -136,32 +168,32 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3658664099 # number of cpu cycles simulated +system.cpu.numCycles 3658670345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60038433 # Number of instructions committed -system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses +system.cpu.committedInsts 60038469 # Number of instructions committed +system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls -system.cpu.num_int_insts 55913650 # number of integer instructions +system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls +system.cpu.num_int_insts 55913692 # number of integer instructions system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read -system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written +system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read +system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 16115710 # number of memory refs -system.cpu.num_load_insts 9747514 # Number of load instructions -system.cpu.num_store_insts 6368196 # Number of store instructions -system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles -system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles -system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983585 # Percentage of idle cycles -system.cpu.Branches 9064413 # Number of branches fetched -system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction -system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction -system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction +system.cpu.num_mem_refs 16115703 # number of memory refs +system.cpu.num_load_insts 9747509 # Number of load instructions +system.cpu.num_store_insts 6368194 # Number of store instructions +system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles +system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles +system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983587 # Percentage of idle cycles +system.cpu.Branches 9064428 # Number of branches fetched +system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction +system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction +system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction @@ -189,11 +221,11 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction -system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction -system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction +system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction +system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 60050271 # Class of executed instruction +system.cpu.op_class::total 60050307 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed @@ -207,11 +239,11 @@ system.cpu.kern.ipl_good::21 243 0.16% 49.46% # nu system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -275,9 +307,9 @@ system.cpu.kern.mode_switch_good::kernel 0.320726 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -310,15 +342,50 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1480181 # Throughput (bytes/s) -system.iobus.data_through_bus 2707742 # Total data (bytes) -system.cpu.icache.tags.replacements 919591 # number of replacements -system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor +system.iobus.trans_dist::ReadReq 7358 # Transaction distribution +system.iobus.trans_dist::ReadResp 7358 # Transaction distribution +system.iobus.trans_dist::WriteReq 51390 # Transaction distribution +system.iobus.trans_dist::WriteResp 9838 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) +system.cpu.icache.tags.replacements 919603 # number of replacements +system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -326,26 +393,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63 system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits -system.cpu.icache.overall_hits::total 59130053 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses -system.cpu.icache.overall_misses::total 920218 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits +system.cpu.icache.overall_hits::total 59130077 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses +system.cpu.icache.overall_misses::total 920230 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses @@ -361,17 +428,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 992295 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 992289 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id @@ -381,64 +448,64 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits -system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits +system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses -system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses +system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -447,14 +514,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks -system.cpu.l2cache.writebacks::total 74285 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks +system.cpu.l2cache.writebacks::total 74279 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2042683 # number of replacements +system.cpu.dcache.tags.replacements 2042707 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy @@ -464,52 +531,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits -system.cpu.dcache.overall_hits::total 13656011 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses -system.cpu.dcache.overall_misses::total 2026051 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits +system.cpu.dcache.overall_hits::total 13655981 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses +system.cpu.dcache.overall_misses::total 2026074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses +system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,11 +585,35 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks -system.cpu.dcache.writebacks::total 833475 # number of writebacks +system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks +system.cpu.dcache.writebacks::total 833484 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41883 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 034bdfed2..977509ec9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962815 # Number of seconds simulated -sim_ticks 1962815218500 # Number of ticks simulated -final_tick 1962815218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.961827 # Number of seconds simulated +sim_ticks 1961826628500 # Number of ticks simulated +final_tick 1961826628500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1506000 # Simulator instruction rate (inst/s) -host_op_rate 1505999 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 49787604582 # Simulator tick rate (ticks/s) -host_mem_usage 317424 # Number of bytes of host memory used -host_seconds 39.42 # Real time elapsed on the host -sim_insts 59372159 # Number of instructions simulated -sim_ops 59372159 # Number of ops (including micro ops) simulated +host_inst_rate 1388652 # Simulator instruction rate (inst/s) +host_op_rate 1388652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44739465331 # Simulator tick rate (ticks/s) +host_mem_usage 370560 # Number of bytes of host memory used +host_seconds 43.85 # Real time elapsed on the host +sim_insts 60892387 # Number of instructions simulated +sim_ops 60892387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 724992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24166912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 833152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24900864 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 138560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1080576 # Number of bytes read from this memory -system.physmem.bytes_read::total 26112000 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 724992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 138560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 863552 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5090112 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 31872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 336832 # Number of bytes read from this memory +system.physmem.bytes_read::total 26103680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 833152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5078656 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7749440 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11328 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 377608 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7737984 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13018 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 389076 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16884 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408000 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 79533 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 5263 # Number of read requests responded to by this memory +system.physmem.num_reads::total 407870 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 79354 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121085 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 369363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12312372 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 120906 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 424682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12692693 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 70592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 550524 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13303341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369363 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 70592 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 439956 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2593271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1354854 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3948125 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2593271 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12312372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 70592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 550524 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17251466 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408000 # Number of read requests accepted -system.physmem.writeReqs 121085 # Number of write requests accepted -system.physmem.readBursts 408000 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 121085 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26099968 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 7747840 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26112000 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7749440 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_read::cpu1.inst 16246 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13305804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 424682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16246 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2588738 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1355537 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3944275 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2588738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 424682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12692693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1356026 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16246 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17250079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407870 # Number of read requests accepted +system.physmem.writeReqs 120906 # Number of write requests accepted +system.physmem.readBursts 407870 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 120906 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26092032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue +system.physmem.bytesWritten 7736064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26103680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7737984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3360 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25223 # Per bank write bursts -system.physmem.perBankRdBursts::1 25569 # Per bank write bursts -system.physmem.perBankRdBursts::2 25254 # Per bank write bursts -system.physmem.perBankRdBursts::3 25702 # Per bank write bursts -system.physmem.perBankRdBursts::4 25695 # Per bank write bursts -system.physmem.perBankRdBursts::5 25237 # Per bank write bursts -system.physmem.perBankRdBursts::6 25154 # Per bank write bursts -system.physmem.perBankRdBursts::7 25289 # Per bank write bursts -system.physmem.perBankRdBursts::8 25197 # Per bank write bursts -system.physmem.perBankRdBursts::9 25673 # Per bank write bursts -system.physmem.perBankRdBursts::10 25761 # Per bank write bursts -system.physmem.perBankRdBursts::11 25821 # Per bank write bursts -system.physmem.perBankRdBursts::12 25887 # Per bank write bursts -system.physmem.perBankRdBursts::13 25811 # Per bank write bursts -system.physmem.perBankRdBursts::14 25568 # Per bank write bursts -system.physmem.perBankRdBursts::15 24971 # Per bank write bursts -system.physmem.perBankWrBursts::0 7862 # Per bank write bursts -system.physmem.perBankWrBursts::1 7635 # Per bank write bursts -system.physmem.perBankWrBursts::2 7481 # Per bank write bursts -system.physmem.perBankWrBursts::3 8078 # Per bank write bursts -system.physmem.perBankWrBursts::4 7635 # Per bank write bursts -system.physmem.perBankWrBursts::5 7244 # Per bank write bursts -system.physmem.perBankWrBursts::6 7160 # Per bank write bursts -system.physmem.perBankWrBursts::7 6937 # Per bank write bursts -system.physmem.perBankWrBursts::8 6882 # Per bank write bursts -system.physmem.perBankWrBursts::9 7297 # Per bank write bursts -system.physmem.perBankWrBursts::10 7429 # Per bank write bursts -system.physmem.perBankWrBursts::11 7398 # Per bank write bursts -system.physmem.perBankWrBursts::12 8124 # Per bank write bursts -system.physmem.perBankWrBursts::13 8265 # Per bank write bursts -system.physmem.perBankWrBursts::14 8169 # Per bank write bursts -system.physmem.perBankWrBursts::15 7464 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6995 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25277 # Per bank write bursts +system.physmem.perBankRdBursts::1 25718 # Per bank write bursts +system.physmem.perBankRdBursts::2 25598 # Per bank write bursts +system.physmem.perBankRdBursts::3 25075 # Per bank write bursts +system.physmem.perBankRdBursts::4 25186 # Per bank write bursts +system.physmem.perBankRdBursts::5 25258 # Per bank write bursts +system.physmem.perBankRdBursts::6 25824 # Per bank write bursts +system.physmem.perBankRdBursts::7 25548 # Per bank write bursts +system.physmem.perBankRdBursts::8 25573 # Per bank write bursts +system.physmem.perBankRdBursts::9 25196 # Per bank write bursts +system.physmem.perBankRdBursts::10 25177 # Per bank write bursts +system.physmem.perBankRdBursts::11 25610 # Per bank write bursts +system.physmem.perBankRdBursts::12 25669 # Per bank write bursts +system.physmem.perBankRdBursts::13 25717 # Per bank write bursts +system.physmem.perBankRdBursts::14 26016 # Per bank write bursts +system.physmem.perBankRdBursts::15 25246 # Per bank write bursts +system.physmem.perBankWrBursts::0 7929 # Per bank write bursts +system.physmem.perBankWrBursts::1 7788 # Per bank write bursts +system.physmem.perBankWrBursts::2 7545 # Per bank write bursts +system.physmem.perBankWrBursts::3 7026 # Per bank write bursts +system.physmem.perBankWrBursts::4 7134 # Per bank write bursts +system.physmem.perBankWrBursts::5 7133 # Per bank write bursts +system.physmem.perBankWrBursts::6 7657 # Per bank write bursts +system.physmem.perBankWrBursts::7 7252 # Per bank write bursts +system.physmem.perBankWrBursts::8 7395 # Per bank write bursts +system.physmem.perBankWrBursts::9 7084 # Per bank write bursts +system.physmem.perBankWrBursts::10 7119 # Per bank write bursts +system.physmem.perBankWrBursts::11 7401 # Per bank write bursts +system.physmem.perBankWrBursts::12 7832 # Per bank write bursts +system.physmem.perBankWrBursts::13 8315 # Per bank write bursts +system.physmem.perBankWrBursts::14 8567 # Per bank write bursts +system.physmem.perBankWrBursts::15 7699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 1962808109000 # Total gap between requests +system.physmem.numWrRetry 8 # Number of times write queue was full causing retry +system.physmem.totGap 1961819616500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408000 # Read request sizes (log2) +system.physmem.readPktSize::6 407870 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 121085 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 407738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see +system.physmem.writePktSize::6 120906 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 407616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -161,357 +161,363 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 512.666919 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 309.343673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.043592 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15664 23.73% 23.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11865 17.97% 41.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5137 7.78% 49.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3080 4.67% 54.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3330 5.04% 59.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1778 2.69% 61.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1463 2.22% 64.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1306 1.98% 66.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22400 33.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66023 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5447 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.865981 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2190.069327 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5442 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1871 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66427 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 509.252202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 306.095148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 413.238328 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15972 24.04% 24.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12116 18.24% 42.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5140 7.74% 50.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2994 4.51% 54.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3304 4.97% 59.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1746 2.63% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1491 2.24% 64.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1317 1.98% 66.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22347 33.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66427 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 75.036996 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2192.886898 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 5428 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5447 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.225078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.080270 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.855094 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4780 87.75% 87.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 19 0.35% 88.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.29% 88.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 235 4.31% 92.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 38 0.70% 93.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 9 0.17% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 13 0.24% 93.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.18% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 23 0.42% 94.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.04% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 94.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 7 0.13% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.09% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 94.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 29 0.53% 95.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.26% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.11% 95.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.11% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 182 3.34% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.02% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.18% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 5 0.09% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.09% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5433 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5433 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.248482 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.059784 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.984616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4773 87.85% 87.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 17 0.31% 88.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 17 0.31% 88.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 237 4.36% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 33 0.61% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 9 0.17% 93.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 6 0.11% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 9 0.17% 93.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.44% 94.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.02% 94.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 10 0.18% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.11% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.06% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.07% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 32 0.59% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 11 0.20% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.06% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 9 0.17% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 180 3.31% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.07% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.07% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 5 0.09% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.13% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.24% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5447 # Writes before turning the bus around for reads -system.physmem.totQLat 2167934250 # Total ticks spent queuing -system.physmem.totMemAccLat 9814409250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2039060000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5316.01 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5433 # Writes before turning the bus around for reads +system.physmem.totQLat 2198653000 # Total ticks spent queuing +system.physmem.totMemAccLat 9842803000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2038440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5392.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24066.01 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24142.98 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.30 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.30 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.31 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.94 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing -system.physmem.readRowHits 365758 # Number of row buffer hits during reads -system.physmem.writeRowHits 97091 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.69 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.18 # Row buffer hit rate for writes -system.physmem.avgGap 3709816.21 # Average gap between requests -system.physmem.pageHitRate 87.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1840831671000 # Time in different power states -system.physmem.memoryStateTime::REF 65542620000 # Time in different power states +system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing +system.physmem.readRowHits 365377 # Number of row buffer hits during reads +system.physmem.writeRowHits 96760 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.03 # Row buffer hit rate for writes +system.physmem.avgGap 3710114.71 # Average gap between requests +system.physmem.pageHitRate 87.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1840052567250 # Time in different power states +system.physmem.memoryStateTime::REF 65509600000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 56438386500 # Time in different power states +system.physmem.memoryStateTime::ACT 56261656500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17291736 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 292660 # Transaction distribution -system.membus.trans_dist::ReadResp 292660 # Transaction distribution -system.membus.trans_dist::WriteReq 12414 # Transaction distribution -system.membus.trans_dist::WriteResp 12414 # Transaction distribution -system.membus.trans_dist::Writeback 79533 # Transaction distribution +system.membus.trans_dist::ReadReq 292757 # Transaction distribution +system.membus.trans_dist::ReadResp 292757 # Transaction distribution +system.membus.trans_dist::WriteReq 14067 # Transaction distribution +system.membus.trans_dist::WriteResp 14067 # Transaction distribution +system.membus.trans_dist::Writeback 79354 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4556 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1019 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3360 # Transaction distribution -system.membus.trans_dist::ReadExReq 122803 # Transaction distribution -system.membus.trans_dist::ReadExResp 122701 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39228 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 904540 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 943768 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83295 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83295 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1027063 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68738 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31201152 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31269890 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33930178 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33930178 # Total data (bytes) -system.membus.snoop_data_through_bus 10304 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 39224500 # Layer occupancy (ticks) +system.membus.trans_dist::UpgradeReq 16159 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6995 # Transaction distribution +system.membus.trans_dist::ReadExReq 123294 # Transaction distribution +system.membus.trans_dist::ReadExResp 122471 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 930313 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 972845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83293 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83293 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1056138 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81954 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31181376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31263330 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33923618 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21418 # Total snoops (count) +system.membus.snoop_fanout::samples 557197 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 557197 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 557197 # Request fanout histogram +system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1533573250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1536995500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3826483141 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3833296255 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43139750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43122000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 342222 # number of replacements -system.l2c.tags.tagsinuse 65256.426750 # Cycle average of tags in use -system.l2c.tags.total_refs 2542307 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407368 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.240812 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652281750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55518.260732 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3744.767678 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4299.632317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1171.746225 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 522.019798 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.847141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.057141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.065607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017879 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.007965 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995734 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65146 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 748 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5288 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7253 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51739 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994049 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26946350 # Number of tag accesses -system.l2c.tags.data_accesses 26946350 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 527823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 377901 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 461413 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 449863 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1817000 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 850078 # number of Writeback hits -system.l2c.Writeback_hits::total 850078 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 70 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 205 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 25 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 21 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 113452 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 85004 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 198456 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 527823 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 491353 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 461413 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 534867 # number of demand (read+write) hits -system.l2c.demand_hits::total 2015456 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 527823 # number of overall hits -system.l2c.overall_hits::cpu0.data 491353 # number of overall hits -system.l2c.overall_hits::cpu1.inst 461413 # number of overall hits -system.l2c.overall_hits::cpu1.data 534867 # number of overall hits -system.l2c.overall_hits::total 2015456 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11331 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 270739 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2173 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1052 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285295 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2603 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 469 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3072 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 62 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 80 # 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number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 827161250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17596749000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 162190250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 79449000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18665549500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 700470 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 348985 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1049455 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 162993 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 93496 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 256489 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7343632619 # 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number of overall miss cycles -system.l2c.overall_miss_latency::total 27166383354 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 539154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 648640 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 463586 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 450915 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2102295 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 850078 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 850078 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2738 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3277 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 87 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 101 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 220452 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 100851 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 321303 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 539154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 869092 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 463586 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 551766 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2423598 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 539154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 869092 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 463586 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 551766 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2423598 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.021016 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.417395 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004687 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.135706 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950694 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.870130 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.937443 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.712644 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.792079 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.755319 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.485366 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.157133 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382340 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.021016 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.434636 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004687 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.030627 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.168403 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.021016 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.434636 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004687 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.030627 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.168403 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72999.845556 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 64995.250038 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74638.863323 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75521.863118 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65425.435076 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 269.101037 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 744.104478 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 341.619466 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2628.919355 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1168.700000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1806.260563 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68632.080551 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73023.363097 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69198.546599 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 66561.107051 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72999.845556 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 66025.434543 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74638.863323 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 73178.900231 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 66561.107051 # average overall miss latency +system.l2c.tags.replacements 342092 # number of replacements +system.l2c.tags.tagsinuse 65220.775537 # Cycle average of tags in use +system.l2c.tags.total_refs 2444844 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 407280 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.002858 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55275.158075 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4808.073812 # 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number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4697 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 889 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 909 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1798 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 117934 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 5037 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122971 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13018 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 389564 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 5275 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 408355 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13018 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 389564 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 5275 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 408355 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 787294250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14275629250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 30082250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 14147750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15107153500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29547954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17431743 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 325358512 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22081159750 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 787294250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 20938424738 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 30082250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 325358512 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22081159750 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1373183500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17608500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1390792000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2147807000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674603500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2822410500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3520990500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692212000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4213202500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018499 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.289029 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002278 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138536 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941964 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.763135 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.866605 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.955914 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975322 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.965628 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.474650 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.106488 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.415771 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018499 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60477.358273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53748.356465 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60406.124498 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61679.338768 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 54073.440389 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -646,54 +652,54 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # 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Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.035621 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1755504878000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.569739 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035609 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035609 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # 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number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21248383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21248383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122117.143678 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122117.143678 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122117.143678 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122117.143678 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122117.143678 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -702,22 +708,22 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2504351556 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2504351556 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12199383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12199383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2501404806 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2501404806 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12199383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12199383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12199383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12199383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -726,14 +732,14 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60270.301213 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60270.301213 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70111.396552 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60199.384049 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60199.384049 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70111.396552 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70111.396552 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -751,22 +757,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 6067147 # DTB read hits +system.cpu0.dtb.read_hits 7562596 # DTB read hits system.cpu0.dtb.read_misses 7765 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 4265547 # DTB write hits +system.cpu0.dtb.write_hits 5147185 # DTB write hits system.cpu0.dtb.write_misses 910 # DTB write misses system.cpu0.dtb.write_acv 133 # DTB write access violations system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 10332694 # DTB hits +system.cpu0.dtb.data_hits 12709781 # DTB hits system.cpu0.dtb.data_misses 8675 # DTB misses system.cpu0.dtb.data_acv 343 # DTB access violations system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3354719 # ITB hits +system.cpu0.itb.fetch_hits 3660706 # ITB hits system.cpu0.itb.fetch_misses 3984 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3358703 # ITB accesses +system.cpu0.itb.fetch_accesses 3664690 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -779,91 +785,91 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925630437 # number of cpu cycles simulated +system.cpu0.numCycles 3923653257 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 38276405 # Number of instructions committed -system.cpu0.committedOps 38276405 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 35596815 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 153493 # Number of float alu accesses -system.cpu0.num_func_calls 936479 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4465105 # number of instructions that are conditional controls -system.cpu0.num_int_insts 35596815 # number of integer instructions -system.cpu0.num_fp_insts 153493 # number of float instructions -system.cpu0.num_int_register_reads 48919188 # number of times the integer registers were read -system.cpu0.num_int_register_writes 26532196 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 75000 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 75910 # number of times the floating registers were written -system.cpu0.num_mem_refs 10365856 # number of memory refs -system.cpu0.num_load_insts 6090539 # Number of load instructions -system.cpu0.num_store_insts 4275317 # Number of store instructions -system.cpu0.num_idle_cycles 3742236660.998093 # Number of idle cycles -system.cpu0.num_busy_cycles 183393776.001907 # Number of busy cycles -system.cpu0.not_idle_fraction 0.046717 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.953283 # Percentage of idle cycles -system.cpu0.Branches 5694884 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2096297 5.48% 5.48% # Class of executed instruction -system.cpu0.op_class::IntAlu 24983670 65.26% 70.73% # Class of executed instruction -system.cpu0.op_class::IntMult 39322 0.10% 70.83% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.83% # Class of executed instruction -system.cpu0.op_class::FloatAdd 24596 0.06% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.90% # Class of executed instruction -system.cpu0.op_class::MemRead 6232893 16.28% 87.18% # Class of executed instruction -system.cpu0.op_class::MemWrite 4280562 11.18% 98.36% # Class of executed instruction -system.cpu0.op_class::IprAccess 626200 1.64% 100.00% # Class of executed instruction +system.cpu0.committedInsts 48127777 # Number of instructions committed +system.cpu0.committedOps 48127777 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44643925 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 213512 # Number of float alu accesses +system.cpu0.num_func_calls 1209739 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5647172 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44643925 # number of integer instructions +system.cpu0.num_fp_insts 213512 # number of float instructions +system.cpu0.num_int_register_reads 61387452 # number of times the integer registers were read +system.cpu0.num_int_register_writes 33242964 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 104337 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 106136 # number of times the floating registers were written +system.cpu0.num_mem_refs 12750882 # number of memory refs +system.cpu0.num_load_insts 7590433 # Number of load instructions +system.cpu0.num_store_insts 5160449 # Number of store instructions +system.cpu0.num_idle_cycles 3699495012.998114 # Number of idle cycles +system.cpu0.num_busy_cycles 224158244.001886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057130 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942870 # Percentage of idle cycles +system.cpu0.Branches 7246936 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2741568 5.70% 5.70% # Class of executed instruction +system.cpu0.op_class::IntAlu 31634980 65.72% 71.41% # Class of executed instruction +system.cpu0.op_class::IntMult 52525 0.11% 71.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 26830 0.06% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1883 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.58% # Class of executed instruction +system.cpu0.op_class::MemRead 7767201 16.14% 87.72% # Class of executed instruction +system.cpu0.op_class::MemWrite 5166567 10.73% 98.45% # Class of executed instruction +system.cpu0.op_class::IprAccess 745241 1.55% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38285423 # Class of executed instruction +system.cpu0.op_class::total 48136795 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4863 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 138357 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 44808 38.76% 38.76% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.11% 38.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1975 1.71% 40.58% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 40.60% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 68665 59.40% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 115595 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 44283 48.84% 48.84% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.14% 48.98% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1975 2.18% 51.16% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.02% 51.18% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 44267 48.82% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 90672 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1909699143000 97.29% 97.29% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 95243500 0.00% 97.30% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 764380500 0.04% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 12585500 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 52243094000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962814446500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.988283 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6805 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 166328 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 57239 40.25% 40.25% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.34% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1975 1.39% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 424 0.30% 42.03% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82449 57.97% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 142218 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56706 49.09% 49.09% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1975 1.71% 50.91% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 424 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 56283 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 115519 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1902225794500 96.96% 96.96% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 94977500 0.00% 96.97% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 767421000 0.04% 97.01% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 314336500 0.02% 97.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 58423341500 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961825871000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990688 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.644681 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.784394 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682640 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.812267 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed @@ -895,37 +901,37 @@ system.cpu0.kern.syscall::144 2 0.85% 99.15% # nu system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 234 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 86 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2216 1.80% 1.87% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.04% 1.92% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.01% 1.92% # number of callpals executed -system.cpu0.kern.callpal::swpipl 109456 88.95% 90.88% # number of callpals executed -system.cpu0.kern.callpal::rdps 6662 5.41% 96.29% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.29% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.29% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.30% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.30% # number of callpals executed -system.cpu0.kern.callpal::rti 4016 3.26% 99.57% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.32% 99.89% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.11% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 123047 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 5724 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1372 # number of protection mode switches +system.cpu0.kern.callpal::wripir 506 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3105 2.06% 2.40% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.43% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 135265 89.81% 92.25% # number of callpals executed +system.cpu0.kern.callpal::rdps 6701 4.45% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::wrusp 4 0.00% 96.70% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed +system.cpu0.kern.callpal::rti 4423 2.94% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 150611 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 7020 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1371 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1371 -system.cpu0.kern.mode_good::user 1372 +system.cpu0.kern.mode_good::kernel 1370 +system.cpu0.kern.mode_good::user 1371 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.239518 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.195157 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.386556 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959023925000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3790517000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.326660 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958053140500 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3772726000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2217 # number of times the context was actually changed +system.cpu0.kern.swap_context 3106 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -957,49 +963,59 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 109416622 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2148133 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2148118 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12414 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12414 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 850078 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41558 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 4615 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1065 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 5680 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 322069 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 322069 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1078328 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2181300 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 927173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1598235 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5785036 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34505856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 81606637 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 29669504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 63812309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 209594306 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 209584002 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 5180608 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5075622491 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 2102030 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102015 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14067 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14067 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 792816 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41560 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11336 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27718 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297616 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297616 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1407417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3134555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 624007 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 452565 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5618544 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 45036672 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 120042720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 19968192 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16553666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201601250 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 98838 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3254541 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012823 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112512 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3212807 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41734 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3254541 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4795402363 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 715500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2428486244 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4030575545 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2086565739 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3169257997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 5536514081 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 1404115991 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 2646502814 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1391048 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7376 # Transaction distribution -system.iobus.trans_dist::ReadResp 7376 # Transaction distribution -system.iobus.trans_dist::WriteReq 53966 # Transaction distribution -system.iobus.trans_dist::WriteResp 53966 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10614 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 484 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 776560164 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 7373 # Transaction distribution +system.iobus.trans_dist::ReadResp 7373 # Transaction distribution +system.iobus.trans_dist::WriteReq 55619 # Transaction distribution +system.iobus.trans_dist::WriteResp 55619 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13922 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1010,30 +1026,29 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122684 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 42456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1936 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2730370 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2730370 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9969000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 42532 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125984 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 81954 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743570 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13277000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 362000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1053,67 +1068,67 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374413689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374410189 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26814000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28465000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42018250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42017000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 538541 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.393356 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 37746250 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 539053 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.023263 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 703089 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.385515 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47433077 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 703601 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.414738 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.393356 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992956 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992956 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.385515 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992940 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 38824598 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 38824598 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 37746250 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 37746250 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 37746250 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 37746250 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 37746250 # number of overall hits -system.cpu0.icache.overall_hits::total 37746250 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 539174 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 539174 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 539174 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 539174 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 539174 # number of overall misses -system.cpu0.icache.overall_misses::total 539174 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7756302744 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7756302744 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7756302744 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7756302744 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7756302744 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7756302744 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 38285424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 38285424 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 38285424 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 38285424 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 38285424 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 38285424 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014083 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014083 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014083 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014083 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014083 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014083 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14385.528130 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14385.528130 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14385.528130 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14385.528130 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14385.528130 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 48840515 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48840515 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47433077 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47433077 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47433077 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47433077 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47433077 # number of overall hits +system.cpu0.icache.overall_hits::total 47433077 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 703719 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 703719 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 703719 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 703719 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 703719 # number of overall misses +system.cpu0.icache.overall_misses::total 703719 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10017635497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10017635497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10017635497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10017635497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10017635497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10017635497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 48136796 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 48136796 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 48136796 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 48136796 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 48136796 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 48136796 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014619 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014619 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014619 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014619 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014619 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014619 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14235.277855 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14235.277855 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14235.277855 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14235.277855 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14235.277855 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1122,119 +1137,119 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 539174 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 539174 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 539174 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 539174 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 539174 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 539174 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 6673548256 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6673548256 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6673548256 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6673548256 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6673548256 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6673548256 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014083 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014083 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014083 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014083 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12377.355466 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12377.355466 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12377.355466 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 703719 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 703719 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 703719 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 703719 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 703719 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 703719 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8605152503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8605152503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8605152503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8605152503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8605152503 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8605152503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014619 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014619 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014619 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014619 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.108809 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12228.108809 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.108809 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 871192 # number of replacements -system.cpu0.dcache.tags.tagsinuse 481.742326 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9465806 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 871704 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 10.858968 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1191194 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.224955 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11513307 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1191706 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.661197 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.742326 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940903 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.940903 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.224955 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986767 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986767 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 42232679 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 42232679 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5299779 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5299779 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3905718 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3905718 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 124794 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 124794 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 131579 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 131579 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9205497 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9205497 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9205497 # number of overall hits -system.cpu0.dcache.overall_hits::total 9205497 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 645318 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 645318 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 224183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 224183 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7829 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 7829 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 497 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 497 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 869501 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 869501 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 869501 # number of overall misses -system.cpu0.dcache.overall_misses::total 869501 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 23374202500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 23374202500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9262527483 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 9262527483 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 102834500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 102834500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3584562 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3584562 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 32636729983 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32636729983 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 32636729983 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32636729983 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5945097 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5945097 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4129901 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4129901 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132623 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 132623 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 132076 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 132076 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10074998 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10074998 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10074998 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10074998 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108546 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.108546 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.054283 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.054283 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059032 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059032 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003763 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.003763 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086303 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086303 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086303 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086303 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 36221.215742 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 36221.215742 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41316.814758 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41316.814758 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13135.074722 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13135.074722 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7212.398390 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7212.398390 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37535.011441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37535.011441 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37535.011441 # average overall miss latency +system.cpu0.dcache.tags.tag_accesses 52084143 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 52084143 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6477469 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6477469 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4731394 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4731394 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 141563 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 141563 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149256 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149256 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11208863 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11208863 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11208863 # number of overall hits +system.cpu0.dcache.overall_hits::total 11208863 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 942620 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 942620 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 258040 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 258040 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13696 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13696 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5452 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5452 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1200660 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1200660 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1200660 # number of overall misses +system.cpu0.dcache.overall_misses::total 1200660 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27232981250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 27232981250 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10355566942 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10355566942 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 149859500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 149859500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42011389 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 42011389 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 37588548192 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 37588548192 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 37588548192 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 37588548192 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7420089 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7420089 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4989434 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4989434 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 155259 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 155259 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 154708 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 154708 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12409523 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12409523 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12409523 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12409523 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127036 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127036 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051717 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051717 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088214 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088214 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035241 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035241 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.096753 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.096753 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096753 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.096753 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28890.731419 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 28890.731419 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40131.634406 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40131.634406 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.844334 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.844334 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7705.683969 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7705.683969 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31306.571546 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31306.571546 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 31306.571546 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1243,62 +1258,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 405151 # number of writebacks -system.cpu0.dcache.writebacks::total 405151 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 645318 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 645318 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 224183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 224183 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7829 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 497 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 497 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 869501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 869501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 869501 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 869501 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21958327500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21958327500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8765186517 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8765186517 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 87163500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 87163500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 2590438 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 2590438 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30723514017 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 30723514017 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30723514017 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 30723514017 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1004927000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1004927000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1718158000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1718158000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2723085000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2723085000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108546 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108546 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.054283 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.054283 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059032 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059032 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.003763 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.003763 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086303 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086303 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086303 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 34027.142432 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 34027.142432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39098.354991 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39098.354991 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11133.414229 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11133.414229 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5212.148893 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5212.148893 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35334.650583 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35334.650583 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 686359 # number of writebacks +system.cpu0.dcache.writebacks::total 686359 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942620 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 942620 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 258040 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 258040 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13696 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13696 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5452 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1200660 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1200660 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1200660 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1200660 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25222171750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25222171750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9786377058 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9786377058 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122453500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122453500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31105611 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31105611 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35008548808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 35008548808 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35008548808 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 35008548808 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465625500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465625500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2277904000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2277904000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3743529500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3743529500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127036 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051717 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051717 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088214 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088214 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035241 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035241 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096753 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096753 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096753 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26757.518141 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26757.518141 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37925.814052 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37925.814052 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.822138 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.822138 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5705.357850 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5705.357850 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29157.753909 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29157.753909 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1310,22 +1325,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3617054 # DTB read hits +system.cpu1.dtb.read_hits 2348280 # DTB read hits system.cpu1.dtb.read_misses 2620 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 2433875 # DTB write hits +system.cpu1.dtb.write_hits 1676993 # DTB write hits system.cpu1.dtb.write_misses 235 # DTB write misses system.cpu1.dtb.write_acv 24 # DTB write access violations system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 6050929 # DTB hits +system.cpu1.dtb.data_hits 4025273 # DTB hits system.cpu1.dtb.data_misses 2855 # DTB misses system.cpu1.dtb.data_acv 24 # DTB access violations system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1988100 # ITB hits +system.cpu1.itb.fetch_hits 1801078 # ITB hits system.cpu1.itb.fetch_misses 1064 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1989164 # ITB accesses +system.cpu1.itb.fetch_accesses 1802142 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1338,87 +1353,87 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923841470 # number of cpu cycles simulated +system.cpu1.numCycles 3921880878 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21095754 # Number of instructions committed -system.cpu1.committedOps 21095754 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 19410964 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 175175 # Number of float alu accesses -system.cpu1.num_func_calls 648514 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2286581 # number of instructions that are conditional controls -system.cpu1.num_int_insts 19410964 # number of integer instructions -system.cpu1.num_fp_insts 175175 # number of float instructions -system.cpu1.num_int_register_reads 26520307 # number of times the integer registers were read -system.cpu1.num_int_register_writes 14289908 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 90745 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 92744 # number of times the floating registers were written -system.cpu1.num_mem_refs 6073169 # number of memory refs -system.cpu1.num_load_insts 3630901 # Number of load instructions -system.cpu1.num_store_insts 2442268 # Number of store instructions -system.cpu1.num_idle_cycles 3837673362.965370 # Number of idle cycles -system.cpu1.num_busy_cycles 86168107.034630 # Number of busy cycles -system.cpu1.not_idle_fraction 0.021960 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.978040 # Percentage of idle cycles -system.cpu1.Branches 3165037 # Number of branches fetched -system.cpu1.op_class::No_OpClass 1250062 5.92% 5.92% # Class of executed instruction -system.cpu1.op_class::IntAlu 13186802 62.50% 68.43% # Class of executed instruction -system.cpu1.op_class::IntMult 30198 0.14% 68.57% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.57% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13644 0.06% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.63% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 68.64% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.64% # Class of executed instruction -system.cpu1.op_class::MemRead 3726078 17.66% 86.30% # Class of executed instruction -system.cpu1.op_class::MemWrite 2443288 11.58% 97.88% # Class of executed instruction -system.cpu1.op_class::IprAccess 446802 2.12% 100.00% # Class of executed instruction +system.cpu1.committedInsts 12764610 # Number of instructions committed +system.cpu1.committedOps 12764610 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 11762987 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 170364 # Number of float alu accesses +system.cpu1.num_func_calls 404048 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1265459 # number of instructions that are conditional controls +system.cpu1.num_int_insts 11762987 # number of integer instructions +system.cpu1.num_fp_insts 170364 # number of float instructions +system.cpu1.num_int_register_reads 16177090 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8656212 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 88600 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 90534 # number of times the floating registers were written +system.cpu1.num_mem_refs 4047820 # number of memory refs +system.cpu1.num_load_insts 2361802 # Number of load instructions +system.cpu1.num_store_insts 1686018 # Number of store instructions +system.cpu1.num_idle_cycles 3873240792.459649 # Number of idle cycles +system.cpu1.num_busy_cycles 48640085.540351 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012402 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987598 # Percentage of idle cycles +system.cpu1.Branches 1821460 # Number of branches fetched +system.cpu1.op_class::No_OpClass 690637 5.41% 5.41% # Class of executed instruction +system.cpu1.op_class::IntAlu 7566798 59.27% 64.68% # Class of executed instruction +system.cpu1.op_class::IntMult 21839 0.17% 64.85% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu1.op_class::FloatAdd 13058 0.10% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.95% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1759 0.01% 64.96% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.96% # Class of executed instruction +system.cpu1.op_class::MemRead 2432293 19.05% 84.01% # Class of executed instruction +system.cpu1.op_class::MemWrite 1686990 13.21% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 354115 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21098633 # Class of executed instruction +system.cpu1.op_class::total 12767489 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3863 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 100733 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 37218 40.29% 40.29% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 2.13% 42.42% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 86 0.09% 42.51% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 53108 57.49% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 92382 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 36366 48.68% 48.68% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 2.64% 51.32% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 86 0.12% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 36280 48.57% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 74702 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1906657223000 97.18% 97.18% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 706239500 0.04% 97.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 59367000 0.00% 97.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 54497875500 2.78% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961920705000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.977108 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 77083 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26133 38.19% 38.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1969 2.88% 41.07% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 506 0.74% 41.81% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 39822 58.19% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 68430 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25289 48.13% 48.13% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1969 3.75% 51.87% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 506 0.96% 52.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 24783 47.16% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 52547 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909614154000 97.38% 97.38% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 700846000 0.04% 97.42% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 353816000 0.02% 97.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 50271593000 2.56% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1960940409000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.967704 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.683136 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.808621 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.622344 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.767894 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed @@ -1434,87 +1449,87 @@ system.cpu1.kern.syscall::74 9 9.78% 96.74% # nu system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 92 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.02% # number of callpals executed -system.cpu1.kern.callpal::swpctx 2020 2.13% 2.15% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 2.16% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.16% # number of callpals executed -system.cpu1.kern.callpal::swpipl 87059 91.90% 94.06% # number of callpals executed -system.cpu1.kern.callpal::rdps 2187 2.31% 96.37% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 96.37% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 96.38% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 96.38% # number of callpals executed -system.cpu1.kern.callpal::rti 3266 3.45% 99.83% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.13% 99.95% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.04% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 424 0.60% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1955 2.77% 3.37% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.38% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.39% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62269 88.12% 91.51% # number of callpals executed +system.cpu1.kern.callpal::rdps 2146 3.04% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.54% # number of callpals executed +system.cpu1.kern.callpal::wrusp 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.55% # number of callpals executed +system.cpu1.kern.callpal::rti 3685 5.21% 99.77% # number of callpals executed +system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 94732 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 2415 # number of protection mode switches +system.cpu1.kern.callpal::total 70663 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1918 # number of protection mode switches system.cpu1.kern.mode_switch::user 367 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2037 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 415 +system.cpu1.kern.mode_switch::idle 2888 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 797 system.cpu1.kern.mode_good::user 367 -system.cpu1.kern.mode_good::idle 48 -system.cpu1.kern.mode_switch_good::kernel 0.171843 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 430 +system.cpu1.kern.mode_switch_good::kernel 0.415537 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.023564 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.172235 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 65779284000 3.35% 3.35% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1486343500 0.08% 3.43% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893759051500 96.57% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 2021 # number of times the context was actually changed -system.cpu1.icache.tags.replacements 463035 # number of replacements -system.cpu1.icache.tags.tagsinuse 500.061178 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 20635046 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 463547 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 44.515542 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 97712638250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 500.061178 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.976682 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.976682 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21562220 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21562220 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 20635046 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 20635046 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 20635046 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 20635046 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 20635046 # number of overall hits -system.cpu1.icache.overall_hits::total 20635046 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 463587 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 463587 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 463587 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 463587 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 463587 # number of overall misses -system.cpu1.icache.overall_misses::total 463587 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6202855739 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6202855739 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6202855739 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6202855739 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6202855739 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6202855739 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 21098633 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 21098633 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 21098633 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 21098633 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 21098633 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 21098633 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.021972 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.021972 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.021972 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.021972 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.021972 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.021972 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13380.133047 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13380.133047 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13380.133047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13380.133047 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13380.133047 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148892 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.308138 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17565031500 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1483893000 0.08% 0.97% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1941003590000 99.03% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1956 # number of times the context was actually changed +system.cpu1.icache.tags.replacements 311453 # number of replacements +system.cpu1.icache.tags.tagsinuse 446.345950 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12455485 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 311964 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.926033 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1960014862500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.345950 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.871769 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.871769 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 71 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 440 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 13079493 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13079493 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12455485 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12455485 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12455485 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12455485 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12455485 # number of overall hits +system.cpu1.icache.overall_hits::total 12455485 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 312004 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 312004 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 312004 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 312004 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 312004 # number of overall misses +system.cpu1.icache.overall_misses::total 312004 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4105450991 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4105450991 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4105450991 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4105450991 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4105450991 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4105450991 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 12767489 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 12767489 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 12767489 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 12767489 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 12767489 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 12767489 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024437 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024437 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024437 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024437 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024437 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024437 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13158.328070 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13158.328070 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13158.328070 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13158.328070 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13158.328070 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1523,118 +1538,118 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 463587 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 463587 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 463587 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 463587 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 463587 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 463587 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5274833261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5274833261 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5274833261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5274833261 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5274833261 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5274833261 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021972 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021972 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021972 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021972 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11378.302802 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11378.302802 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11378.302802 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 312004 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 312004 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 312004 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 312004 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 312004 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 312004 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3481247009 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3481247009 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3481247009 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3481247009 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3481247009 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3481247009 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024437 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024437 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024437 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024437 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11157.699930 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11157.699930 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11157.699930 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 581700 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.027042 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5462019 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 582040 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 9.384267 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 61159690250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.027042 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.960990 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.960990 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 340 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 298 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.664062 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 24828314 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 24828314 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3080149 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3080149 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2259986 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2259986 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 60927 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 60927 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71555 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71555 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5340135 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5340135 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5340135 # number of overall hits -system.cpu1.dcache.overall_hits::total 5340135 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 473178 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 473178 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 102501 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 102501 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11671 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11671 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 568 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 568 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 575679 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 575679 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 575679 # number of overall misses -system.cpu1.dcache.overall_misses::total 575679 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5938208750 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5938208750 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2338814234 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2338814234 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 149892750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 149892750 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4181580 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4181580 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8277022984 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8277022984 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8277022984 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8277022984 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3553327 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3553327 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2362487 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2362487 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 72598 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 72598 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 72123 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 72123 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 5915814 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 5915814 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 5915814 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 5915814 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.133165 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.133165 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043387 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043387 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.160762 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.160762 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007875 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.007875 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097312 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.097312 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097312 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.097312 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12549.629843 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12549.629843 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22817.477234 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22817.477234 # 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Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 155503 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.790879 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1048852145500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.308424 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949821 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949821 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16322131 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16322131 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2189503 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2189503 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1567525 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1567525 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 46972 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 46972 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 49481 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 49481 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3757028 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3757028 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3757028 # number of overall hits +system.cpu1.dcache.overall_hits::total 3757028 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 113756 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 113756 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 55958 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 55958 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8862 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8862 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5884 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5884 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 169714 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 169714 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 169714 # number of overall misses +system.cpu1.dcache.overall_misses::total 169714 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1372027750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1372027750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1020320505 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1020320505 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80442000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 80442000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43305909 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 43305909 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2392348255 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2392348255 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2392348255 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2392348255 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2303259 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2303259 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1623483 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1623483 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 55834 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 55834 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 55365 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 55365 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 3926742 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 3926742 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3926742 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3926742 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049389 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049389 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034468 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.034468 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158720 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158720 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106277 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106277 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043220 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043220 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.043220 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.146225 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.146225 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18233.684281 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18233.684281 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9077.183480 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9077.183480 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7359.943746 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7359.943746 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14096.351833 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14096.351833 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14096.351833 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1643,62 +1658,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 444927 # number of writebacks -system.cpu1.dcache.writebacks::total 444927 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 473178 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 473178 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 102501 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 102501 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11671 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 568 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 568 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 575679 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 575679 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 575679 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 575679 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4991497250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4991497250 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2127317766 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2127317766 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 126550250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 126550250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3045420 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3045420 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7118815016 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7118815016 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7118815016 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7118815016 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 479658500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 479658500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 907862000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 907862000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1387520500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1387520500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.133165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.133165 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.043387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.043387 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.160762 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.160762 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007875 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.007875 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.097312 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097312 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.097312 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10548.878540 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10548.878540 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 20754.117189 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 20754.117189 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10843.136835 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10843.136835 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.654930 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.654930 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12365.945285 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12365.945285 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 106457 # number of writebacks +system.cpu1.dcache.writebacks::total 106457 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 113756 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 113756 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 55958 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 55958 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8862 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8862 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5884 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5884 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 169714 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 169714 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 169714 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 169714 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1144439250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1144439250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 906162495 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 906162495 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62718000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62718000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31536091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31536091 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2050601745 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2050601745 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2050601745 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2050601745 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18765500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18765500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 713325000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 713325000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 732090500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 732090500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049389 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049389 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034468 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034468 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.158720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.158720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106277 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106277 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.043220 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043220 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.043220 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10060.473733 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10060.473733 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16193.618339 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16193.618339 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7077.183480 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7077.183480 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5359.634772 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5359.634772 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12082.690556 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12082.690556 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 7916cb036..a960683a9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.919439 # Number of seconds simulated -sim_ticks 1919438772000 # Number of ticks simulated -final_tick 1919438772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1919439025000 # Number of ticks simulated +final_tick 1919439025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1398299 # Simulator instruction rate (inst/s) -host_op_rate 1398299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47840414078 # Simulator tick rate (ticks/s) -host_mem_usage 314348 # Number of bytes of host memory used -host_seconds 40.12 # Real time elapsed on the host -sim_insts 56102112 # Number of instructions simulated -sim_ops 56102112 # Number of ops (including micro ops) simulated +host_inst_rate 1426339 # Simulator instruction rate (inst/s) +host_op_rate 1426339 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48799693433 # Simulator tick rate (ticks/s) +host_mem_usage 367228 # Number of bytes of host memory used +host_seconds 39.33 # Real time elapsed on the host +sim_insts 56102180 # Number of instructions simulated +sim_ops 56102180 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 850816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24875968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24875904 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25727744 # Number of bytes read from this memory +system.physmem.bytes_read::total 25727680 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 850816 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 850816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4747712 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 4747520 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7407040 # Number of bytes written to this memory +system.physmem.bytes_written::total 7406848 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 13294 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388687 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388686 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401996 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 74183 # Number of write requests responded to by this memory +system.physmem.num_reads::total 401995 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74180 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115735 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115732 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 443263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12960022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12959987 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13403785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13403750 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 443263 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 443263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2473490 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1385472 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3858961 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2473490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 2473389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1385471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3858861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2473389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 443263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12960022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12959987 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1385972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17262746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401996 # Number of read requests accepted -system.physmem.writeReqs 115735 # Number of write requests accepted -system.physmem.readBursts 401996 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 115735 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25716224 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11520 # Total number of bytes read from write queue -system.physmem.bytesWritten 7405312 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25727744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7407040 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 180 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17262610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401995 # Number of read requests accepted +system.physmem.writeReqs 115732 # Number of write requests accepted +system.physmem.readBursts 401995 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 115732 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25715968 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11712 # Total number of bytes read from write queue +system.physmem.bytesWritten 7405120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25727680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7406848 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 183 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 132 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 25161 # Per bank write bursts -system.physmem.perBankRdBursts::1 25541 # Per bank write bursts +system.physmem.perBankRdBursts::1 25539 # Per bank write bursts system.physmem.perBankRdBursts::2 25618 # Per bank write bursts -system.physmem.perBankRdBursts::3 25537 # Per bank write bursts -system.physmem.perBankRdBursts::4 24981 # Per bank write bursts -system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::3 25536 # Per bank write bursts +system.physmem.perBankRdBursts::4 24982 # Per bank write bursts +system.physmem.perBankRdBursts::5 24977 # Per bank write bursts system.physmem.perBankRdBursts::6 24228 # Per bank write bursts system.physmem.perBankRdBursts::7 24506 # Per bank write bursts -system.physmem.perBankRdBursts::8 25159 # Per bank write bursts -system.physmem.perBankRdBursts::9 24820 # Per bank write bursts +system.physmem.perBankRdBursts::8 25158 # Per bank write bursts +system.physmem.perBankRdBursts::9 24823 # Per bank write bursts system.physmem.perBankRdBursts::10 25363 # Per bank write bursts -system.physmem.perBankRdBursts::11 24840 # Per bank write bursts -system.physmem.perBankRdBursts::12 24420 # Per bank write bursts +system.physmem.perBankRdBursts::11 24839 # Per bank write bursts +system.physmem.perBankRdBursts::12 24418 # Per bank write bursts system.physmem.perBankRdBursts::13 25388 # Per bank write bursts system.physmem.perBankRdBursts::14 25795 # Per bank write bursts -system.physmem.perBankRdBursts::15 25483 # Per bank write bursts +system.physmem.perBankRdBursts::15 25481 # Per bank write bursts system.physmem.perBankWrBursts::0 7550 # Per bank write bursts system.physmem.perBankWrBursts::1 7529 # Per bank write bursts system.physmem.perBankWrBursts::2 7880 # Per bank write bursts @@ -78,9 +78,9 @@ system.physmem.perBankWrBursts::3 7553 # Pe system.physmem.perBankWrBursts::4 7115 # Per bank write bursts system.physmem.perBankWrBursts::5 6983 # Per bank write bursts system.physmem.perBankWrBursts::6 6321 # Per bank write bursts -system.physmem.perBankWrBursts::7 6319 # Per bank write bursts +system.physmem.perBankWrBursts::7 6315 # Per bank write bursts system.physmem.perBankWrBursts::8 7293 # Per bank write bursts -system.physmem.perBankWrBursts::9 6554 # Per bank write bursts +system.physmem.perBankWrBursts::9 6555 # Per bank write bursts system.physmem.perBankWrBursts::10 7205 # Per bank write bursts system.physmem.perBankWrBursts::11 6861 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts @@ -88,23 +88,23 @@ system.physmem.perBankWrBursts::13 7821 # Pe system.physmem.perBankWrBursts::14 7980 # Per bank write bursts system.physmem.perBankWrBursts::15 7780 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 1919426851000 # Total gap between requests +system.physmem.numWrRetry 12 # Number of times write queue was full causing retry +system.physmem.totGap 1919427104000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401996 # Read request sizes (log2) +system.physmem.readPktSize::6 401995 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 115735 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401802 # What read queue length does an incoming req see +system.physmem.writePktSize::6 115732 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401798 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -151,124 +151,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6976 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8460 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6824 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6566 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6884 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 160 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 198 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63869 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 518.585480 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 313.979775 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 413.923527 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14875 23.29% 23.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11515 18.03% 41.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4721 7.39% 48.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3142 4.92% 53.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3018 4.73% 58.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1863 2.92% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1301 2.04% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1404 2.20% 65.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22030 34.49% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63869 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5101 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 78.768477 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2955.016496 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5098 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::44 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63991 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 517.589786 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 312.394273 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 414.375602 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15074 23.56% 23.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11584 18.10% 41.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4587 7.17% 48.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3091 4.83% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3045 4.76% 58.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1807 2.82% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1323 2.07% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1474 2.30% 65.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22006 34.39% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63991 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5109 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.644353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2952.702952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5106 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5101 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5101 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.683395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.235797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.276820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4452 87.28% 87.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 22 0.43% 87.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.29% 88.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 224 4.39% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 41 0.80% 93.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 6 0.12% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.18% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.14% 93.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.37% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.04% 94.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.08% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 11 0.22% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.06% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 7 0.14% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 30 0.59% 95.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 13 0.25% 95.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.06% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 166 3.25% 98.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 10 0.20% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.12% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.08% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 6 0.12% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.18% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.18% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.06% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.04% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.06% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.08% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5101 # Writes before turning the bus around for reads -system.physmem.totQLat 2117396500 # Total ticks spent queuing -system.physmem.totMemAccLat 9651446500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2009080000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5269.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5109 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5109 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.647289 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.199358 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.195525 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4460 87.30% 87.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 21 0.41% 87.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 12 0.23% 87.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 224 4.38% 92.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 41 0.80% 93.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.39% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 7 0.14% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.12% 93.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 14 0.27% 94.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.08% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.06% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 9 0.18% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.10% 94.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.08% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 25 0.49% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 9 0.18% 95.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 15 0.29% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 168 3.29% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.04% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.02% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.04% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.16% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.10% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 5 0.10% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 9 0.18% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 13 0.25% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.02% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.10% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5109 # Writes before turning the bus around for reads +system.physmem.totQLat 2129492750 # Total ticks spent queuing +system.physmem.totMemAccLat 9663467750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2009060000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5299.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24019.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24049.72 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.40 # Average system read bandwidth in MiByte/s @@ -278,100 +277,113 @@ system.physmem.busUtil 0.13 # Da system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing -system.physmem.readRowHits 360116 # Number of row buffer hits during reads -system.physmem.writeRowHits 93539 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.62 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing +system.physmem.readRowHits 359991 # Number of row buffer hits during reads +system.physmem.writeRowHits 93535 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads system.physmem.writeRowHitRate 80.82 # Row buffer hit rate for writes -system.physmem.avgGap 3707382.50 # Average gap between requests -system.physmem.pageHitRate 87.65 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1800046548500 # Time in different power states +system.physmem.avgGap 3707411.64 # Average gap between requests +system.physmem.pageHitRate 87.63 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1800186005000 # Time in different power states system.physmem.memoryStateTime::REF 64094160000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 55294756500 # Time in different power states +system.physmem.memoryStateTime::ACT 55155300000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17291227 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 292357 # Transaction distribution system.membus.trans_dist::ReadResp 292357 # Transaction distribution system.membus.trans_dist::WriteReq 9649 # Transaction distribution system.membus.trans_dist::WriteResp 9649 # Transaction distribution -system.membus.trans_dist::Writeback 74183 # Transaction distribution +system.membus.trans_dist::Writeback 74180 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116727 # Transaction distribution -system.membus.trans_dist::ReadExResp 116727 # Transaction distribution +system.membus.trans_dist::ReadExReq 116726 # Transaction distribution +system.membus.trans_dist::ReadExResp 116726 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33158 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878409 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911567 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878404 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911562 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 994859 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474496 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30519052 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33179340 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33179340 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 32375500 # Layer occupancy (ticks) +system.membus.pkt_count::total 994854 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44556 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30474240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30518796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33179084 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 158 # Total snoops (count) +system.membus.snoop_fanout::samples 518029 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 518029 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 518029 # Request fanout histogram +system.membus.reqLayer0.occupancy 30371000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1450892000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1451093000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751806368 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3752017868 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43113000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43114250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.344805 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.344808 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753524887000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.344805 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084050 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084050 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1753524972000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.344808 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.084051 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.084051 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375525 # Number of tag accesses -system.iocache.tags.data_accesses 375525 # Number of data accesses +system.iocache.tags.tag_accesses 375557 # Number of tag accesses +system.iocache.tags.data_accesses 375557 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 4 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 4 # number of WriteInvalidateReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 24523133 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 24523133 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 24523133 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 24523133 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 24523133 # number of overall miss cycles +system.iocache.overall_miss_latency::total 24523133 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41556 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41556 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000096 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000096 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 141752.213873 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 141752.213873 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 141752.213873 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 141752.213873 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 141752.213873 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,30 +400,30 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2506570306 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2506570306 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 15526633 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15526633 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512178304 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512178304 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 15526633 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15526633 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 15526633 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15526633 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999904 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999904 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60323.698161 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60323.698161 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 89749.323699 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60458.661533 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60458.661533 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 89749.323699 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 89749.323699 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -430,22 +442,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052614 # DTB read hits -system.cpu.dtb.read_misses 10356 # DTB read misses +system.cpu.dtb.read_hits 9052455 # DTB read hits +system.cpu.dtb.read_misses 10357 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728915 # DTB read accesses -system.cpu.dtb.write_hits 6349217 # DTB write hits -system.cpu.dtb.write_misses 1144 # DTB write misses +system.cpu.dtb.read_accesses 728916 # DTB read accesses +system.cpu.dtb.write_hits 6349129 # DTB write hits +system.cpu.dtb.write_misses 1143 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291933 # DTB write accesses -system.cpu.dtb.data_hits 15401831 # DTB hits +system.cpu.dtb.write_accesses 291932 # DTB write accesses +system.cpu.dtb.data_hits 15401584 # DTB hits system.cpu.dtb.data_misses 11500 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations system.cpu.dtb.data_accesses 1020848 # DTB accesses -system.cpu.itb.fetch_hits 4974960 # ITB hits +system.cpu.itb.fetch_hits 4974880 # ITB hits system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4979970 # ITB accesses +system.cpu.itb.fetch_accesses 4979890 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -458,34 +470,34 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3838877544 # number of cpu cycles simulated +system.cpu.numCycles 3838878050 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102112 # Number of instructions committed -system.cpu.committedOps 56102112 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51977185 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses -system.cpu.num_func_calls 1481236 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6460933 # number of instructions that are conditional controls -system.cpu.num_int_insts 51977185 # number of integer instructions -system.cpu.num_fp_insts 324460 # number of float instructions -system.cpu.num_int_register_reads 71206533 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459103 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written -system.cpu.num_mem_refs 15454487 # number of memory refs -system.cpu.num_load_insts 9089505 # Number of load instructions -system.cpu.num_store_insts 6364982 # Number of store instructions -system.cpu.num_idle_cycles 3587234430.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251643113.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065551 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934449 # Percentage of idle cycles -system.cpu.Branches 8412678 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197715 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36172357 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 61004 0.11% 70.27% # Class of executed instruction +system.cpu.committedInsts 56102180 # Number of instructions committed +system.cpu.committedOps 56102180 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 51977296 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324326 # Number of float alu accesses +system.cpu.num_func_calls 1481232 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6461044 # number of instructions that are conditional controls +system.cpu.num_int_insts 51977296 # number of integer instructions +system.cpu.num_fp_insts 324326 # number of float instructions +system.cpu.num_int_register_reads 71206831 # number of times the integer registers were read +system.cpu.num_int_register_writes 38459262 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163576 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166452 # number of times the floating registers were written +system.cpu.num_mem_refs 15454224 # number of memory refs +system.cpu.num_load_insts 9089337 # Number of load instructions +system.cpu.num_store_insts 6364887 # Number of store instructions +system.cpu.num_idle_cycles 3587231475.998131 # Number of idle cycles +system.cpu.num_busy_cycles 251646574.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065552 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934448 # Percentage of idle cycles +system.cpu.Branches 8412776 # Number of branches fetched +system.cpu.op_class::No_OpClass 3197684 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36172751 64.46% 70.16% # Class of executed instruction +system.cpu.op_class::IntMult 60997 0.11% 70.27% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38087 0.07% 70.34% # Class of executed instruction +system.cpu.op_class::FloatAdd 38083 0.07% 70.34% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction @@ -511,14 +523,14 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316582 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371054 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953544 1.70% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 9316413 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6370959 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953524 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56113979 # Class of executed instruction +system.cpu.op_class::total 56114047 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6378 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212019 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6380 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 212017 # number of hwrei instructions executed system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1931 1.05% 42.01% # number of times we switched to this ipl @@ -529,11 +541,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1931 1.29% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149118 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857248521000 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91287500 0.00% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737179000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61361050500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1919438038000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1857251860000 96.76% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91366000 0.00% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 736784000 0.04% 96.80% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 61358281000 3.20% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1919438291000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -574,8 +586,8 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed +system.cpu.kern.callpal::swpctx 4175 2.16% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed system.cpu.kern.callpal::swpipl 175949 91.22% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6832 3.54% 96.96% # number of callpals executed @@ -586,21 +598,21 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5156 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192894 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5902 # number of protection mode switches +system.cpu.kern.callpal::total 192892 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5903 # number of protection mode switches system.cpu.kern.mode_switch::user 1742 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1912 +system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 system.cpu.kern.mode_good::user 1742 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.323958 # fraction of useful protection mode switches +system.cpu.kern.mode_good::idle 169 +system.cpu.kern.mode_switch_good::kernel 0.323734 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392567 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46116573000 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5192895500 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1868128567500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_switch_good::idle 0.080707 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392443 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46142250000 2.40% 2.40% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5192719000 0.27% 2.67% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1868103320000 97.33% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4176 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -632,11 +644,11 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1409873 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51201 # Transaction distribution +system.iobus.trans_dist::WriteReq 51197 # Transaction distribution system.iobus.trans_dist::WriteResp 51201 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 4 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -653,23 +665,22 @@ system.iobus.pkt_count_system.bridge.master::total 33158 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116608 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2706164 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44556 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2706164 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) @@ -692,21 +703,21 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374412187 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23509000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42014000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42016750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 927724 # number of replacements -system.cpu.icache.tags.tagsinuse 508.304001 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55185585 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928235 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.452170 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39855277250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.304001 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 927651 # number of replacements +system.cpu.icache.tags.tagsinuse 508.304035 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55185726 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928162 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.456998 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.304035 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.992781 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id @@ -715,44 +726,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 1 system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57042375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57042375 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55185585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55185585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55185585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55185585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55185585 # number of overall hits -system.cpu.icache.overall_hits::total 55185585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928395 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928395 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928395 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928395 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928395 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13910.293033 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13910.293033 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13910.293033 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57042370 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57042370 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55185726 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55185726 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55185726 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55185726 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55185726 # number of overall hits +system.cpu.icache.overall_hits::total 55185726 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928322 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928322 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928322 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928322 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928322 # number of overall misses +system.cpu.icache.overall_misses::total 928322 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909129000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12909129000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12909129000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12909129000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12909129000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12909129000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56114048 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56114048 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13905.874255 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13905.874255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13905.874255 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13905.874255 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -761,135 +772,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # 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number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11052282500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016545 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016545 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016545 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016545 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.719974 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.719974 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.719974 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11047351000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11047351000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11047351000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11047351000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016543 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016543 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016543 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.343846 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.343846 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.343846 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.343846 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336239 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65296.333666 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2445823 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401400 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.093231 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 336238 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65296.035696 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2445623 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401399 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.092748 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55553.405547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.094279 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.833840 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847678 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 55554.100042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4767.074149 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4974.861505 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.847688 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072740 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996343 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.075910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996338 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65161 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3266 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55772 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3263 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55775 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994278 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25933937 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25933937 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 915081 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814447 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729528 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834526 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834526 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 25932255 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25932255 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 915008 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 814389 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1729397 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 834448 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 834448 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 187344 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 187344 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915081 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001791 # 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number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1086349 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2014651 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 834448 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 834448 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304190 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304190 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928375 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390597 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318972 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928375 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390597 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318972 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014320 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250330 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141581 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304189 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928302 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1390538 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2318840 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928302 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1390538 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2318840 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014321 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250343 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141590 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384122 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384122 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014320 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279596 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173396 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014320 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279596 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173396 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73195.238453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65072.018863 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65450.594032 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384120 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.384120 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014321 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279608 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173405 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014321 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279608 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173405 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72884.684820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65060.810413 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 65425.434876 # average ReadReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7192 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7192 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69040.824085 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 66515.840330 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72884.684820 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66298.077136 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 66515.840330 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -898,66 +909,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74183 # number of writebacks -system.cpu.l2cache.writebacks::total 74183 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 74180 # number of writebacks +system.cpu.l2cache.writebacks::total 74180 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13294 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271960 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 285254 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116846 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116846 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116845 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116845 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 13294 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20916027619 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21718395619 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334183000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334183000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893390000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893390000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227573000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227573000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250343 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384122 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173396 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014320 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279596 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173396 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60666.917406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52570.305376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52947.640524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384120 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173405 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014321 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279608 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173405 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60355.649165 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52559.008678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52922.363928 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56538.425526 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56538.425526 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60666.917406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53762.825468 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53991.084603 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56674.052112 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56674.052112 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60355.649165 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53795.675516 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54012.558149 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -965,11 +976,11 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1390084 # number of replacements +system.cpu.dcache.tags.replacements 1390025 # number of replacements system.cpu.dcache.tags.tagsinuse 511.978881 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030288 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390596 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.089406 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 14030084 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1390537 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.089688 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.978881 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy @@ -979,72 +990,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63074137 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63074137 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802568 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802568 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845442 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845442 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183034 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183034 # 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number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15021410 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021410 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021410 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120516 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120516 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049467 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085963 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085963 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091429 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091429 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091429 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091429 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27121.578377 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27121.578377 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35851.398495 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35851.398495 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13255.141164 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13255.141164 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29055.226541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29055.226541 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29055.226541 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63073026 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63073026 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7802461 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7802461 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5845351 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5845351 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183030 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 183030 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13647812 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13647812 # 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number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 28994287250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922192632 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10922192632 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228270750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 228270750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39916479882 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39916479882 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39916479882 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39916479882 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8871595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8871595 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6149557 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6149557 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200245 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15021152 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15021152 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15021152 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15021152 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120512 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120512 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085970 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085970 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091427 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091427 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091427 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091427 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27119.413703 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27119.413703 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35903.935596 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35903.935596 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13259.991287 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13259.991287 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 29065.256879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 29065.256879 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29065.256879 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1053,54 +1064,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834526 # number of writebacks -system.cpu.dcache.writebacks::total 834526 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069193 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069193 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304207 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304207 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17214 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373400 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373400 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373400 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373400 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26734131250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26734131250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245126618 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245126618 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36979257868 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36979257868 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36979257868 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36979257868 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011219500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435455500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435455500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120516 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120516 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085963 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085963 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091429 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091429 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091429 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25004.027570 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25004.027570 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33678.142245 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33678.142245 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11254.327873 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11254.327873 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26925.337023 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26925.337023 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 834448 # number of writebacks +system.cpu.dcache.writebacks::total 834448 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069134 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069134 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304206 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304206 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17215 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17215 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373340 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373340 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373340 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373340 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26730348750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26730348750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10261067368 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10261067368 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193828250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193828250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36991416118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 36991416118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36991416118 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 36991416118 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424273000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424273000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009178000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009178000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433451000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433451000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120512 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049468 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049468 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085970 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085970 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091427 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091427 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091427 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25001.869504 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25001.869504 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33730.654123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33730.654123 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11259.265176 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11259.265176 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26935.366419 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26935.366419 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1108,32 +1119,41 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 106562255 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2021905 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2021774 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2021757 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9649 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9649 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834526 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 834448 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41564 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304190 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304190 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856770 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3649068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505838 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59416000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142462412 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 201878412 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 201868428 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2671296 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2424407500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 304189 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304189 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856624 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648872 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5505496 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59411328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142453644 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 201864972 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41913 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3195062 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013063 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113544 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3153325 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41737 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3195062 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2424224500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395179500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395050000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186860632 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2186768132 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index df149be6e..2e680c93e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,69 +1,18 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.900855 # Number of seconds simulated -sim_ticks 900854787500 # Number of ticks simulated -final_tick 900854787500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.900830 # Number of seconds simulated +sim_ticks 900829868000 # Number of ticks simulated +final_tick 900829868000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 875862 # Simulator instruction rate (inst/s) -host_op_rate 1055198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12821864647 # Simulator tick rate (ticks/s) -host_mem_usage 433912 # Number of bytes of host memory used -host_seconds 70.26 # Real time elapsed on the host -sim_insts 61537412 # Number of instructions simulated -sim_ops 74137396 # Number of ops (including micro ops) simulated +host_inst_rate 1355321 # Simulator instruction rate (inst/s) +host_op_rate 1632835 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19839612971 # Simulator tick rate (ticks/s) +host_mem_usage 467260 # Number of bytes of host memory used +host_seconds 45.41 # Real time elapsed on the host +sim_insts 61539136 # Number of instructions simulated +sim_ops 74139862 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 460108 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6580092 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 258564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2992120 # Number of bytes read from this memory -system.physmem.bytes_read::total 49612932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 460108 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 258564 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 718672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4174784 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7201872 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13417 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 102873 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 46770 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082398 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65231 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822003 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43649210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 284 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 213 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 510746 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7304276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 287021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3321423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 55073173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 510746 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 287021 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 797767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4634247 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 3360195 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7994487 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4634247 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43649210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 284 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 213 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 510746 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10664471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 287021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3321468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 63067661 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -82,180 +31,270 @@ system.realview.nvmem.bw_inst_read::total 75 # I system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 65740815 # Throughput (bytes/s) -system.membus.data_through_bus 59222928 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 468620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6508860 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 266564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2938616 # Number of bytes read from this memory +system.physmem.bytes_read::total 49504452 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 468620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 266564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 735184 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3365568 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 3027048 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 6392656 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 101760 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 45934 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5080703 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 52587 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 756762 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 809359 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43650418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 71 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 520209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7225404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 295909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3262121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54954275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 520209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 295909 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 816119 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3736075 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 3360288 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 44 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7096408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3736075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43650418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 71 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 520209 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10585693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 295909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3262165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62050682 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 6129610 # Transaction distribution +system.membus.trans_dist::ReadResp 6129610 # Transaction distribution +system.membus.trans_dist::WriteReq 767040 # Transaction distribution +system.membus.trans_dist::WriteResp 767040 # Transaction distribution +system.membus.trans_dist::Writeback 52587 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37380 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 20039 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14449 # Transaction distribution +system.membus.trans_dist::ReadExReq 163617 # Transaction distribution +system.membus.trans_dist::ReadExResp 136674 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382414 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 8564 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 682 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1995948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4387646 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 9830400 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 9830400 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14218046 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2389580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 17128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1364 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16575508 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18983656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 39321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 39321600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 58305256 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 295628 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 295628 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 295628 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 70256 # number of replacements -system.l2c.tags.tagsinuse 51491.506872 # Cycle average of tags in use -system.l2c.tags.total_refs 1633923 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 135467 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.061410 # Average number of references to valid blocks. +system.l2c.tags.replacements 60014 # number of replacements +system.l2c.tags.tagsinuse 50124.590156 # Cycle average of tags in use +system.l2c.tags.total_refs 136044 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 120331 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.130581 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39155.338647 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.673377 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4830.605577 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5154.208952 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1696.649192 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 652.030072 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.597463 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000041 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073709 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.078647 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.025889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009949 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.785698 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65207 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3953 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 12685 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 48286 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994980 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 16963603 # Number of tag accesses -system.l2c.tags.data_accesses 16963603 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4298 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1596 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 413244 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 202837 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4578 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1943 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 438543 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 146503 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1213542 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 34 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 19288 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 47383 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 68 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 43 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 22698 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 13285 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 102859 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 175673 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 175673 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6079 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 6659 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 12738 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 793 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1507 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 100168 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 50523 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 150691 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 60 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 34 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 19288 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 147551 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 68 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 43 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 22698 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 63808 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 253550 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 60 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 34 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 19288 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 147551 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 68 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 43 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 22698 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 63808 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 253550 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.058824 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.358098 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.199607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.183232 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.111253 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.213934 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.963645 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.973870 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.968990 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.971989 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.974779 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.973457 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.926803 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.880332 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.911222 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.058824 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.358098 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.693279 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.183232 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.720207 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.628349 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.016667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.058824 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.358098 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.693279 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.183232 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.720207 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.628349 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -264,8 +303,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65231 # number of writebacks -system.l2c.writebacks::total 65231 # number of writebacks +system.l2c.writebacks::writebacks 52587 # number of writebacks +system.l2c.writebacks::total 52587 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -273,11 +312,92 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 156214740 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 140726796 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 46301771 # Throughput (bytes/s) -system.iobus.data_through_bus 41711172 # Total data (bytes) +system.toL2Bus.trans_dist::ReadReq 1357667 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1357667 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767040 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767040 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 175673 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 37136 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 20079 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 57215 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 177634 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 177634 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2263595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2631190 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4894785 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 23563666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15087382 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38651048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 575784 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 575784 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 575784 # Request fanout histogram +system.iobus.trans_dist::ReadReq 6098452 # Transaction distribution +system.iobus.trans_dist::ReadResp 6098452 # Transaction distribution +system.iobus.trans_dist::WriteReq 7955 # Transaction distribution +system.iobus.trans_dist::WriteResp 7955 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7906 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 488 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382414 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 9830400 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 9830400 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 12212814 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40294 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 268 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2389580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 39321600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 39321600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 41711180 # Cumulative packet size per connected master and slave (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -301,9 +421,9 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7391669 # DTB read hits -system.cpu0.dtb.read_misses 1915 # DTB read misses -system.cpu0.dtb.write_hits 6659638 # DTB write hits +system.cpu0.dtb.read_hits 7391828 # DTB read hits +system.cpu0.dtb.read_misses 1916 # DTB read misses +system.cpu0.dtb.write_hits 6659769 # DTB write hits system.cpu0.dtb.write_misses 1130 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -314,12 +434,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 84 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7393584 # DTB read accesses -system.cpu0.dtb.write_accesses 6660768 # DTB write accesses +system.cpu0.dtb.read_accesses 7393744 # DTB read accesses +system.cpu0.dtb.write_accesses 6660899 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051307 # DTB hits -system.cpu0.dtb.misses 3045 # DTB misses -system.cpu0.dtb.accesses 14054352 # DTB accesses +system.cpu0.dtb.hits 14051597 # DTB hits +system.cpu0.dtb.misses 3046 # DTB misses +system.cpu0.dtb.accesses 14054643 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -341,7 +461,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 37936012 # ITB inst hits +system.cpu0.itb.inst_hits 37936653 # ITB inst hits system.cpu0.itb.inst_misses 1207 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -358,37 +478,37 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37937219 # ITB inst accesses -system.cpu0.itb.hits 37936012 # DTB hits +system.cpu0.itb.inst_accesses 37937860 # ITB inst accesses +system.cpu0.itb.hits 37936653 # DTB hits system.cpu0.itb.misses 1207 # DTB misses -system.cpu0.itb.accesses 37937219 # DTB accesses -system.cpu0.numCycles 1801227301 # number of cpu cycles simulated +system.cpu0.itb.accesses 37937860 # DTB accesses +system.cpu0.numCycles 1801220958 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 37698803 # Number of instructions committed -system.cpu0.committedOps 44946380 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39863943 # Number of integer alu accesses +system.cpu0.committedInsts 37699441 # Number of instructions committed +system.cpu0.committedOps 44947195 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 39864660 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4171 # Number of float alu accesses -system.cpu0.num_func_calls 1205467 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4697957 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39863943 # number of integer instructions +system.cpu0.num_func_calls 1205511 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4698026 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39864660 # number of integer instructions system.cpu0.num_fp_insts 4171 # number of float instructions -system.cpu0.num_int_register_reads 70363299 # number of times the integer registers were read -system.cpu0.num_int_register_writes 26108579 # number of times the integer registers were written +system.cpu0.num_int_register_reads 70364659 # number of times the integer registers were read +system.cpu0.num_int_register_writes 26109079 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3915 # number of times the floating registers were read system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 134797325 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 18388517 # number of times the CC registers were written -system.cpu0.num_mem_refs 14597479 # number of memory refs -system.cpu0.num_load_insts 7571296 # Number of load instructions -system.cpu0.num_store_insts 7026183 # Number of store instructions -system.cpu0.num_idle_cycles 1756006001.161348 # Number of idle cycles -system.cpu0.num_busy_cycles 45221299.838652 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025106 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974894 # Percentage of idle cycles -system.cpu0.Branches 6054325 # Number of branches fetched +system.cpu0.num_cc_register_reads 134799783 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 18388749 # number of times the CC registers were written +system.cpu0.num_mem_refs 14597797 # number of memory refs +system.cpu0.num_load_insts 7571468 # Number of load instructions +system.cpu0.num_store_insts 7026329 # Number of store instructions +system.cpu0.num_idle_cycles 1756040520.255098 # Number of idle cycles +system.cpu0.num_busy_cycles 45180437.744902 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025083 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974917 # Percentage of idle cycles +system.cpu0.Branches 6054439 # Number of branches fetched system.cpu0.op_class::No_OpClass 13280 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 30338974 67.42% 67.45% # Class of executed instruction +system.cpu0.op_class::IntAlu 30339474 67.42% 67.45% # Class of executed instruction system.cpu0.op_class::IntMult 51765 0.12% 67.56% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.56% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.56% # Class of executed instruction @@ -417,52 +537,51 @@ system.cpu0.op_class::SimdFloatMisc 639 0.00% 67.56% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.56% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.56% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.56% # Class of executed instruction -system.cpu0.op_class::MemRead 7571296 16.82% 84.39% # Class of executed instruction -system.cpu0.op_class::MemWrite 7026183 15.61% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 7571468 16.82% 84.39% # Class of executed instruction +system.cpu0.op_class::MemWrite 7026329 15.61% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 45002137 # Class of executed instruction +system.cpu0.op_class::total 45002955 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42773 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 419775 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.035896 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 37516680 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 420287 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 89.264431 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 64363581500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.035896 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998117 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998117 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 42789 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 346148 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.428315 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 37590948 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 346660 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 108.437512 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 4521683000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.428315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998883 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 38357256 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 38357256 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 37516680 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 37516680 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 37516680 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 37516680 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 37516680 # number of overall hits -system.cpu0.icache.overall_hits::total 37516680 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 420288 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 420288 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 420288 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 420288 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 420288 # number of overall misses -system.cpu0.icache.overall_misses::total 420288 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37936968 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37936968 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37936968 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37936968 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37936968 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37936968 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011079 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011079 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011079 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011079 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011079 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011079 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 76221879 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76221879 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 37590948 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37590948 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37590948 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37590948 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37590948 # number of overall hits +system.cpu0.icache.overall_hits::total 37590948 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 346661 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 346661 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 346661 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 346661 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 346661 # number of overall misses +system.cpu0.icache.overall_misses::total 346661 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37937609 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37937609 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37937609 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37937609 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37937609 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37937609 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009138 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009138 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009138 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009138 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009138 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009138 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,76 +591,211 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 348431 # number of replacements -system.cpu0.dcache.tags.tagsinuse 471.119339 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12834011 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 348738 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.801298 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 133971 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15179.385733 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 737408 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 149269 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.940128 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 992860000 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7074.912262 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.111336 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.268775 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3357.655544 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4738.437815 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.431818 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000495 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.204935 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.289211 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.926476 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15278 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3216 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5292 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 6770 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.932495 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 17962499 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 17962499 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4364 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 1619 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 326789 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 179454 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 512226 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 323282 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 323282 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 38112 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 38112 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 4364 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 1619 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 326789 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 217566 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 550338 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 4364 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 1619 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 326789 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 217566 # number of overall hits +system.cpu0.l2cache.overall_hits::total 550338 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 89 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 56 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 19767 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 70654 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 90566 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 12767 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 12767 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 8852 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 8852 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 114761 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 114761 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 89 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 56 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 19767 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 185415 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 205327 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 89 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 56 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 19767 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 185415 # number of overall misses +system.cpu0.l2cache.overall_misses::total 205327 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4453 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 1675 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 346556 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 250108 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 602792 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 323282 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 323282 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 12769 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 12769 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 8852 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 8852 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 152873 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 152873 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 4453 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 1675 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 346556 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 402981 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 755665 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 4453 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 1675 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 346556 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 402981 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 755665 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.033433 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.057038 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.282494 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.150244 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999843 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999843 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.750695 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.750695 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.033433 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.057038 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.460109 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.271717 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019987 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.033433 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.057038 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.460109 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.271717 # miss rate for overall accesses +system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.l2cache.fast_writes 0 # number of fast writes performed +system.cpu0.l2cache.cache_copies 0 # number of cache copies performed +system.cpu0.l2cache.writebacks::writebacks 114351 # number of writebacks +system.cpu0.l2cache.writebacks::total 114351 # number of writebacks +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 371621 # number of replacements +system.cpu0.dcache.tags.tagsinuse 458.751149 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 12812322 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 371931 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.448115 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 22109000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.119339 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920155 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.920155 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.599609 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 53249455 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 53249455 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6868875 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6868875 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5598061 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5598061 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 78744 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 78744 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135195 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 135195 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 136387 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 136387 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12466936 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12466936 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12545680 # number of overall hits -system.cpu0.dcache.overall_hits::total 12545680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 173318 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 173318 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 159147 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 159147 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 50343 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 50343 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9388 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9388 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7646 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7646 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 332465 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 332465 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 382808 # number of overall misses -system.cpu0.dcache.overall_misses::total 382808 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042193 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7042193 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757208 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5757208 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.751149 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895998 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.895998 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.605469 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 26837769 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 26837769 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6854480 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6854480 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5591690 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5591690 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 77211 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 77211 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 134223 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 134223 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 135188 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 135188 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12446170 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12446170 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12523381 # number of overall hits +system.cpu0.dcache.overall_hits::total 12523381 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 187851 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 187851 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 165642 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 165642 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 51876 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 51876 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10381 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10381 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8852 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 8852 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 353493 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 353493 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 405369 # number of overall misses +system.cpu0.dcache.overall_misses::total 405369 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7042331 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7042331 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5757332 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5757332 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 129087 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 129087 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144583 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 144583 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144033 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144033 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12799401 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12799401 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12928488 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12928488 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.024611 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.024611 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027643 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.027643 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.389993 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.389993 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064932 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064932 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053085 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053085 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025975 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025975 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029610 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029610 # miss rate for overall accesses +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 144604 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 144604 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144040 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144040 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12799663 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12799663 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12928750 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12928750 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026675 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.026675 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028771 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.028771 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.401869 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.401869 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.071789 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.071789 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.061455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.061455 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027617 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027617 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031354 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031354 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -550,9 +804,45 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 321785 # number of writebacks -system.cpu0.dcache.writebacks::total 321785 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 323282 # number of writebacks +system.cpu0.dcache.writebacks::total 323282 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 689270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 689270 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 763494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 763494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 323282 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 12769 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 8852 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 21621 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 152873 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 152873 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 706618 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2854542 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 4790 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 11848 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 3577798 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 22212896 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 49695730 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9580 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 23696 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 71941902 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 229047 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1276029 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.135706 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.342476 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1102864 86.43% 86.43% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 173165 13.57% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 1276029 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -576,9 +866,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6028686 # DTB read hits -system.cpu1.dtb.read_misses 5403 # DTB read misses -system.cpu1.dtb.write_hits 4781604 # DTB write hits +system.cpu1.dtb.read_hits 6029083 # DTB read hits +system.cpu1.dtb.read_misses 5405 # DTB read misses +system.cpu1.dtb.write_hits 4781968 # DTB write hits system.cpu1.dtb.write_misses 1104 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -589,12 +879,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 185 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6034089 # DTB read accesses -system.cpu1.dtb.write_accesses 4782708 # DTB write accesses +system.cpu1.dtb.read_accesses 6034488 # DTB read accesses +system.cpu1.dtb.write_accesses 4783072 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10810290 # DTB hits -system.cpu1.dtb.misses 6507 # DTB misses -system.cpu1.dtb.accesses 10816797 # DTB accesses +system.cpu1.dtb.hits 10811051 # DTB hits +system.cpu1.dtb.misses 6509 # DTB misses +system.cpu1.dtb.accesses 10817560 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -616,7 +906,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 24626141 # ITB inst hits +system.cpu1.itb.inst_hits 24627232 # ITB inst hits system.cpu1.itb.inst_misses 3166 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -633,38 +923,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 24629307 # ITB inst accesses -system.cpu1.itb.hits 24626141 # DTB hits +system.cpu1.itb.inst_accesses 24630398 # ITB inst accesses +system.cpu1.itb.hits 24627232 # DTB hits system.cpu1.itb.misses 3166 # DTB misses -system.cpu1.itb.accesses 24629307 # DTB accesses -system.cpu1.numCycles 1801709576 # number of cpu cycles simulated +system.cpu1.itb.accesses 24630398 # DTB accesses +system.cpu1.numCycles 1801708036 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 23838609 # Number of instructions committed -system.cpu1.committedOps 29191016 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 25547086 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5650 # Number of float alu accesses -system.cpu1.num_func_calls 987842 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2987341 # number of instructions that are conditional controls -system.cpu1.num_int_insts 25547086 # number of integer instructions -system.cpu1.num_fp_insts 5650 # number of float instructions -system.cpu1.num_int_register_reads 48277330 # number of times the integer registers were read -system.cpu1.num_int_register_writes 17495174 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3706 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 86963152 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 11050350 # number of times the CC registers were written -system.cpu1.num_mem_refs 11165955 # number of memory refs -system.cpu1.num_load_insts 6206289 # Number of load instructions -system.cpu1.num_store_insts 4959666 # Number of store instructions -system.cpu1.num_idle_cycles 1771680344.893366 # Number of idle cycles -system.cpu1.num_busy_cycles 30029231.106634 # Number of busy cycles -system.cpu1.not_idle_fraction 0.016667 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.983333 # Percentage of idle cycles -system.cpu1.Branches 4459555 # Number of branches fetched +system.cpu1.committedInsts 23839695 # Number of instructions committed +system.cpu1.committedOps 29192667 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 25548618 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5779 # Number of float alu accesses +system.cpu1.num_func_calls 987959 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2987443 # number of instructions that are conditional controls +system.cpu1.num_int_insts 25548618 # number of integer instructions +system.cpu1.num_fp_insts 5779 # number of float instructions +system.cpu1.num_int_register_reads 48280801 # number of times the integer registers were read +system.cpu1.num_int_register_writes 17496069 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3771 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2012 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 86968126 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 11050847 # number of times the CC registers were written +system.cpu1.num_mem_refs 11166773 # number of memory refs +system.cpu1.num_load_insts 6206724 # Number of load instructions +system.cpu1.num_store_insts 4960049 # Number of store instructions +system.cpu1.num_idle_cycles 1771724648.110516 # Number of idle cycles +system.cpu1.num_busy_cycles 29983387.889484 # Number of busy cycles +system.cpu1.not_idle_fraction 0.016642 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.983358 # Percentage of idle cycles +system.cpu1.Branches 4459767 # Number of branches fetched system.cpu1.op_class::No_OpClass 15552 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 18046643 61.66% 61.71% # Class of executed instruction -system.cpu1.op_class::IntMult 40424 0.14% 61.85% # Class of executed instruction +system.cpu1.op_class::IntAlu 18047467 61.65% 61.71% # Class of executed instruction +system.cpu1.op_class::IntMult 40427 0.14% 61.85% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 61.85% # Class of executed instruction @@ -688,58 +978,58 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 61.85% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 61.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1539 0.01% 61.85% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1550 0.01% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 61.85% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 61.85% # Class of executed instruction -system.cpu1.op_class::MemRead 6206289 21.20% 83.06% # Class of executed instruction -system.cpu1.op_class::MemWrite 4959666 16.94% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 6206724 21.20% 83.06% # Class of executed instruction +system.cpu1.op_class::MemWrite 4960049 16.94% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 29270113 # Class of executed instruction +system.cpu1.op_class::total 29271769 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48301 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 442993 # number of replacements -system.cpu1.icache.tags.tagsinuse 472.644505 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 24184321 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 443505 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 54.529985 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 254679414000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.644505 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.923134 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.923134 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 48299 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 398154 # number of replacements +system.cpu1.icache.tags.tagsinuse 474.812776 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 24230251 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 398666 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 60.778323 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 103932913000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 474.812776 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.927369 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.927369 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 257 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 25071331 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 25071331 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 24184321 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 24184321 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 24184321 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 24184321 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 24184321 # number of overall hits -system.cpu1.icache.overall_hits::total 24184321 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 443505 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 443505 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 443505 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 443505 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 443505 # number of overall misses -system.cpu1.icache.overall_misses::total 443505 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 24627826 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 24627826 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 24627826 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 24627826 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 24627826 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 24627826 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018008 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.018008 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018008 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.018008 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018008 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.018008 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 49656500 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 49656500 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 24230251 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 24230251 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 24230251 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 24230251 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 24230251 # number of overall hits +system.cpu1.icache.overall_hits::total 24230251 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 398666 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 398666 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 398666 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 398666 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 398666 # number of overall misses +system.cpu1.icache.overall_misses::total 398666 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 24628917 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 24628917 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 24628917 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 24628917 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 24628917 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 24628917 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016187 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.016187 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016187 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.016187 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016187 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.016187 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -749,79 +1039,215 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 274056 # number of replacements -system.cpu1.dcache.tags.tagsinuse 468.122166 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 9407683 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 274568 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 34.263581 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 94419429000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 468.122166 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.914301 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.914301 # Average percentage of cache occupancy +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 0 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 88565 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 12390.036216 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 691452 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 104644 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.607660 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 876305009500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 6229.071421 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 8.886003 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.649559 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3323.104999 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2826.324234 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.380192 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000542 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000162 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.202826 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.172505 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.756228 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 16066 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9480 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2833 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.980591 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15740589 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15740589 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 5896 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2700 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 375664 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 151551 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 535811 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 209707 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 209707 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 21 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 48287 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 48287 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 5896 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2700 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 375664 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 199838 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 584098 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 5896 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2700 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 375664 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 199838 # number of overall hits +system.cpu1.l2cache.overall_hits::total 584098 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 263 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22734 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 51350 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 74696 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 18752 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 18752 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 11227 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 11227 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 68490 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 68490 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 263 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 22734 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 119840 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 143186 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 263 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 22734 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 119840 # number of overall misses +system.cpu1.l2cache.overall_misses::total 143186 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 6245 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2963 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 398398 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 202901 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 610507 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 209707 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 209707 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 18773 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 18773 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 11227 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 11227 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 116777 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 116777 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6245 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2963 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 398398 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 319678 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 727284 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 6245 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2963 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 398398 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 319678 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 727284 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.088761 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.057064 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.253079 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.122351 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998881 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998881 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.586502 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.586502 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.088761 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.057064 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.374877 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.196878 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.055885 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.088761 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.057064 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.374877 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.196878 # miss rate for overall accesses +system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.l2cache.fast_writes 0 # number of fast writes performed +system.cpu1.l2cache.cache_copies 0 # number of cache copies performed +system.cpu1.l2cache.writebacks::writebacks 61322 # number of writebacks +system.cpu1.l2cache.writebacks::total 61322 # number of writebacks +system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.tags.replacements 299305 # number of replacements +system.cpu1.dcache.tags.tagsinuse 464.628152 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 9384005 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 299817 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 31.299109 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 94422670000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 464.628152 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.907477 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.907477 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 322 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39106907 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39106907 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4611957 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4611957 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4543395 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4543395 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35603 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 35603 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94939 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 94939 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 95657 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 95657 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9155352 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9155352 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9190955 # number of overall hits -system.cpu1.dcache.overall_hits::total 9190955 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 143554 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 143554 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 130048 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 130048 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 27770 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 27770 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10527 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10527 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9468 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9468 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 273602 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 273602 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 301372 # number of overall misses -system.cpu1.dcache.overall_misses::total 301372 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755511 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 4755511 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673443 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4673443 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.tag_accesses 19727044 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 19727044 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4592285 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4592285 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4538287 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4538287 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 35329 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 35329 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 94231 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 94231 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 93873 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 93873 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9130572 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9130572 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9165901 # number of overall hits +system.cpu1.dcache.overall_hits::total 9165901 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 163656 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 163656 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 135550 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 135550 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 28044 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 28044 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11201 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11201 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 11227 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 11227 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 299206 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 299206 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 327250 # number of overall misses +system.cpu1.dcache.overall_misses::total 327250 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4755941 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4755941 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4673837 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4673837 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 63373 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 63373 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105466 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 105466 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105125 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 9428954 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 9428954 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9492327 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9492327 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.030187 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.030187 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027827 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.027827 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.438199 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.438199 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099814 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.099814 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.090064 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.090064 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029017 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.029017 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.031749 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.031749 # miss rate for overall accesses +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 105432 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105100 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105100 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 9429778 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 9429778 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 9493151 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 9493151 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.034411 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.034411 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029002 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.029002 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.442523 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.442523 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.106239 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.106239 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106822 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106822 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031730 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031730 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034472 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.034472 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -830,9 +1256,45 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 249941 # number of writebacks -system.cpu1.dcache.writebacks::total 249941 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 209707 # number of writebacks +system.cpu1.dcache.writebacks::total 209707 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 1728836 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1728836 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 3546 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 3546 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 209707 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 18773 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 11227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 30000 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 116777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 116777 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797550 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 3132383 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12644 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25448 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3968025 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25515060 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36101346 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50896 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 61692590 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 259574 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1204043 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.188487 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.391100 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 977097 81.15% 81.15% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 226946 18.85% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1204043 # Request fanout histogram system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 511b86cf1..227319fff 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,18 +1,30 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.321351 # Number of seconds simulated -sim_ticks 2321351025500 # Number of ticks simulated -final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321335 # Number of seconds simulated +sim_ticks 2321335404000 # Number of ticks simulated +final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 818788 # Simulator instruction rate (inst/s) -host_op_rate 985991 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31464875718 # Simulator tick rate (ticks/s) -host_mem_usage 430844 # Number of bytes of host memory used -host_seconds 73.78 # Real time elapsed on the host +host_inst_rate 1308981 # Simulator instruction rate (inst/s) +host_op_rate 1576286 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50301976363 # Simulator tick rate (ticks/s) +host_mem_usage 455960 # Number of bytes of host memory used +host_seconds 46.15 # Real time elapsed on the host sim_insts 60406834 # Number of instructions simulated sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory @@ -33,47 +45,127 @@ system.physmem.num_reads::total 13921575 # Nu system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 303884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3908023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 303884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595578 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1299173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894751 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55568847 # Throughput (bytes/s) -system.membus.data_through_bus 128994799 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.physmem.bw_total::cpu.inst 303884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5207196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536681 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 14973631 # Transaction distribution +system.membus.trans_dist::ReadResp 14973631 # Transaction distribution +system.membus.trans_dist::WriteReq 763122 # Transaction distribution +system.membus.trans_dist::WriteResp 763122 # Transaction distribution +system.membus.trans_dist::Writeback 57873 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution +system.membus.trans_dist::ReadExReq 131874 # Transaction distribution +system.membus.trans_dist::ReadExResp 131874 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892845 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4279041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31804161 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16497448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18894319 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 128994799 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214751 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 214751 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 214751 # Request fanout histogram system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48459111 # Throughput (bytes/s) -system.iobus.data_through_bus 112490607 # Total data (bytes) +system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution +system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution +system.iobus.trans_dist::WriteReq 8131 # Transaction distribution +system.iobus.trans_dist::WriteResp 8131 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -98,7 +190,7 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13142244 # DTB read hits +system.cpu.dtb.read_hits 13142243 # DTB read hits system.cpu.dtb.read_misses 7297 # DTB read misses system.cpu.dtb.write_hits 11216207 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses @@ -111,12 +203,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13149541 # DTB read accesses +system.cpu.dtb.read_accesses 13149540 # DTB read accesses system.cpu.dtb.write_accesses 11218388 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 24358451 # DTB hits +system.cpu.dtb.hits 24358450 # DTB hits system.cpu.dtb.misses 9478 # DTB misses -system.cpu.dtb.accesses 24367929 # DTB accesses +system.cpu.dtb.accesses 24367928 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -159,7 +251,7 @@ system.cpu.itb.inst_accesses 61434478 # IT system.cpu.itb.hits 61430007 # DTB hits system.cpu.itb.misses 4471 # DTB misses system.cpu.itb.accesses 61434478 # DTB accesses -system.cpu.numCycles 4642702052 # number of cpu cycles simulated +system.cpu.numCycles 4642753590 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 60406834 # Number of instructions committed @@ -179,10 +271,10 @@ system.cpu.num_cc_register_writes 28977741 # nu system.cpu.num_mem_refs 25221274 # number of memory refs system.cpu.num_load_insts 13499937 # Number of load instructions system.cpu.num_store_insts 11721337 # Number of store instructions -system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles -system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles -system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.984091 # Percentage of idle cycles +system.cpu.num_idle_cycles 4568976022.512934 # Number of idle cycles +system.cpu.num_busy_cycles 73777567.487067 # Number of busy cycles +system.cpu.not_idle_fraction 0.015891 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.984109 # Percentage of idle cycles system.cpu.Branches 10298517 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction @@ -221,35 +313,35 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 72875708 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 850515 # number of replacements -system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 850504 # number of replacements +system.cpu.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60581751 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.689630 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits -system.cpu.icache.overall_hits::total 60581740 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses -system.cpu.icache.overall_misses::total 851027 # number of overall misses +system.cpu.icache.tags.tag_accesses 62283783 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62283783 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60581751 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60581751 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60581751 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60581751 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60581751 # number of overall hits +system.cpu.icache.overall_hits::total 60581751 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 851016 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 851016 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 851016 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 851016 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 851016 # number of overall misses +system.cpu.icache.overall_misses::total 851016 # number of overall misses system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses @@ -272,21 +364,21 @@ system.cpu.icache.fast_writes 0 # nu system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 62250 # number of replacements -system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 50006.820137 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1669876 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959775 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993971 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.537259 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.563017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.avg_refs 13.083214 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36897.819647 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.959772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993972 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.485209 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6090.561537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563016 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107032 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.107033 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.092935 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id @@ -298,29 +390,29 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17035648 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7541 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 17035355 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17035355 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7540 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 838793 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 366790 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1216275 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 838782 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 366774 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1216247 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 592630 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 592630 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 113706 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 113706 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 7541 # number of demand (read+write) hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 113709 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 113709 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7540 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 838793 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 480496 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1329981 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 7541 # number of overall hits +system.cpu.l2cache.demand_hits::cpu.inst 838782 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 480483 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1329956 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7540 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3151 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 838793 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 480496 # number of overall hits -system.cpu.l2cache.overall_hits::total 1329981 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 838782 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 480483 # number of overall hits +system.cpu.l2cache.overall_hits::total 1329956 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.inst 10608 # number of ReadReq misses @@ -340,46 +432,46 @@ system.cpu.l2cache.overall_misses::cpu.itb.walker 3 system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses system.cpu.l2cache.overall_misses::total 153961 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7545 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 849401 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 849390 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 376645 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1236734 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 592630 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 592630 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 247183 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 247183 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7545 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 849401 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 849390 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 623828 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1483917 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7545 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 849390 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 623828 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1483917 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539981 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.539981 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.229783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.103753 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.229783 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.103753 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,11 +483,11 @@ system.cpu.l2cache.cache_copies 0 # nu system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks system.cpu.l2cache.writebacks::total 57873 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 623329 # number of replacements +system.cpu.dcache.tags.replacements 623316 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21798557 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 623828 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.943217 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -405,36 +497,36 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 90313368 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 90313368 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11240238 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11240238 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9961313 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9961313 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236011 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236011 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits -system.cpu.dcache.overall_hits::total 21312398 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 21201551 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21201551 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21312407 # number of overall hits +system.cpu.dcache.overall_hits::total 21312407 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 292017 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 292017 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250126 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250126 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses -system.cpu.dcache.overall_misses::total 615595 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11186 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11186 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 542143 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 542143 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615585 # number of overall misses +system.cpu.dcache.overall_misses::total 615585 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 11532255 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11532255 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses) @@ -443,20 +535,20 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 21743694 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21743694 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21927992 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21927992 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025322 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025322 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024933 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024933 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -467,12 +559,44 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks -system.cpu.dcache.writebacks::total 592642 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592630 # number of writebacks +system.cpu.dcache.writebacks::total 592630 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 2445766 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2445766 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 592630 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247183 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5740322 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17852 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7510658 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83266131 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 35704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74380 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 137867763 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2097938 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2097938 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2097938 # Request fanout histogram system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 051c13810..73c076f14 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,167 +1,189 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.194312 # Number of seconds simulated -sim_ticks 1194312178000 # Number of ticks simulated -final_tick 1194312178000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.675181 # Number of seconds simulated +sim_ticks 2675180779000 # Number of ticks simulated +final_tick 2675180779000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 475403 # Simulator instruction rate (inst/s) -host_op_rate 567868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9241250441 # Simulator tick rate (ticks/s) -host_mem_usage 438040 # Number of bytes of host memory used -host_seconds 129.24 # Real time elapsed on the host -sim_insts 61439698 # Number of instructions simulated -sim_ops 73389630 # Number of ops (including micro ops) simulated +host_inst_rate 485184 # Simulator instruction rate (inst/s) +host_op_rate 579312 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20736099933 # Simulator tick rate (ticks/s) +host_mem_usage 486856 # Number of bytes of host memory used +host_seconds 129.01 # Real time elapsed on the host +sim_insts 62593972 # Number of instructions simulated +sim_ops 74737529 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393932 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4710012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 323460 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4796088 # Number of bytes read from this memory -system.physmem.bytes_read::total 62128516 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393932 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 323460 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717392 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4097216 # Number of bytes written to this memory +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 120908 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 513788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 6659968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 37828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 531832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 3262144 # Number of bytes read from this memory +system.physmem.bytes_read::total 135383236 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 120908 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 37828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 158736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4300032 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7124560 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12383 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5145 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74957 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6654210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64019 # Number of write requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7329168 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 8117 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 8087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 104062 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 682 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 50971 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15712287 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 67188 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820855 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43459753 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 107 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 329840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3943703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 54 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 270834 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4015774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52020332 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 329840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 270834 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600674 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3430607 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2520567 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5965408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3430607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43459753 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 329840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3957937 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 54 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 270834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6536341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57985740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6654210 # Number of read requests accepted -system.physmem.writeReqs 820855 # Number of write requests accepted -system.physmem.readBursts 6654210 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 820855 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 425838464 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue -system.physmem.bytesWritten 7136448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62128516 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7124560 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709321 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12079 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 415236 # Per bank write bursts -system.physmem.perBankRdBursts::1 415218 # Per bank write bursts -system.physmem.perBankRdBursts::2 415240 # Per bank write bursts -system.physmem.perBankRdBursts::3 415658 # Per bank write bursts -system.physmem.perBankRdBursts::4 422402 # Per bank write bursts -system.physmem.perBankRdBursts::5 415506 # Per bank write bursts -system.physmem.perBankRdBursts::6 415779 # Per bank write bursts -system.physmem.perBankRdBursts::7 415682 # Per bank write bursts -system.physmem.perBankRdBursts::8 416047 # Per bank write bursts -system.physmem.perBankRdBursts::9 415577 # Per bank write bursts -system.physmem.perBankRdBursts::10 415398 # Per bank write bursts -system.physmem.perBankRdBursts::11 414862 # Per bank write bursts -system.physmem.perBankRdBursts::12 415007 # Per bank write bursts -system.physmem.perBankRdBursts::13 415552 # Per bank write bursts -system.physmem.perBankRdBursts::14 415496 # Per bank write bursts -system.physmem.perBankRdBursts::15 415066 # Per bank write bursts -system.physmem.perBankWrBursts::0 6763 # Per bank write bursts -system.physmem.perBankWrBursts::1 6728 # Per bank write bursts -system.physmem.perBankWrBursts::2 6819 # Per bank write bursts -system.physmem.perBankWrBursts::3 7055 # Per bank write bursts -system.physmem.perBankWrBursts::4 7301 # Per bank write bursts -system.physmem.perBankWrBursts::5 7028 # Per bank write bursts -system.physmem.perBankWrBursts::6 7316 # Per bank write bursts -system.physmem.perBankWrBursts::7 7231 # Per bank write bursts -system.physmem.perBankWrBursts::8 7485 # Per bank write bursts -system.physmem.perBankWrBursts::9 7107 # Per bank write bursts -system.physmem.perBankWrBursts::10 7000 # Per bank write bursts -system.physmem.perBankWrBursts::11 6549 # Per bank write bursts -system.physmem.perBankWrBursts::12 6696 # Per bank write bursts -system.physmem.perBankWrBursts::13 6902 # Per bank write bursts -system.physmem.perBankWrBursts::14 6960 # Per bank write bursts -system.physmem.perBankWrBursts::15 6567 # Per bank write bursts +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 824472 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46447798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 96 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 45196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 192057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2489539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 48 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 198802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 1219411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50607135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 45196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14140 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 59337 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1607380 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6355 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1125956 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2739691 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1607380 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46447798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 96 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 45196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 198412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2489539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 48 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1324758 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 1219411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53346826 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15712287 # Number of read requests accepted +system.physmem.writeReqs 824472 # Number of write requests accepted +system.physmem.readBursts 15712287 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 824472 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1005465984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 120384 # Total number of bytes read from write queue +system.physmem.bytesWritten 7344256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 135383236 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7329168 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1881 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709695 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15472 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 981539 # Per bank write bursts +system.physmem.perBankRdBursts::1 981448 # Per bank write bursts +system.physmem.perBankRdBursts::2 981211 # Per bank write bursts +system.physmem.perBankRdBursts::3 981521 # Per bank write bursts +system.physmem.perBankRdBursts::4 988300 # Per bank write bursts +system.physmem.perBankRdBursts::5 981533 # Per bank write bursts +system.physmem.perBankRdBursts::6 981210 # Per bank write bursts +system.physmem.perBankRdBursts::7 981071 # Per bank write bursts +system.physmem.perBankRdBursts::8 981831 # Per bank write bursts +system.physmem.perBankRdBursts::9 982015 # Per bank write bursts +system.physmem.perBankRdBursts::10 981421 # Per bank write bursts +system.physmem.perBankRdBursts::11 980878 # Per bank write bursts +system.physmem.perBankRdBursts::12 981926 # Per bank write bursts +system.physmem.perBankRdBursts::13 981948 # Per bank write bursts +system.physmem.perBankRdBursts::14 981516 # Per bank write bursts +system.physmem.perBankRdBursts::15 981038 # Per bank write bursts +system.physmem.perBankWrBursts::0 7155 # Per bank write bursts +system.physmem.perBankWrBursts::1 7293 # Per bank write bursts +system.physmem.perBankWrBursts::2 6957 # Per bank write bursts +system.physmem.perBankWrBursts::3 6994 # Per bank write bursts +system.physmem.perBankWrBursts::4 7537 # Per bank write bursts +system.physmem.perBankWrBursts::5 7187 # Per bank write bursts +system.physmem.perBankWrBursts::6 7207 # Per bank write bursts +system.physmem.perBankWrBursts::7 7058 # Per bank write bursts +system.physmem.perBankWrBursts::8 7329 # Per bank write bursts +system.physmem.perBankWrBursts::9 7596 # Per bank write bursts +system.physmem.perBankWrBursts::10 7177 # Per bank write bursts +system.physmem.perBankWrBursts::11 6681 # Per bank write bursts +system.physmem.perBankWrBursts::12 7505 # Per bank write bursts +system.physmem.perBankWrBursts::13 7329 # Per bank write bursts +system.physmem.perBankWrBursts::14 7034 # Per bank write bursts +system.physmem.perBankWrBursts::15 6715 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1194307723500 # Total gap between requests +system.physmem.totGap 2675178052500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6799 # Read request sizes (log2) -system.physmem.readPktSize::3 6488089 # Read request sizes (log2) +system.physmem.readPktSize::3 15532057 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159322 # Read request sizes (log2) +system.physmem.readPktSize::6 173431 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 64019 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 572550 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 410650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 412558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 460055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 417389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 445707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1151151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1116358 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1442650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 62467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 48974 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44870 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 43130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8270 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67188 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1100287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996591 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 996926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1111424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1006011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1072049 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2766642 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2669294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3474563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 133275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 106575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20020 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see @@ -180,47 +202,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6950 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -229,394 +251,422 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 473292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 914.815615 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 785.169464 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.643252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25022 5.29% 5.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21566 4.56% 9.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5869 1.24% 11.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2391 0.51% 11.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2344 0.50% 12.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1629 0.34% 12.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4093 0.86% 13.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 899 0.19% 13.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 409479 86.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 473292 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6481 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1026.648974 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 26505.494009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6473 99.88% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6481 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6481 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.205215 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.176618 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.984217 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2581 39.82% 39.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.23% 40.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3862 59.59% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 20 0.31% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6481 # Writes before turning the bus around for reads -system.physmem.totQLat 170730095750 # Total ticks spent queuing -system.physmem.totMemAccLat 295487458250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 33268630000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25659.32 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1051606 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.108084 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 883.927529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 220.726845 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33004 3.14% 3.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22001 2.09% 5.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9307 0.89% 6.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2514 0.24% 6.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3272 0.31% 6.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2167 0.21% 6.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8722 0.83% 7.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1051 0.10% 7.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969568 92.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1051606 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6601 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2380.003939 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98592.588392 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6595 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6601 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6601 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.384336 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.341066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.250693 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2463 37.31% 37.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 32 0.48% 37.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3686 55.84% 93.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 215 3.26% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 85 1.29% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.76% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 28 0.42% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.21% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 7 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6601 # Writes before turning the bus around for reads +system.physmem.totQLat 408788863752 # Total ticks spent queuing +system.physmem.totMemAccLat 703358976252 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78552030000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26020.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44409.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 356.56 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.98 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 52.02 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.97 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44770.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 375.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.61 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.83 # Data bus utilization in percentage -system.physmem.busUtilRead 2.79 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 4.36 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.98 # Average write queue length when enqueuing -system.physmem.readRowHits 6199598 # Number of row buffer hits during reads -system.physmem.writeRowHits 92343 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.79 # Row buffer hit rate for writes -system.physmem.avgGap 159772.22 # Average gap between requests -system.physmem.pageHitRate 93.00 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 945808643750 # Time in different power states -system.physmem.memoryStateTime::REF 39880620000 # Time in different power states +system.physmem.busUtil 2.96 # Data bus utilization in percentage +system.physmem.busUtilRead 2.94 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 6.50 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.70 # Average write queue length when enqueuing +system.physmem.readRowHits 14689438 # Number of row buffer hits during reads +system.physmem.writeRowHits 84116 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.29 # Row buffer hit rate for writes +system.physmem.avgGap 161771.61 # Average gap between requests +system.physmem.pageHitRate 93.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2326940534750 # Time in different power states +system.physmem.memoryStateTime::REF 89330020000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 208620525000 # Time in different power states +system.physmem.memoryStateTime::ACT 258906121500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 40 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 40 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 40 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 60005732 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7703348 # Transaction distribution -system.membus.trans_dist::ReadResp 7703348 # Transaction distribution -system.membus.trans_dist::WriteReq 767581 # Transaction distribution -system.membus.trans_dist::WriteResp 767581 # Transaction distribution -system.membus.trans_dist::Writeback 64019 # Transaction distribution -system.membus.trans_dist::UpgradeReq 31325 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17234 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12079 # Transaction distribution -system.membus.trans_dist::ReadExReq 137481 # Transaction distribution -system.membus.trans_dist::ReadExResp 137066 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382642 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 16891737 # Transaction distribution +system.membus.trans_dist::ReadResp 16891737 # Transaction distribution +system.membus.trans_dist::WriteReq 769090 # Transaction distribution +system.membus.trans_dist::WriteResp 769090 # Transaction distribution +system.membus.trans_dist::Writeback 67188 # Transaction distribution +system.membus.trans_dist::UpgradeReq 56135 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 22757 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15472 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 15580 # Transaction distribution +system.membus.trans_dist::ReadExResp 8709 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384390 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 906 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971036 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4364934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 12976128 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17341062 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389989 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 20624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1812 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17348564 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19761065 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 71665577 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 71665577 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1224785500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2098 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2043502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4443432 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35507496 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4196 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18456148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 20879924 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 145136180 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 70292 # Total snoops (count) +system.membus.snoop_fanout::samples 326383 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 326383 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 326383 # Request fanout histogram +system.membus.reqLayer0.occupancy 1567209495 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 18000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9231500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11789999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 778500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 2092500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 9212282000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 5079172023 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 16050388750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.reqLayer6.occupancy 18080219999 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4994463970 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 38410223885 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 69203 # number of replacements -system.l2c.tags.tagsinuse 52959.316379 # Cycle average of tags in use -system.l2c.tags.total_refs 1672724 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 134375 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 12.448179 # Average number of references to valid blocks. +system.l2c.tags.replacements 91391 # number of replacements +system.l2c.tags.tagsinuse 54779.294121 # Cycle average of tags in use +system.l2c.tags.total_refs 364235 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156090 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.333493 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 40136.915421 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000411 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001544 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3716.167205 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4233.542603 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.741623 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.001622 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2809.362324 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2060.583626 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.612441 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.064599 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042867 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.031442 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808095 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 8096.170170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.060665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.035962 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 869.411373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1869.125081 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29277.356218 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.888363 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 410.348906 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3214.362362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11039.535021 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.123538 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.013266 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028521 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.446737 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.006261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.049047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.168450 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.835866 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 51568 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 13123 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4964 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 46576 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8176 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55031 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17204185 # Number of tag accesses -system.l2c.tags.data_accesses 17204185 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 3944 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1786 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419390 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 205855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5333 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1846 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 464270 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 143434 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1245858 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 570720 # number of Writeback hits -system.l2c.Writeback_hits::total 570720 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1291 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1814 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 97 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 311 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56339 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 52717 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109056 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 3944 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 1786 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 419390 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 262194 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5333 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1846 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 464270 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 196151 # number of demand (read+write) hits -system.l2c.demand_hits::total 1354914 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 3944 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 1786 # number of overall hits -system.l2c.overall_hits::cpu0.inst 419390 # number of overall hits -system.l2c.overall_hits::cpu0.data 262194 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5333 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1846 # number of overall hits -system.l2c.overall_hits::cpu1.inst 464270 # number of overall hits -system.l2c.overall_hits::cpu1.data 196151 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.190550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.243771 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.485099 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.686385 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.760919 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.715100 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.491750 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.017699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.066667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.197985 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.315295 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.541127 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.022472 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.107517 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.362041 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.516345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.491750 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61536.078404 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64144.911504 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 60422.020983 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.865377 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.762019 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10012.913857 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.109347 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10009.472458 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10012.548604 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53749.881836 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59393.523292 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56679.960281 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63612.049707 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65506.557783 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83986.890786 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10043.574479 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10025.066839 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10035.987400 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10112.391602 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10020.746628 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.249887 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60750.569019 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59271.077532 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60028.558346 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41250 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 58039.547038 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 54565.083729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58734.350238 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59619.458537 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57194.817495 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68292.740841 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 62017.659701 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 74176.442323 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73237.606838 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62293.819338 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107493.558749 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82771.736116 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -810,67 +872,53 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 119643708 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2534658 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2534658 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767581 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767581 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 570720 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 30701 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17545 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 48246 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260694 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260694 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 864108 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1226294 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 6184 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 12819 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 939372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4600756 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 6173 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 15243 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7670949 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 27234976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 41362613 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 7152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 15780 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30036788 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39599456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 7388 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 21348 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138285501 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138285501 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4606436 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4757764712 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1924888432 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1752701680 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 4396499 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 8876994 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2115350205 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2925844707 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 4326000 # Layer occupancy (ticks) -system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 9906999 # Layer occupancy (ticks) -system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45460895 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7671423 # Transaction distribution -system.iobus.trans_dist::ReadResp 7671423 # Transaction distribution -system.iobus.trans_dist::WriteReq 7962 # Transaction distribution -system.iobus.trans_dist::WriteResp 7962 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30548 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8040 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 1633013 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1633009 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769090 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769090 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 208041 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 61292 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 23072 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 84364 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 39 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 23321 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 23321 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 2956029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 2099720 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5055749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 25795270 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 15582958 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41378228 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 171942 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 753795 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 753795 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 753795 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2576673570 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2390227339 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1329617427 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 16716140 # Transaction distribution +system.iobus.trans_dist::ReadResp 16716140 # Transaction distribution +system.iobus.trans_dist::WriteReq 8087 # Transaction distribution +system.iobus.trans_dist::WriteResp 8087 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8820 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -887,54 +935,53 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382642 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 12976128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 15358770 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40317 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1480 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389989 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 51904512 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 54294501 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 54294501 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21416000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 2384390 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33448454 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40731 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 126648952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21726000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4026000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4416000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 376000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 528000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 298000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -965,12 +1012,12 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6488064000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374680000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16364250250 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376303000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 39178496115 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +1041,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6063582 # DTB read hits -system.cpu0.dtb.read_misses 3748 # DTB read misses -system.cpu0.dtb.write_hits 5648980 # DTB write hits -system.cpu0.dtb.write_misses 807 # DTB write misses +system.cpu0.dtb.read_hits 7131006 # DTB read hits +system.cpu0.dtb.read_misses 3644 # DTB read misses +system.cpu0.dtb.write_hits 6127729 # DTB write hits +system.cpu0.dtb.write_misses 663 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1893 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 116 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6067330 # DTB read accesses -system.cpu0.dtb.write_accesses 5649787 # DTB write accesses +system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7134650 # DTB read accesses +system.cpu0.dtb.write_accesses 6128392 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11712562 # DTB hits -system.cpu0.dtb.misses 4555 # DTB misses -system.cpu0.dtb.accesses 11717117 # DTB accesses +system.cpu0.dtb.hits 13258735 # DTB hits +system.cpu0.dtb.misses 4307 # DTB misses +system.cpu0.dtb.accesses 13263042 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,8 +1081,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 29557926 # ITB inst hits -system.cpu0.itb.inst_misses 2205 # ITB inst misses +system.cpu0.itb.inst_hits 31182741 # ITB inst hits +system.cpu0.itb.inst_misses 2176 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1044,132 +1091,130 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1181 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1281 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29560131 # ITB inst accesses -system.cpu0.itb.hits 29557926 # DTB hits -system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29560131 # DTB accesses -system.cpu0.numCycles 2388624356 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 31184917 # ITB inst accesses +system.cpu0.itb.hits 31182741 # DTB hits +system.cpu0.itb.misses 2176 # DTB misses +system.cpu0.itb.accesses 31184917 # DTB accesses +system.cpu0.numCycles 5349463018 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28859743 # Number of instructions committed -system.cpu0.committedOps 34624628 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 30439288 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241573 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4174263 # number of instructions that are conditional controls -system.cpu0.num_int_insts 30439288 # number of integer instructions -system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 53589242 # number of times the integer registers were read -system.cpu0.num_int_register_writes 19764786 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 123695766 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 15045730 # number of times the CC registers were written -system.cpu0.num_mem_refs 12225186 # number of memory refs -system.cpu0.num_load_insts 6245915 # Number of load instructions -system.cpu0.num_store_insts 5979271 # Number of store instructions -system.cpu0.num_idle_cycles 2246427873.598119 # Number of idle cycles -system.cpu0.num_busy_cycles 142196482.401881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles -system.cpu0.Branches 5599312 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14563 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 22957352 65.14% 65.18% # Class of executed instruction -system.cpu0.op_class::IntMult 43755 0.12% 65.31% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 692 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.31% # Class of executed instruction -system.cpu0.op_class::MemRead 6245915 17.72% 83.03% # Class of executed instruction -system.cpu0.op_class::MemWrite 5979271 16.97% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30507218 # Number of instructions committed +system.cpu0.committedOps 36803230 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32859018 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses +system.cpu0.num_func_calls 1290775 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3957686 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32859018 # number of integer instructions +system.cpu0.num_fp_insts 5449 # number of float instructions +system.cpu0.num_int_register_reads 60131579 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21902535 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133610661 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14490121 # number of times the CC registers were written +system.cpu0.num_mem_refs 13795466 # number of memory refs +system.cpu0.num_load_insts 7343231 # Number of load instructions +system.cpu0.num_store_insts 6452235 # Number of store instructions +system.cpu0.num_idle_cycles 4898257252.279955 # Number of idle cycles +system.cpu0.num_busy_cycles 451205765.720045 # Number of busy cycles +system.cpu0.not_idle_fraction 0.084346 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.915654 # Percentage of idle cycles +system.cpu0.Branches 5660514 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16321 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 23591543 62.99% 63.03% # Class of executed instruction +system.cpu0.op_class::IntMult 47189 0.13% 63.16% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1591 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.17% # Class of executed instruction +system.cpu0.op_class::MemRead 7343231 19.61% 82.77% # Class of executed instruction +system.cpu0.op_class::MemWrite 6452235 17.23% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 35241548 # Class of executed instruction +system.cpu0.op_class::total 37452110 # Class of executed instruction system.cpu0.kern.inst.arm 0 # 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number of replacements +system.cpu0.icache.tags.tagsinuse 511.465010 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 30812705 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 370018 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 83.273530 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10201796750 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.465010 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998955 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998955 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 269 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 506 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 29983590 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 29983590 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29132228 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29132228 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29132228 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29132228 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29132228 # number of overall hits -system.cpu0.icache.overall_hits::total 29132228 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425681 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425681 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425681 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425681 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425681 # number of overall misses -system.cpu0.icache.overall_misses::total 425681 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5899766682 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5899766682 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5899766682 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5899766682 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5899766682 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5899766682 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29557909 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29557909 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29557909 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29557909 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29557909 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29557909 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014402 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014402 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014402 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014402 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014402 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014402 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13859.595993 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13859.595993 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13859.595993 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13859.595993 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13859.595993 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 62735467 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62735467 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 30812705 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 30812705 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 30812705 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 30812705 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 3209345752 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 3209345752 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 31182724 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 31182724 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 31182724 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 31182724 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 31182724 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 31182724 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011866 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011866 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011866 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11854.323585 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 370019 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 370019 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 370019 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 370019 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 370019 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 370019 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2653955748 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 2653955748 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2653955748 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 2653955748 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2653955748 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 2653955748 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 531257750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 531257750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 531257750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 531257750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011866 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.011866 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011866 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.011866 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7172.485056 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7172.485056 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7172.485056 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 329792 # number of replacements -system.cpu0.dcache.tags.tagsinuse 452.041842 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11239100 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 330304 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.026533 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 671364250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 452.041842 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.882894 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 5080 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1775 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 1943 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3501 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.505615 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.440613 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 17864213 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 17864213 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 4737 # 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number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 4962 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 2520 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 369741 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 232662 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 609885 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 286363 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 286363 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 24017 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 24017 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 11154 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 11154 # 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number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 2520 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 369741 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 390511 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 767734 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.045345 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057937 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.023511 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.207855 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.094155 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000007 # 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number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.903226 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.l2cache.fast_writes 0 # number of fast writes performed +system.cpu0.l2cache.cache_copies 0 # number of cache copies performed +system.cpu0.l2cache.writebacks::writebacks 141584 # number of writebacks +system.cpu0.l2cache.writebacks::total 141584 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 1192 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 751 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 1943 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 493 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 1553670748 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 1786439502 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3322000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2285000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 227161754 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1553670748 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 10450561115 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 12237000617 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 478295250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 176453658508 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 176931953758 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1575154999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1575154999 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 478295250 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 178028813507 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 178507108757 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.204627 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.090970 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.766332 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.766332 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.925498 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.925498 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.149554 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.149554 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.103015 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.045345 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057937 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.020287 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.182366 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.431289 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14764.444444 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15650.684932 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 19133.451133 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20614.142301 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41466.037825 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17949.182124 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17949.182124 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14531.756466 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14531.756466 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 444000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 444000 # 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average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30284.195974 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21816.315828 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41466.037825 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36956.950356 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 355829 # number of replacements +system.cpu0.dcache.tags.tagsinuse 496.967445 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11721464 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 356159 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 32.910762 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 767187000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.967445 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970640 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.970640 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 330 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 330 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.644531 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 24668842 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 24668842 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5548461 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5548461 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5771889 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5771889 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 62661 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11588.774342 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1316,78 +1696,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 305747 # number of writebacks -system.cpu0.dcache.writebacks::total 305747 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 276 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 4042 # 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average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3940.055192 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22819.657713 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22819.657713 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22132.812509 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22132.812509 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 286365 # number of writebacks +system.cpu0.dcache.writebacks::total 286365 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3418 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3418 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2438 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2438 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4772155238 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4772155238 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 185341734990 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 185341734990 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1669232496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1669232496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 187010967486 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 187010967486 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030577 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030577 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.030434 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.030434 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.363553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.363553 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064162 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064162 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.068214 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.068214 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030504 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030504 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034153 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034153 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 9921.312659 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9921.312659 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12883.059772 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12883.059772 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14870.892540 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14870.892540 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14776.624119 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14776.624119 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21331.763984 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21331.763984 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11427.704834 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11427.704834 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11829.277347 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11829.277347 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1395,6 +1779,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.toL2Bus.trans_dist::ReadReq 1907557 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1767698 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 12543 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 12543 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 286363 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 331583 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 53089 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23925 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 60027 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 17 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 171374 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 163301 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 753056 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 3449820 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 6852 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 13348 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4223076 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 23690016 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 48159078 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10080 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 19848 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 71879022 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 631972 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1656253 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.339000 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.473370 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1094784 66.10% 66.10% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 561469 33.90% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 1656253 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1405252745 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 72604500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 563408502 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1726182117 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 4332000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 8386000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1418,25 +1853,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7408792 # DTB read hits -system.cpu1.dtb.read_misses 3640 # DTB read misses -system.cpu1.dtb.write_hits 5825509 # DTB write hits -system.cpu1.dtb.write_misses 1435 # DTB write misses +system.cpu1.dtb.read_hits 6599972 # DTB read hits +system.cpu1.dtb.read_misses 3720 # DTB read misses +system.cpu1.dtb.write_hits 5539858 # DTB write hits +system.cpu1.dtb.write_misses 1581 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1866 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1672 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7412432 # DTB read accesses -system.cpu1.dtb.write_accesses 5826944 # DTB write accesses +system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6603692 # DTB read accesses +system.cpu1.dtb.write_accesses 5541439 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13234301 # DTB hits -system.cpu1.dtb.misses 5075 # DTB misses -system.cpu1.dtb.accesses 13239376 # DTB accesses +system.cpu1.dtb.hits 12139830 # DTB hits +system.cpu1.dtb.misses 5301 # DTB misses +system.cpu1.dtb.accesses 12145131 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1458,8 +1893,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 33190882 # ITB inst hits -system.cpu1.itb.inst_misses 2171 # ITB inst misses +system.cpu1.itb.inst_hits 32728613 # ITB inst hits +system.cpu1.itb.inst_misses 2200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1468,130 +1903,132 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1276 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33193053 # ITB inst accesses -system.cpu1.itb.hits 33190882 # DTB hits -system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33193053 # DTB accesses -system.cpu1.numCycles 2387219429 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 32730813 # ITB inst accesses +system.cpu1.itb.hits 32728613 # DTB hits +system.cpu1.itb.misses 2200 # DTB misses +system.cpu1.itb.accesses 32730813 # DTB accesses +system.cpu1.numCycles 5350361558 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32579955 # Number of instructions committed -system.cpu1.committedOps 38765002 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35167643 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 962341 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3529676 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35167643 # number of integer instructions -system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 64976079 # number of times the integer registers were read -system.cpu1.num_int_register_writes 23977665 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 139669414 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 14465628 # number of times the CC registers were written -system.cpu1.num_mem_refs 13620676 # number of memory refs -system.cpu1.num_load_insts 7578910 # Number of load instructions -system.cpu1.num_store_insts 6041766 # Number of store instructions -system.cpu1.num_idle_cycles 1873842319.884373 # Number of idle cycles -system.cpu1.num_busy_cycles 513377109.115627 # Number of busy cycles -system.cpu1.not_idle_fraction 0.215052 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.784948 # Percentage of idle cycles -system.cpu1.Branches 4944984 # Number of branches fetched -system.cpu1.op_class::No_OpClass 14265 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 25564023 65.13% 65.17% # Class of executed instruction -system.cpu1.op_class::IntMult 50133 0.13% 65.29% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1482 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.30% # Class of executed instruction -system.cpu1.op_class::MemRead 7578910 19.31% 84.61% # Class of executed instruction -system.cpu1.op_class::MemWrite 6041766 15.39% 100.00% # Class of executed instruction +system.cpu1.committedInsts 32086754 # Number of instructions committed +system.cpu1.committedOps 37934299 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 33961237 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses +system.cpu1.num_func_calls 973285 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3888456 # number of instructions that are conditional controls +system.cpu1.num_int_insts 33961237 # number of integer instructions +system.cpu1.num_fp_insts 4436 # number of float instructions +system.cpu1.num_int_register_reads 60527961 # number of times the integer registers were read +system.cpu1.num_int_register_writes 22681940 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 134686779 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 15567897 # number of times the CC registers were written +system.cpu1.num_mem_refs 12531559 # number of memory refs +system.cpu1.num_load_insts 6744563 # Number of load instructions +system.cpu1.num_store_insts 5786996 # Number of store instructions +system.cpu1.num_idle_cycles 5182201093.372063 # Number of idle cycles +system.cpu1.num_busy_cycles 168160464.627937 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031430 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968570 # Percentage of idle cycles +system.cpu1.Branches 5094014 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12501 0.03% 0.03% # Class of executed instruction +system.cpu1.op_class::IntAlu 25826807 67.22% 67.25% # Class of executed instruction +system.cpu1.op_class::IntMult 50699 0.13% 67.38% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 745 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.38% # Class of executed instruction +system.cpu1.op_class::MemRead 6744563 17.55% 84.94% # Class of executed instruction +system.cpu1.op_class::MemWrite 5786996 15.06% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 39250579 # Class of executed instruction +system.cpu1.op_class::total 38422311 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 44258 # number of quiesce instructions executed -system.cpu1.icache.tags.replacements 469324 # number of replacements -system.cpu1.icache.tags.tagsinuse 478.642267 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 32721042 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 469836 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 69.643539 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 93149552500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 478.642267 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.934848 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.934848 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 40934 # number of quiesce instructions executed +system.cpu1.icache.tags.replacements 375227 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.528279 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 32352870 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 375739 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 86.104636 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79843888000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.528279 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973688 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973688 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 456 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 33660714 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 33660714 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 32721042 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32721042 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32721042 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32721042 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32721042 # number of overall hits -system.cpu1.icache.overall_hits::total 32721042 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469836 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469836 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469836 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469836 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469836 # number of overall misses -system.cpu1.icache.overall_misses::total 469836 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6435695955 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6435695955 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6435695955 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6435695955 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6435695955 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6435695955 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33190878 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33190878 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33190878 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33190878 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33190878 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33190878 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014156 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014156 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014156 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014156 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014156 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014156 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13697.749757 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13697.749757 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13697.749757 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13697.749757 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13697.749757 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 65832957 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 65832957 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 32352870 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32352870 # 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miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011480 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011480 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011480 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011480 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8407.834987 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8407.834987 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8407.834987 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8407.834987 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8407.834987 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # 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number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5494111045 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5494111045 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5494111045 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5494111045 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5494111045 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5494111045 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6835750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6835750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6835750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 6835750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014156 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014156 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014156 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014156 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11693.678315 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11693.678315 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11693.678315 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 375739 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 375739 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 375739 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 375739 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 375739 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 375739 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2595414990 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2595414990 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2595414990 # 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mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.011480 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011480 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.011480 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6907.494271 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6907.494271 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6907.494271 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 292234 # number of replacements -system.cpu1.dcache.tags.tagsinuse 471.923930 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11040887 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 292603 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.733335 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 84705826250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.923930 # 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number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 22483 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 22483 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81936 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81936 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82707 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82707 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 10829198 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10829198 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 10851681 # number of overall hits -system.cpu1.dcache.overall_hits::total 10851681 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 144053 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 144053 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 152082 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 152082 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41875 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 41875 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11222 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 11222 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10064 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10064 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 296135 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 296135 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 338010 # number of overall misses -system.cpu1.dcache.overall_misses::total 338010 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1718496498 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6150150 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6150150 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 4975183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4975183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 64358 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 64358 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 93158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 93158 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92771 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92771 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 11125333 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11125333 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 11189691 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11189691 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023423 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023423 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030568 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030568 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.650657 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.650657 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120462 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120462 # 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average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8580.578239 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5167.524940 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5167.524940 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27540.367832 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27540.367832 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24128.477939 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24128.477939 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 3539349 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 109722 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 3291325 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 217 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 15 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 138070 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 329563 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 122650 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15477.303394 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 769651 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 138796 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.545196 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2606454315500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5482.269126 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.040765 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.187836 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 603.787912 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2723.851785 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6655.165971 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.334611 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000735 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000011 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036852 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.166251 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.406199 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.944660 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 7087 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 9051 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 481 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 4215 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 2330 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1744 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5747 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1414 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.432556 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.552429 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 16022455 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 16022455 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 6174 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2268 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 369218 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 169436 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 547096 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 225255 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 225255 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1340 # 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number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 21757 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 13669 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 13669 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 110131 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 110131 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 6442 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2437 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 375595 # 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miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.104344 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.938411 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.938411 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.935255 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.935255 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.213600 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.213600 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041602 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.069348 # 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mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.014936 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.251119 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.102958 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.938411 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.938411 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.935255 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.935255 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # 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average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51048.255365 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16263.259832 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16263.259832 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14141.580726 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14141.580726 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 26663.835843 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 26663.835843 # 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average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51048.255365 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 39643.018101 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # 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Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 22948274 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 22948274 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 6183420 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6183420 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4558750 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4558750 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 19290 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 19290 # 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number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 11064350 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11064350 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11126967 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11126967 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.029391 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.029391 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028749 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.028749 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.691937 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.691937 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135086 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135086 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.152897 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.152897 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029119 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029119 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032849 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.032849 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12279.923714 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12279.923714 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18601.092569 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18601.092569 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18035.734966 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18035.734966 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23209.607987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23209.607987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14927.386504 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14927.386504 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13157.902267 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 13157.902267 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 264973 # number of writebacks -system.cpu1.dcache.writebacks::total 264973 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 379 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 2067 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 2067 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 2446 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 2446 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 2446 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 2446 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143674 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 143674 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150015 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 150015 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 26855 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 26855 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11222 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11222 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10062 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 293689 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 293689 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 320544 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 320544 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1427169251 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1427169251 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6022199670 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6022199670 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 445093004 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 445093004 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73834751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73834751 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31881029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31881029 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7449368921 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7449368921 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7894461925 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7894461925 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168604609000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168604609000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25187299088 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25187299088 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 193791908088 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 193791908088 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023361 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023361 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030153 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030153 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.417275 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.417275 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.120462 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.120462 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108461 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108461 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026398 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026398 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.028646 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.028646 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9933.385658 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9933.385658 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40143.983402 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40143.983402 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16573.934239 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16573.934239 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6579.464534 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6579.464534 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3168.458458 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3168.458458 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25364.821022 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25364.821022 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 24628.325363 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 24628.325363 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 225255 # number of writebacks +system.cpu1.dcache.writebacks::total 225255 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 794 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 794 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 3242 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 3242 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 4036 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 4036 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 4036 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 4036 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 186449 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 186449 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 131695 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 131695 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 27821 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 27821 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12089 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12089 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 13671 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 13671 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 318144 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 318144 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 345965 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 345965 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1916001744 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1916001744 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2027549872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2027549872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 596503999 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 596503999 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 193851000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 193851000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 289002030 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 289002030 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 494000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 494000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3943551616 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3943551616 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4540055615 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4540055615 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 12848996742 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 12848996742 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34213847345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34213847345 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 47062844087 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 47062844087 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029267 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029267 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028058 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028058 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.444304 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.444304 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.135086 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.135086 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.152875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.152875 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028754 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028754 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031092 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.031092 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10276.277931 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10276.277931 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15395.799932 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15395.799932 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21440.782107 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21440.782107 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16035.321367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16035.321367 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21139.787141 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21139.787141 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12395.492657 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12395.492657 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13122.875479 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13122.875479 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1815,6 +2592,57 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 957719 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 715905 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 756547 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 756547 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 225255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 189199 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 53977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23970 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 50977 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 39 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 119927 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 111476 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 751552 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 2675268 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6827 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 16819 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3450466 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 24038516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 40612602 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 9748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 25768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 64686634 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 549743 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1492746 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.338347 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.473147 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 987680 66.17% 66.17% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 505066 33.83% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1492746 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1514414783 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 42402999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 563804260 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 984220768 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 4390000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 10377250 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1831,10 +2659,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 745112259250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 745112259250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 745112259250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 745112259250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1782387791115 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1782387791115 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1782387791115 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 563f1978d..51c016582 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,134 +1,146 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.614581 # Number of seconds simulated -sim_ticks 2614581252500 # Number of ticks simulated -final_tick 2614581252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.614572 # Number of seconds simulated +sim_ticks 2614571564500 # Number of ticks simulated +final_tick 2614571564500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 331710 # Simulator instruction rate (inst/s) -host_op_rate 396174 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14409825510 # Simulator tick rate (ticks/s) -host_mem_usage 433940 # Number of bytes of host memory used -host_seconds 181.44 # Real time elapsed on the host -sim_insts 60186875 # Number of instructions simulated -sim_ops 71883476 # Number of ops (including micro ops) simulated +host_inst_rate 536806 # Simulator instruction rate (inst/s) +host_op_rate 641128 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23319189669 # Simulator tick rate (ticks/s) +host_mem_usage 459056 # Number of bytes of host memory used +host_seconds 112.12 # Real time elapsed on the host +sim_insts 60187274 # Number of instructions simulated +sim_ops 71883961 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9109080 # Number of bytes read from this memory -system.physmem.bytes_read::total 132497440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704520 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3720512 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9109336 # Number of bytes read from this memory +system.physmem.bytes_read::total 132497824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704648 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3720832 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6736584 # Number of bytes written to this memory +system.physmem.bytes_written::total 6736904 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142355 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15495006 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58133 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17222 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142359 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15495012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58138 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812151 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46922769 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812156 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46922943 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3483954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50676352 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1422986 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1153558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2576544 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1422986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46922769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 269508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3484065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50676687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 269508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269508 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1423113 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1153563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2576676 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1423113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46922943 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4637512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53252896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15495006 # Number of read requests accepted -system.physmem.writeReqs 812151 # Number of write requests accepted -system.physmem.readBursts 15495006 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812151 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 991553920 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 126464 # Total number of bytes read from write queue -system.physmem.bytesWritten 6744512 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132497440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6736584 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1976 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706747 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu.inst 269508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4637627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53253363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15495012 # Number of read requests accepted +system.physmem.writeReqs 812156 # Number of write requests accepted +system.physmem.readBursts 15495012 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 812156 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 991563904 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 116864 # Total number of bytes read from write queue +system.physmem.bytesWritten 6748800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132497824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6736904 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1826 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706685 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 968147 # Per bank write bursts +system.physmem.perBankRdBursts::0 968097 # Per bank write bursts system.physmem.perBankRdBursts::1 967810 # Per bank write bursts system.physmem.perBankRdBursts::2 967673 # Per bank write bursts system.physmem.perBankRdBursts::3 967915 # Per bank write bursts -system.physmem.perBankRdBursts::4 974375 # Per bank write bursts -system.physmem.perBankRdBursts::5 968054 # Per bank write bursts +system.physmem.perBankRdBursts::4 974446 # Per bank write bursts +system.physmem.perBankRdBursts::5 968066 # Per bank write bursts system.physmem.perBankRdBursts::6 967653 # Per bank write bursts -system.physmem.perBankRdBursts::7 967480 # Per bank write bursts -system.physmem.perBankRdBursts::8 968459 # Per bank write bursts +system.physmem.perBankRdBursts::7 967482 # Per bank write bursts +system.physmem.perBankRdBursts::8 968460 # Per bank write bursts system.physmem.perBankRdBursts::9 968209 # Per bank write bursts system.physmem.perBankRdBursts::10 967967 # Per bank write bursts system.physmem.perBankRdBursts::11 967960 # Per bank write bursts -system.physmem.perBankRdBursts::12 967929 # Per bank write bursts -system.physmem.perBankRdBursts::13 967878 # Per bank write bursts +system.physmem.perBankRdBursts::12 967930 # Per bank write bursts +system.physmem.perBankRdBursts::13 967880 # Per bank write bursts system.physmem.perBankRdBursts::14 967953 # Per bank write bursts -system.physmem.perBankRdBursts::15 967568 # Per bank write bursts -system.physmem.perBankWrBursts::0 6652 # Per bank write bursts -system.physmem.perBankWrBursts::1 6388 # Per bank write bursts -system.physmem.perBankWrBursts::2 6319 # Per bank write bursts -system.physmem.perBankWrBursts::3 6364 # Per bank write bursts -system.physmem.perBankWrBursts::4 6622 # Per bank write bursts -system.physmem.perBankWrBursts::5 6858 # Per bank write bursts -system.physmem.perBankWrBursts::6 6646 # Per bank write bursts -system.physmem.perBankWrBursts::7 6573 # Per bank write bursts -system.physmem.perBankWrBursts::8 7007 # Per bank write bursts +system.physmem.perBankRdBursts::15 967685 # Per bank write bursts +system.physmem.perBankWrBursts::0 6670 # Per bank write bursts +system.physmem.perBankWrBursts::1 6386 # Per bank write bursts +system.physmem.perBankWrBursts::2 6320 # Per bank write bursts +system.physmem.perBankWrBursts::3 6360 # Per bank write bursts +system.physmem.perBankWrBursts::4 6634 # Per bank write bursts +system.physmem.perBankWrBursts::5 6864 # Per bank write bursts +system.physmem.perBankWrBursts::6 6659 # Per bank write bursts +system.physmem.perBankWrBursts::7 6574 # Per bank write bursts +system.physmem.perBankWrBursts::8 7028 # Per bank write bursts system.physmem.perBankWrBursts::9 6769 # Per bank write bursts system.physmem.perBankWrBursts::10 6571 # Per bank write bursts -system.physmem.perBankWrBursts::11 6647 # Per bank write bursts +system.physmem.perBankWrBursts::11 6645 # Per bank write bursts system.physmem.perBankWrBursts::12 6565 # Per bank write bursts -system.physmem.perBankWrBursts::13 6381 # Per bank write bursts -system.physmem.perBankWrBursts::14 6555 # Per bank write bursts -system.physmem.perBankWrBursts::15 6466 # Per bank write bursts +system.physmem.perBankWrBursts::13 6383 # Per bank write bursts +system.physmem.perBankWrBursts::14 6560 # Per bank write bursts +system.physmem.perBankWrBursts::15 6462 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2614576987500 # Total gap between requests +system.physmem.totGap 2614567301000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6644 # Read request sizes (log2) system.physmem.readPktSize::3 15335434 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152928 # Read request sizes (log2) +system.physmem.readPktSize::6 152934 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58133 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1126497 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 970808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 976433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1092616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 986699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1053397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2722203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2628336 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3415970 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 138177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 115073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 106569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 89 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58138 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1126447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 970731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 976234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1093523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 987097 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1054685 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2721121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2624601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3412795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 139881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 107818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 104436 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18770 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -159,25 +171,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3716 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -208,45 +220,45 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1027240 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.825895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.842120 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 203.903622 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22776 2.22% 2.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22448 2.19% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8450 0.82% 5.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2555 0.25% 5.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2575 0.25% 5.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1819 0.18% 5.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8664 0.84% 6.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 942 0.09% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 957011 93.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1027240 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2531.539869 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116318.280129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6115 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1027284 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.798163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.747967 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.998959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22800 2.22% 2.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22532 2.19% 4.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8422 0.82% 5.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2556 0.25% 5.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2545 0.25% 5.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1785 0.17% 5.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8607 0.84% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 981 0.10% 6.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957056 93.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1027284 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6124 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2529.911822 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116281.505657 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6119 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 3 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6120 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.219444 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.191199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.977796 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2386 38.99% 38.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 19 0.31% 39.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3702 60.49% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 12 0.20% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6120 # Writes before turning the bus around for reads -system.physmem.totQLat 400457727500 # Total ticks spent queuing -system.physmem.totMemAccLat 690952040000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77465150000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25847.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6124 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6124 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.219138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.190607 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.983110 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2397 39.14% 39.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 24 0.39% 39.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3669 59.91% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 32 0.52% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6124 # Writes before turning the bus around for reads +system.physmem.totQLat 400730693500 # Total ticks spent queuing +system.physmem.totMemAccLat 691227931000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77465930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25864.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44597.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 379.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44614.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 379.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.58 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.58 # Average system write bandwidth in MiByte/s @@ -254,74 +266,71 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.98 # Data bus utilization in percentage system.physmem.busUtilRead 2.96 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.67 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing -system.physmem.readRowHits 14482583 # Number of row buffer hits during reads -system.physmem.writeRowHits 88590 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 28.13 # Average write queue length when enqueuing +system.physmem.readRowHits 14482679 # Number of row buffer hits during reads +system.physmem.writeRowHits 88673 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes -system.physmem.avgGap 160333.10 # Average gap between requests +system.physmem.writeRowHitRate 84.07 # Row buffer hit rate for writes +system.physmem.avgGap 160332.39 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2239817846000 # Time in different power states -system.physmem.memoryStateTime::REF 87306440000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2239359524750 # Time in different power states +system.physmem.memoryStateTime::REF 87306180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 287452006500 # Time in different power states +system.physmem.memoryStateTime::ACT 287902801500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54170150 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16546653 # Transaction distribution -system.membus.trans_dist::ReadResp 16546653 # Transaction distribution +system.membus.trans_dist::ReadReq 16546657 # Transaction distribution +system.membus.trans_dist::ReadResp 16546657 # Transaction distribution system.membus.trans_dist::WriteReq 763381 # Transaction distribution system.membus.trans_dist::WriteResp 763381 # Transaction distribution -system.membus.trans_dist::Writeback 58133 # Transaction distribution +system.membus.trans_dist::Writeback 58138 # Transaction distribution system.membus.trans_dist::UpgradeReq 4511 # Transaction distribution system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution -system.membus.trans_dist::ReadExReq 132457 # Transaction distribution -system.membus.trans_dist::ReadExResp 132457 # Transaction distribution +system.membus.trans_dist::ReadExReq 132459 # Transaction distribution +system.membus.trans_dist::ReadExResp 132459 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383082 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3840 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894355 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1894372 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4281306 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34952137 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16550632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18948866 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141632258 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141632258 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1207280500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34952154 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390530 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16551336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18949570 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 141632962 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 215583 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 215583 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 215583 # Request fanout histogram +system.membus.reqLayer0.occupancy 1204828500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3534000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3334000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17916889500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17917176000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4952195664 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4952454428 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37921268500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37912905250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -329,7 +338,6 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 47837076 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16518783 # Transaction distribution system.iobus.trans_dist::ReadResp 16518783 # Transaction distribution system.iobus.trans_dist::WriteReq 8182 # Transaction distribution @@ -361,34 +369,33 @@ system.iobus.pkt_count_system.bridge.master::total 2383082 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 33053930 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 125073922 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390530 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 125073922 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) @@ -435,11 +442,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374900000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38692913500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38695381750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -465,9 +472,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13160128 # DTB read hits +system.cpu.dtb.read_hits 13160242 # DTB read hits system.cpu.dtb.read_misses 7329 # DTB read misses -system.cpu.dtb.write_hits 11227968 # DTB write hits +system.cpu.dtb.write_hits 11228050 # DTB write hits system.cpu.dtb.write_misses 2212 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -478,12 +485,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13167457 # DTB read accesses -system.cpu.dtb.write_accesses 11230180 # DTB write accesses +system.cpu.dtb.read_accesses 13167571 # DTB read accesses +system.cpu.dtb.write_accesses 11230262 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 24388096 # DTB hits +system.cpu.dtb.hits 24388292 # DTB hits system.cpu.dtb.misses 9541 # DTB misses -system.cpu.dtb.accesses 24397637 # DTB accesses +system.cpu.dtb.accesses 24397833 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -505,7 +512,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 61480692 # ITB inst hits +system.cpu.itb.inst_hits 61481095 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -522,37 +529,37 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61485163 # ITB inst accesses -system.cpu.itb.hits 61480692 # DTB hits +system.cpu.itb.inst_accesses 61485566 # ITB inst accesses +system.cpu.itb.hits 61481095 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61485163 # DTB accesses -system.cpu.numCycles 5229162505 # number of cpu cycles simulated +system.cpu.itb.accesses 61485566 # DTB accesses +system.cpu.numCycles 5229143129 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60186875 # Number of instructions committed -system.cpu.committedOps 71883476 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 64248071 # Number of integer alu accesses +system.cpu.committedInsts 60187274 # Number of instructions committed +system.cpu.committedOps 71883961 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 64248492 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139776 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7549008 # number of instructions that are conditional controls -system.cpu.num_int_insts 64248071 # number of integer instructions +system.cpu.num_func_calls 2139801 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7549047 # number of instructions that are conditional controls +system.cpu.num_int_insts 64248492 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 116109819 # number of times the integer registers were read -system.cpu.num_int_register_writes 42862791 # number of times the integer registers were written +system.cpu.num_int_register_reads 116110622 # number of times the integer registers were read +system.cpu.num_int_register_writes 42863098 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_cc_register_reads 257767219 # number of times the CC registers were read -system.cpu.num_cc_register_writes 28995131 # number of times the CC registers were written -system.cpu.num_mem_refs 25244051 # number of memory refs -system.cpu.num_load_insts 13512687 # Number of load instructions -system.cpu.num_store_insts 11731364 # Number of store instructions -system.cpu.num_idle_cycles 4584182254.578246 # Number of idle cycles -system.cpu.num_busy_cycles 644980250.421753 # Number of busy cycles -system.cpu.not_idle_fraction 0.123343 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.876657 # Percentage of idle cycles -system.cpu.Branches 10306559 # Number of branches fetched +system.cpu.num_cc_register_reads 257769006 # number of times the CC registers were read +system.cpu.num_cc_register_writes 28995258 # number of times the CC registers were written +system.cpu.num_mem_refs 25244235 # number of memory refs +system.cpu.num_load_insts 13512788 # Number of load instructions +system.cpu.num_store_insts 11731447 # Number of store instructions +system.cpu.num_idle_cycles 4584209782.584247 # Number of idle cycles +system.cpu.num_busy_cycles 644933346.415753 # Number of busy cycles +system.cpu.not_idle_fraction 0.123334 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.876666 # Percentage of idle cycles +system.cpu.Branches 10306630 # Number of branches fetched system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 47576706 65.23% 65.27% # Class of executed instruction +system.cpu.op_class::IntAlu 47577014 65.23% 65.27% # Class of executed instruction system.cpu.op_class::IntMult 87551 0.12% 65.39% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction @@ -581,20 +588,20 @@ system.cpu.op_class::SimdFloatMisc 2109 0.00% 65.39% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction -system.cpu.op_class::MemRead 13512687 18.53% 83.92% # Class of executed instruction -system.cpu.op_class::MemWrite 11731364 16.08% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13512788 18.53% 83.92% # Class of executed instruction +system.cpu.op_class::MemWrite 11731447 16.08% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 72938935 # Class of executed instruction +system.cpu.op_class::total 72939427 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83001 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 855859 # number of replacements -system.cpu.icache.tags.tagsinuse 510.877209 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 60624321 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 856371 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.792123 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 19627747250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.877209 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 83004 # number of quiesce instructions executed +system.cpu.icache.tags.replacements 855897 # number of replacements +system.cpu.icache.tags.tagsinuse 510.877214 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 60624686 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 856409 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.789408 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19623933250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.877214 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.997807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -603,44 +610,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 194 system.cpu.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 62337063 # Number of tag accesses -system.cpu.icache.tags.data_accesses 62337063 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 60624321 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60624321 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60624321 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60624321 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60624321 # number of overall hits -system.cpu.icache.overall_hits::total 60624321 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856371 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856371 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856371 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856371 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856371 # number of overall misses -system.cpu.icache.overall_misses::total 856371 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11763954000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11763954000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11763954000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11763954000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11763954000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11763954000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61480692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61480692 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61480692 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61480692 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61480692 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61480692 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013929 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013929 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013929 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013929 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013929 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013929 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13736.983153 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13736.983153 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13736.983153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13736.983153 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13736.983153 # average overall miss latency +system.cpu.icache.tags.tag_accesses 62337504 # Number of tag accesses +system.cpu.icache.tags.data_accesses 62337504 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60624686 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60624686 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60624686 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60624686 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60624686 # number of overall hits +system.cpu.icache.overall_hits::total 60624686 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 856409 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 856409 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 856409 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 856409 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 856409 # number of overall misses +system.cpu.icache.overall_misses::total 856409 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11766778500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11766778500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11766778500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11766778500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11766778500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11766778500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61481095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61481095 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61481095 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61481095 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61481095 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61481095 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013930 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013930 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013930 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013930 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13739.671699 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13739.671699 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13739.671699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13739.671699 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13739.671699 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,186 +656,186 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856371 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856371 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856371 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856371 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856371 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856371 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10047194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10047194000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10047194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10047194000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10047194000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10047194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856409 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -932,94 +939,94 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 625842 # number of replacements +system.cpu.dcache.tags.replacements 625894 # number of replacements system.cpu.dcache.tags.tagsinuse 511.875658 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21786000 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 626354 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.782248 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21786154 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 626406 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.779606 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 668864250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.875658 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999757 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 90403758 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 90403758 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11249339 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11249339 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9965366 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9965366 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 84253 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 84253 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236457 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236457 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247663 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247663 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21214705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21214705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21298958 # number of overall hits -system.cpu.dcache.overall_hits::total 21298958 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 294663 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 294663 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 255297 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 255297 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 100106 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 100106 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11207 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11207 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 549960 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 549960 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 650066 # number of overall misses -system.cpu.dcache.overall_misses::total 650066 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4040384999 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4040384999 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11533122261 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11533122261 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 155182000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15573507260 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15573507260 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15573507260 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15573507260 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 11544002 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11544002 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10220663 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10220663 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 184359 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 184359 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247664 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247664 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247663 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247663 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21764665 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21764665 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21949024 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21949024 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025525 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025525 # miss rate for ReadReq accesses +system.cpu.dcache.tags.tag_accesses 90404594 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 90404594 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11249411 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11249411 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9965441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9965441 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 84252 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 84252 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236461 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236461 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247668 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247668 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21214852 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21214852 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21299104 # number of overall hits +system.cpu.dcache.overall_hits::total 21299104 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 294699 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 294699 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 255299 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 255299 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 100108 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 100108 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11208 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11208 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 549998 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 549998 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 650106 # number of overall misses +system.cpu.dcache.overall_misses::total 650106 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4039018749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4039018749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11552022511 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11552022511 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 154983250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 154983250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15591041260 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15591041260 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15591041260 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15591041260 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 11544110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 11544110 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10220740 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10220740 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 184360 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 184360 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247669 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247669 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247668 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247668 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21764850 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21764850 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21949210 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21949210 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025528 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025528 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024979 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024979 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.542995 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.542995 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045251 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045251 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025268 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029617 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029617 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13711.884421 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13711.884421 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45175.314481 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45175.314481 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13846.881413 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13846.881413 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28317.527202 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28317.527202 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23956.809401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23956.809401 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.543003 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.543003 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045254 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045254 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025270 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025270 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029619 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029619 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13705.573310 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13705.573310 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45248.992401 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45248.992401 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13827.913098 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13827.913098 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28347.450827 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28347.450827 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23982.306362 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23982.306362 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1028,70 +1035,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs 58 system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 594981 # number of writebacks -system.cpu.dcache.writebacks::total 594981 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 534 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 534 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4836 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 4836 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 5370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 5370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 5370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 5370 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294129 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 294129 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250461 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250461 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 73479 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 73479 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11207 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11207 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 544590 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 544590 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618069 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618069 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3445567250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3445567250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10763005489 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10763005489 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1228271500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1228271500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132710000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132710000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14208572739 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14208572739 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15436844239 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15436844239 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182058544250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182058544250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242551425 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242551425 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208301095675 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208301095675 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025479 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398565 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398565 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045251 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045251 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025022 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025022 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11714.476471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11714.476471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42972.780149 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42972.780149 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16715.952857 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16715.952857 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11841.706077 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11841.706077 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26090.403311 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26090.403311 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24975.923787 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24975.923787 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 595027 # number of writebacks +system.cpu.dcache.writebacks::total 595027 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 533 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 533 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 4827 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 4827 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 5360 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 5360 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 5360 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 5360 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 294166 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 294166 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250472 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250472 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 73481 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 73481 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11208 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11208 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 544638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 544638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618119 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618119 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3444363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3444363000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10784804239 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10784804239 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1224587250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1224587250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132510750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132510750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14229167239 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14229167239 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15453754489 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15453754489 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182056011250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182056011250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26242438939 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26242438939 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208298450189 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208298450189 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025482 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024506 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.398573 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.398573 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.045254 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025024 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025024 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11708.909255 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11708.909255 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43057.923596 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43057.923596 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16665.359072 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16665.359072 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11822.872056 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11822.872056 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26125.917103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26125.917103 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25001.261066 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25001.261066 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1099,33 +1106,46 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 52981595 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2453579 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2453579 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2453657 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2453657 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763381 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763381 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 594981 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2922 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247539 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247539 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724389 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748549 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12041 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::Writeback 595027 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 247551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 247551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1724466 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5748697 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12042 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 26252 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7511231 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54730908 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83579878 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12460 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 138353418 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 138353418 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 171268 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3007873000 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count::total 7511457 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54733404 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83586150 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 30172 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 138362190 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 18590 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2108398 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2108398 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2108398 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3007986500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1294746250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1294797750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533153086 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2533255572 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) @@ -1147,10 +1167,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1760059764500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760059764500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1760059764500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1760318460750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1760318460750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1760318460750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index a9cd1b1ac..5818937f9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.321351 # Number of seconds simulated -sim_ticks 2321351025500 # Number of ticks simulated -final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.321335 # Number of seconds simulated +sim_ticks 2321335404000 # Number of ticks simulated +final_tick 2321335404000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 709541 # Simulator instruction rate (inst/s) -host_op_rate 854435 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27266672116 # Simulator tick rate (ticks/s) -host_mem_usage 431868 # Number of bytes of host memory used -host_seconds 85.14 # Real time elapsed on the host +host_inst_rate 1185543 # Simulator instruction rate (inst/s) +host_op_rate 1427641 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45558461303 # Simulator tick rate (ticks/s) +host_mem_usage 457752 # Number of bytes of host memory used +host_seconds 50.95 # Real time elapsed on the host sim_insts 60406834 # Number of instructions simulated sim_ops 72742429 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -16,54 +16,54 @@ system.clk_domain.clock 1000 # Cl system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 508168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5844952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 197248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 3227072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 508104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5777624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 197312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3294400 # Number of bytes read from this memory system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 508168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 197248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 508104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 197312 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3703808 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1462736 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1553080 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1461532 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1554284 # Number of bytes written to this memory system.physmem.bytes_written::total 6719624 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14152 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 91353 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3082 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 50423 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14151 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 90301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3083 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 51475 # Number of read requests responded to by this memory system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 57872 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 365684 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 388270 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 365383 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 388571 # Number of write requests responded to by this memory system.physmem.num_writes::total 811826 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47429803 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 83 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 218910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2517910 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 84971 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1390170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 218910 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 84971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1595540 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 630123 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 669041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2894704 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1595540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 218884 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2488923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 84999 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1419183 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51641930 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 218884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 84999 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 303884 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1595551 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 629608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 669565 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2894723 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1595551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47429803 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 83 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 218910 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3148032 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 84971 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2059211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54536286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 218884 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3118531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 84999 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2088748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54536653 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -76,30 +76,66 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55568819 # Throughput (bytes/s) -system.membus.data_through_bus 128994735 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 14973628 # Transaction distribution +system.membus.trans_dist::ReadResp 14973628 # Transaction distribution +system.membus.trans_dist::WriteReq 763122 # Transaction distribution +system.membus.trans_dist::WriteResp 763122 # Transaction distribution +system.membus.trans_dist::Writeback 57872 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4519 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4519 # Transaction distribution +system.membus.trans_dist::ReadExReq 131877 # Transaction distribution +system.membus.trans_dist::ReadExResp 131877 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382824 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3360 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 27525120 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31804164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390127 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 6720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16497384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18894255 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 128994735 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214752 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 214752 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 214752 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62250 # number of replacements -system.l2c.tags.tagsinuse 50005.872632 # Cycle average of tags in use -system.l2c.tags.total_refs 1678480 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 50005.858036 # Cycle average of tags in use +system.l2c.tags.total_refs 1678527 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 127635 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.150625 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36900.828862 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993863 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993971 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4874.093087 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3539.587837 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2140.383073 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2548.991939 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.563062 # Average percentage of cache occupancy +system.l2c.tags.avg_refs 13.150993 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2306275686000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36902.743708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.993864 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.993972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4873.119904 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3553.057866 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2141.364810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2533.583912 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.563091 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074373 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.054010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.032660 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.038895 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074358 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.054215 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032675 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.038659 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.763029 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id @@ -107,136 +143,136 @@ system.l2c.tags.age_task_id_blocks_1023::4 2 # system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9282 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52127 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17104797 # Number of tag accesses -system.l2c.tags.data_accesses 17104797 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8775 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3263 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 451755 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188951 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5151 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2105 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 387038 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 177833 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1224871 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 592686 # number of Writeback hits -system.l2c.Writeback_hits::total 592686 # number of Writeback hits +system.l2c.tags.tag_accesses 17105211 # Number of tag accesses +system.l2c.tags.data_accesses 17105211 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8799 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3276 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 451004 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 189163 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5176 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 2130 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 387778 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 177603 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1224929 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592674 # number of Writeback hits +system.l2c.Writeback_hits::total 592674 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 10 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 62028 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 51680 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113708 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8775 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3263 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 451755 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 250979 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5151 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2105 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 387038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 229513 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338579 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8775 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3263 # number of overall hits -system.l2c.overall_hits::cpu0.inst 451755 # number of overall hits -system.l2c.overall_hits::cpu0.data 250979 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5151 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2105 # number of overall hits -system.l2c.overall_hits::cpu1.inst 387038 # number of overall hits -system.l2c.overall_hits::cpu1.data 229513 # number of overall hits -system.l2c.overall_hits::total 1338579 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 62080 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 51632 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113712 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8799 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3276 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 451004 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 251243 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 2130 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 387778 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 229235 # number of demand (read+write) hits +system.l2c.demand_hits::total 1338641 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8799 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3276 # number of overall hits +system.l2c.overall_hits::cpu0.inst 451004 # number of overall hits +system.l2c.overall_hits::cpu0.data 251243 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5176 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 2130 # number of overall hits +system.l2c.overall_hits::cpu1.inst 387778 # number of overall hits +system.l2c.overall_hits::cpu1.data 229235 # number of overall hits +system.l2c.overall_hits::total 1338641 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7526 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6094 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3082 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 3778 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20485 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7525 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6105 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3083 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3766 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20484 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1505 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1412 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2917 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 86064 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 47413 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133477 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 85002 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 48477 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133479 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7526 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 92158 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3082 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 51191 # number of demand (read+write) misses -system.l2c.demand_misses::total 153962 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7525 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 91107 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3083 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 52243 # number of demand (read+write) misses +system.l2c.demand_misses::total 153963 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7526 # number of overall misses -system.l2c.overall_misses::cpu0.data 92158 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3082 # number of overall misses -system.l2c.overall_misses::cpu1.data 51191 # number of overall misses -system.l2c.overall_misses::total 153962 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8777 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3266 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 459281 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 195045 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5151 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2105 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 390120 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 181611 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1245356 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 592686 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 592686 # number of Writeback accesses(hits+misses) +system.l2c.overall_misses::cpu0.inst 7525 # number of overall misses +system.l2c.overall_misses::cpu0.data 91107 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3083 # number of overall misses +system.l2c.overall_misses::cpu1.data 52243 # number of overall misses +system.l2c.overall_misses::total 153963 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8801 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3279 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 458529 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 195268 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5176 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 2130 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 390861 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 181369 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1245413 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592674 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592674 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1521 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1422 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 148092 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 99093 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247185 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8777 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3266 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 459281 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 343137 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5151 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2105 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 390120 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 280704 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1492541 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8777 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3266 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 459281 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 343137 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5151 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2105 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 390120 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 280704 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1492541 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000919 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.016386 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.031244 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007900 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.020803 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016449 # miss rate for ReadReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 147082 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 100109 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247191 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8801 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3279 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 458529 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 342350 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5176 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 2130 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 390861 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 281478 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1492604 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8801 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3279 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 458529 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 342350 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5176 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 2130 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 390861 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 281478 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1492604 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000227 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000915 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.016411 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.031265 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007888 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.020764 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016448 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989481 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992968 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.581152 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.478470 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539988 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000919 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.016386 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.268575 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007900 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.182366 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103154 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000228 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.016386 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.268575 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007900 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.182366 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103154 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.577923 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.484242 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539983 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000227 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000915 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.016411 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.266122 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007888 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.185602 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103151 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000227 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000915 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.016411 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.266122 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007888 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.185602 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103151 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -254,11 +290,99 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 59409488 # Throughput (bytes/s) -system.toL2Bus.data_through_bus 137910275 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iobus.throughput 48459111 # Throughput (bytes/s) -system.iobus.data_through_bus 112490607 # Total data (bytes) +system.toL2Bus.trans_dist::ReadReq 2455233 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2455233 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763122 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763122 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 592674 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2943 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2943 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247191 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247191 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1715294 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5740366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22916 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51076 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7529652 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54491548 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83268947 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 45832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 137908479 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 0 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2107457 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2107457 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2107457 # Request fanout histogram +system.iobus.trans_dist::ReadReq 14945841 # Transaction distribution +system.iobus.trans_dist::ReadResp 14945841 # Transaction distribution +system.iobus.trans_dist::WriteReq 8131 # Transaction distribution +system.iobus.trans_dist::WriteResp 8131 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7900 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 476 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 984 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382824 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 27525120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 29907944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39247 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15800 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 952 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 1968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390127 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 110100480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 112490607 # Cumulative packet size per connected master and slave (bytes) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -282,25 +406,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6811742 # DTB read hits -system.cpu0.dtb.read_misses 6183 # DTB read misses -system.cpu0.dtb.write_hits 6269363 # DTB write hits -system.cpu0.dtb.write_misses 2047 # DTB write misses +system.cpu0.dtb.read_hits 6816435 # DTB read hits +system.cpu0.dtb.read_misses 6211 # DTB read misses +system.cpu0.dtb.write_hits 6254825 # DTB write hits +system.cpu0.dtb.write_misses 2049 # DTB write misses system.cpu0.dtb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5527 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5541 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 120 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 235 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6817925 # DTB read accesses -system.cpu0.dtb.write_accesses 6271410 # DTB write accesses +system.cpu0.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6822646 # DTB read accesses +system.cpu0.dtb.write_accesses 6256874 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13081105 # DTB hits -system.cpu0.dtb.misses 8230 # DTB misses -system.cpu0.dtb.accesses 13089335 # DTB accesses +system.cpu0.dtb.hits 13071260 # DTB hits +system.cpu0.dtb.misses 8260 # DTB misses +system.cpu0.dtb.accesses 13079520 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -322,143 +446,143 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32133466 # ITB inst hits -system.cpu0.itb.inst_misses 3581 # ITB inst misses +system.cpu0.itb.inst_hits 32152502 # ITB inst hits +system.cpu0.itb.inst_misses 3598 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 2324 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 763 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 758 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2662 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2674 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32137047 # ITB inst accesses -system.cpu0.itb.hits 32133466 # DTB hits -system.cpu0.itb.misses 3581 # DTB misses -system.cpu0.itb.accesses 32137047 # DTB accesses -system.cpu0.numCycles 4608021079 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32156100 # ITB inst accesses +system.cpu0.itb.hits 32152502 # DTB hits +system.cpu0.itb.misses 3598 # DTB misses +system.cpu0.itb.accesses 32156100 # DTB accesses +system.cpu0.numCycles 4610022066 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31639227 # Number of instructions committed -system.cpu0.committedOps 38587883 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34004805 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5482 # Number of float alu accesses -system.cpu0.num_func_calls 1192523 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4010781 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34004805 # number of integer instructions -system.cpu0.num_fp_insts 5482 # number of float instructions -system.cpu0.num_int_register_reads 62290177 # number of times the integer registers were read -system.cpu0.num_int_register_writes 22551825 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3925 # number of times the floating registers were read +system.cpu0.committedInsts 31655881 # Number of instructions committed +system.cpu0.committedOps 38589756 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34002307 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5498 # Number of float alu accesses +system.cpu0.num_func_calls 1192858 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4013764 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34002307 # number of integer instructions +system.cpu0.num_fp_insts 5498 # number of float instructions +system.cpu0.num_int_register_reads 62271464 # number of times the integer registers were read +system.cpu0.num_int_register_writes 22558612 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3941 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1558 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 115496065 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 15262729 # number of times the CC registers were written -system.cpu0.num_mem_refs 13528824 # number of memory refs -system.cpu0.num_load_insts 6988108 # Number of load instructions -system.cpu0.num_store_insts 6540716 # Number of store instructions -system.cpu0.num_idle_cycles 4534732444.570566 # Number of idle cycles -system.cpu0.num_busy_cycles 73288634.429434 # Number of busy cycles -system.cpu0.not_idle_fraction 0.015905 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.984095 # Percentage of idle cycles -system.cpu0.Branches 5541899 # Number of branches fetched -system.cpu0.op_class::No_OpClass 16090 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 25070156 64.84% 64.89% # Class of executed instruction -system.cpu0.op_class::IntMult 45827 0.12% 65.00% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.00% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1368 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.01% # Class of executed instruction -system.cpu0.op_class::MemRead 6988108 18.07% 83.08% # Class of executed instruction -system.cpu0.op_class::MemWrite 6540716 16.92% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 115497170 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 15275707 # number of times the CC registers were written +system.cpu0.num_mem_refs 13519126 # number of memory refs +system.cpu0.num_load_insts 6992673 # Number of load instructions +system.cpu0.num_store_insts 6526453 # Number of store instructions +system.cpu0.num_idle_cycles 4538759726.926458 # Number of idle cycles +system.cpu0.num_busy_cycles 71262339.073542 # Number of busy cycles +system.cpu0.not_idle_fraction 0.015458 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.984542 # Percentage of idle cycles +system.cpu0.Branches 5545179 # Number of branches fetched +system.cpu0.op_class::No_OpClass 16079 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 25081623 64.87% 64.91% # Class of executed instruction +system.cpu0.op_class::IntMult 45922 0.12% 65.03% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1365 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.03% # Class of executed instruction +system.cpu0.op_class::MemRead 6992673 18.09% 83.12% # Class of executed instruction +system.cpu0.op_class::MemWrite 6526453 16.88% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 38662265 # Class of executed instruction +system.cpu0.op_class::total 38664115 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82781 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 850515 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60581740 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.344221 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.345372 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871766 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127628 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 850504 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.689630 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60581751 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 851016 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 71.187558 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 5451547500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 446.338382 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.351248 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.871755 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.127639 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62283794 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62283794 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31676072 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 28905668 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60581740 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31676072 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 28905668 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60581740 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31676072 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 28905668 # number of overall hits -system.cpu0.icache.overall_hits::total 60581740 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 460107 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 390920 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 851027 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 460107 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 390920 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 851027 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 460107 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 390920 # number of overall misses -system.cpu0.icache.overall_misses::total 851027 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32136179 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 29296588 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.tags.tag_accesses 62283783 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62283783 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31695864 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 28885887 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60581751 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31695864 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 28885887 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60581751 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31695864 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 28885887 # number of overall hits +system.cpu0.icache.overall_hits::total 60581751 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 459362 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 391654 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 851016 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 459362 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 391654 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 851016 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 459362 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 391654 # number of overall misses +system.cpu0.icache.overall_misses::total 851016 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32155226 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 29277541 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32136179 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 29296588 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 32155226 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 29277541 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32136179 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 29296588 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32155226 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 29277541 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014317 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013344 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014286 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.013377 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014317 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013344 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014286 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.013377 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013853 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014317 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013344 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014286 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.013377 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013853 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -469,101 +593,101 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 623329 # number of replacements +system.cpu0.dcache.tags.replacements 623316 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21798515 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 34.942421 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21798519 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 623828 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.943156 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.974436 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 58.022582 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.886669 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.113325 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 453.972290 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 58.024728 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.886665 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.113330 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 90313265 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 90313265 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5835707 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 5404504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11240211 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5610278 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4351033 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9961311 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 52098 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58749 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 110847 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136238 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 99769 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236007 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142767 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 104429 # number of StoreCondReq hits +system.cpu0.dcache.tags.tag_accesses 90313216 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 90313216 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5840103 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 5400119 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11240222 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5597078 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4364227 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9961305 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 52143 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58700 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 110843 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 136250 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 99760 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236010 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142749 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 104447 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11445985 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 9755537 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21201522 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11498083 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 9814286 # number of overall hits -system.cpu0.dcache.overall_hits::total 21312369 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 155593 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 136452 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 292045 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 149613 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 100515 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250128 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 32922 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 40499 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 73421 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6530 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4660 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11190 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 305206 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 236967 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 542173 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 338128 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 277466 # number of overall misses -system.cpu0.dcache.overall_misses::total 615594 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5991300 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 5540956 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5759891 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4451548 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_hits::cpu0.data 11437181 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 9764346 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21201527 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11489324 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 9823046 # number of overall hits +system.cpu0.dcache.overall_hits::total 21312370 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 155804 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 136229 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 292033 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 148603 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 101531 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 250134 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 32964 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 40453 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 73417 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6500 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 4687 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11187 # number of LoadLockedReq misses +system.cpu0.dcache.demand_misses::cpu0.data 304407 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 237760 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 542167 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 337371 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 278213 # number of overall misses +system.cpu0.dcache.overall_misses::total 615584 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5995907 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 5536348 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 11532255 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5745681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 4465758 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 85020 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 99248 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 184268 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142768 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 104429 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 85107 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 99153 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 184260 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142750 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 104447 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142767 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 104429 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142749 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 104447 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11751191 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 9992504 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11836211 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10091752 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21927963 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025970 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.024626 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.025324 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025975 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022580 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11741588 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 10002106 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21743694 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11826695 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 10101259 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21927954 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025985 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.024606 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025863 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.022735 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.387227 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.408059 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.398447 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045739 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044624 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045268 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025972 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023714 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.024935 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028567 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027494 # miss rate for overall accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.387324 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.407986 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.398442 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045534 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044874 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025926 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023771 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028526 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027542 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -573,8 +697,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 592686 # number of writebacks -system.cpu0.dcache.writebacks::total 592686 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 592674 # number of writebacks +system.cpu0.dcache.writebacks::total 592674 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -599,25 +723,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6327054 # DTB read hits -system.cpu1.dtb.read_misses 4532 # DTB read misses -system.cpu1.dtb.write_hits 4945852 # DTB write hits -system.cpu1.dtb.write_misses 1126 # DTB write misses +system.cpu1.dtb.read_hits 6322311 # DTB read hits +system.cpu1.dtb.read_misses 4545 # DTB read misses +system.cpu1.dtb.write_hits 4960387 # DTB write hits +system.cpu1.dtb.write_misses 1127 # DTB write misses system.cpu1.dtb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3028 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 3056 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 87 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6331586 # DTB read accesses -system.cpu1.dtb.write_accesses 4946978 # DTB write accesses +system.cpu1.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6326856 # DTB read accesses +system.cpu1.dtb.write_accesses 4961514 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 11272906 # DTB hits -system.cpu1.dtb.misses 5658 # DTB misses -system.cpu1.dtb.accesses 11278564 # DTB accesses +system.cpu1.dtb.hits 11282698 # DTB hits +system.cpu1.dtb.misses 5672 # DTB misses +system.cpu1.dtb.accesses 11288370 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -639,87 +763,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 29294834 # ITB inst hits -system.cpu1.itb.inst_misses 2597 # ITB inst misses +system.cpu1.itb.inst_hits 29275767 # ITB inst hits +system.cpu1.itb.inst_misses 2611 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2320 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 681 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1660 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1680 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 29297431 # ITB inst accesses -system.cpu1.itb.hits 29294834 # DTB hits -system.cpu1.itb.misses 2597 # DTB misses -system.cpu1.itb.accesses 29297431 # DTB accesses -system.cpu1.numCycles 141054432 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 29278378 # ITB inst accesses +system.cpu1.itb.hits 29275767 # DTB hits +system.cpu1.itb.misses 2611 # DTB misses +system.cpu1.itb.accesses 29278378 # DTB accesses +system.cpu1.numCycles 143033518 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 28767607 # Number of instructions committed -system.cpu1.committedOps 34154546 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 30186625 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4787 # Number of float alu accesses -system.cpu1.num_func_calls 943239 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3534203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30186625 # number of integer instructions -system.cpu1.num_fp_insts 4787 # number of float instructions -system.cpu1.num_int_register_reads 54137170 # number of times the integer registers were read -system.cpu1.num_int_register_writes 20266282 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3568 # number of times the floating registers were read +system.cpu1.committedInsts 28750953 # Number of instructions committed +system.cpu1.committedOps 34152673 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 30189123 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4771 # Number of float alu accesses +system.cpu1.num_func_calls 942904 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3531220 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30189123 # number of integer instructions +system.cpu1.num_fp_insts 4771 # number of float instructions +system.cpu1.num_int_register_reads 54155883 # number of times the integer registers were read +system.cpu1.num_int_register_writes 20259495 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3552 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1222 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 102073939 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 13715012 # number of times the CC registers were written -system.cpu1.num_mem_refs 11692450 # number of memory refs -system.cpu1.num_load_insts 6511829 # Number of load instructions -system.cpu1.num_store_insts 5180621 # Number of store instructions -system.cpu1.num_idle_cycles 138966556.858503 # Number of idle cycles -system.cpu1.num_busy_cycles 2087875.141497 # Number of busy cycles -system.cpu1.not_idle_fraction 0.014802 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.985198 # Percentage of idle cycles -system.cpu1.Branches 4756618 # Number of branches fetched -system.cpu1.op_class::No_OpClass 12428 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 22465876 65.66% 65.70% # Class of executed instruction -system.cpu1.op_class::IntMult 41944 0.12% 65.82% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 745 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.82% # Class of executed instruction -system.cpu1.op_class::MemRead 6511829 19.03% 84.86% # Class of executed instruction -system.cpu1.op_class::MemWrite 5180621 15.14% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 102072834 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 13702034 # number of times the CC registers were written +system.cpu1.num_mem_refs 11702148 # number of memory refs +system.cpu1.num_load_insts 6507264 # Number of load instructions +system.cpu1.num_store_insts 5194884 # Number of store instructions +system.cpu1.num_idle_cycles 140979209.208319 # Number of idle cycles +system.cpu1.num_busy_cycles 2054308.791681 # Number of busy cycles +system.cpu1.not_idle_fraction 0.014362 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.985638 # Percentage of idle cycles +system.cpu1.Branches 4753338 # Number of branches fetched +system.cpu1.op_class::No_OpClass 12439 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 22454409 65.63% 65.67% # Class of executed instruction +system.cpu1.op_class::IntMult 41849 0.12% 65.79% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 748 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.79% # Class of executed instruction +system.cpu1.op_class::MemRead 6507264 19.02% 84.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 5194884 15.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 34213443 # Class of executed instruction +system.cpu1.op_class::total 34211593 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index b0c415fa9..ec6df0068 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -1,89 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.112126 # Number of seconds simulated -sim_ticks 5112125984500 # Number of ticks simulated -final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.112127 # Number of seconds simulated +sim_ticks 5112126720000 # Number of ticks simulated +final_tick 5112126720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1274105 # Simulator instruction rate (inst/s) -host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32578287771 # Simulator tick rate (ticks/s) -host_mem_usage 593532 # Number of bytes of host memory used -host_seconds 156.92 # Real time elapsed on the host -sim_insts 199930130 # Number of instructions simulated -sim_ops 409344539 # Number of ops (including micro ops) simulated +host_inst_rate 1627732 # Simulator instruction rate (inst/s) +host_op_rate 3332615 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41616843658 # Simulator tick rate (ticks/s) +host_mem_usage 647148 # Number of bytes of host memory used +host_seconds 122.84 # Real time elapsed on the host +sim_insts 199947158 # Number of instructions simulated +sim_ops 409371517 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory -system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 852352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10669504 # Number of bytes read from this memory +system.physmem.bytes_read::total 11550592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 852352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 852352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6285632 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory +system.physmem.bytes_written::total 9275712 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 13318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 166711 # Number of read requests responded to by this memory +system.physmem.num_reads::total 180478 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 98213 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory +system.physmem.num_writes::total 144933 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 166731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2087097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2259449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 166731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 166731 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1229553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 584899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1814453 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1229553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 590445 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9050072 # Throughput (bytes/s) -system.membus.data_through_bus 46265107 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use +system.physmem.bw_total::cpu.inst 166731 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2087097 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4073902 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 13903648 # Transaction distribution +system.membus.trans_dist::ReadResp 13903648 # Transaction distribution +system.membus.trans_dist::WriteReq 13796 # Transaction distribution +system.membus.trans_dist::WriteResp 13796 # Transaction distribution +system.membus.trans_dist::Writeback 98213 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2521 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2092 # Transaction distribution +system.membus.trans_dist::ReadExReq 134490 # Transaction distribution +system.membus.trans_dist::ReadExResp 134485 # Transaction distribution +system.membus.trans_dist::MessageReq 1696 # Transaction distribution +system.membus.trans_dist::MessageResp 1696 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20043728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28204873 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28303521 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10027982 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17807872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43232339 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46287315 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 328402 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 328402 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 328402 # Request fanout histogram +system.iocache.tags.replacements 47573 # number of replacements +system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 4994846765009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428616 # Number of tag accesses -system.iocache.tags.data_accesses 428616 # Number of data accesses +system.iocache.tags.tag_accesses 428652 # Number of tag accesses +system.iocache.tags.data_accesses 428652 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses -system.iocache.demand_misses::total 904 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses -system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses +system.iocache.ReadReq_misses::total 908 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses +system.iocache.demand_misses::total 908 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses +system.iocache.overall_misses::total 908 # number of overall misses +system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses @@ -111,39 +151,92 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 2555207 # Throughput (bytes/s) -system.iobus.data_through_bus 13062542 # Total data (bytes) +system.iobus.trans_dist::ReadReq 10011915 # Transaction distribution +system.iobus.trans_dist::ReadResp 10011915 # Transaction distribution +system.iobus.trans_dist::WriteReq 57577 # Transaction distribution +system.iobus.trans_dist::WriteResp 10857 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.iobus.trans_dist::MessageReq 1696 # Transaction distribution +system.iobus.trans_dist::MessageResp 1696 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27352 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 20043728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 20142376 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13676 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 10027982 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 13062574 # Cumulative packet size per connected master and slave (bytes) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10224253344 # number of cpu cycles simulated +system.cpu.numCycles 10224257410 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 199930130 # Number of instructions committed -system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses +system.cpu.committedInsts 199947158 # Number of instructions committed +system.cpu.committedOps 409371517 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 374392167 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2307745 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls -system.cpu.num_int_insts 374365317 # number of integer instructions +system.cpu.num_func_calls 2307997 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 39978602 # number of instructions that are conditional controls +system.cpu.num_int_insts 374392167 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read -system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written +system.cpu.num_int_register_reads 682348609 # number of times the integer registers were read +system.cpu.num_int_register_writes 323388730 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read -system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written -system.cpu.num_mem_refs 35661072 # number of memory refs -system.cpu.num_load_insts 27238907 # Number of load instructions -system.cpu.num_store_insts 8422165 # Number of store instructions -system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles -system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles -system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.955622 # Percentage of idle cycles -system.cpu.Branches 43125613 # Number of branches fetched -system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction -system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction -system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction -system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction +system.cpu.num_cc_register_reads 233729759 # number of times the CC registers were read +system.cpu.num_cc_register_writes 157242019 # number of times the CC registers were written +system.cpu.num_mem_refs 35671209 # number of memory refs +system.cpu.num_load_insts 27243676 # Number of load instructions +system.cpu.num_store_insts 8427533 # Number of store instructions +system.cpu.num_idle_cycles 9770491320.524229 # Number of idle cycles +system.cpu.num_busy_cycles 453766089.475771 # Number of busy cycles +system.cpu.not_idle_fraction 0.044381 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.955619 # Percentage of idle cycles +system.cpu.Branches 43128209 # Number of branches fetched +system.cpu.op_class::No_OpClass 175380 0.04% 0.04% # Class of executed instruction +system.cpu.op_class::IntAlu 373258577 91.18% 91.22% # Class of executed instruction +system.cpu.op_class::IntMult 144442 0.04% 91.26% # Class of executed instruction +system.cpu.op_class::IntDiv 122944 0.03% 91.29% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction @@ -170,18 +263,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction -system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction -system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 27243676 6.65% 97.94% # Class of executed instruction +system.cpu.op_class::MemWrite 8427533 2.06% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 409345569 # Class of executed instruction +system.cpu.op_class::total 409372552 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 790679 # number of replacements +system.cpu.icache.tags.replacements 791918 # number of replacements system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 243546972 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 792430 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 307.341938 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy @@ -189,34 +282,35 @@ system.cpu.icache.tags.occ_percent::total 0.997393 # A system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses -system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits -system.cpu.icache.overall_hits::total 243526070 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses -system.cpu.icache.overall_misses::total 791198 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 245131846 # Number of tag accesses +system.cpu.icache.tags.data_accesses 245131846 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 243546972 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 243546972 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 243546972 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 243546972 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 243546972 # number of overall hits +system.cpu.icache.overall_hits::total 243546972 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 792437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 792437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 792437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 792437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 792437 # number of overall misses +system.cpu.icache.overall_misses::total 792437 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 244339409 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 244339409 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 244339409 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 244339409 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244339409 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 244339409 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -226,50 +320,51 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.026447 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5102112149000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026447 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -278,49 +373,49 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks +system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses +system.cpu.dtb_walker_cache.tags.replacements 8177 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.013955 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12514 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8191 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.527774 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5101283486500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013955 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 53146 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 53146 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12515 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12515 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12515 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12515 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12515 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12515 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9372 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9372 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9372 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9372 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9372 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9372 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21887 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21887 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21887 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21887 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21887 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21887 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428199 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428199 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428199 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428199 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428199 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428199 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -329,65 +424,65 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::writebacks 2797 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2797 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1622084 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1623316 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20184260 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623828 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.430048 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits -system.cpu.dcache.overall_hits::total 20173085 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses -system.cpu.dcache.overall_misses::total 1624882 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses +system.cpu.dcache.tags.tag_accesses 88856245 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88856245 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12022868 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12022868 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8100233 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8100233 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58899 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58899 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20123101 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20123101 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20182000 # number of overall hits +system.cpu.dcache.overall_hits::total 20182000 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 905995 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 905995 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317045 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317045 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403061 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403061 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1223040 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1223040 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1626101 # number of overall misses +system.cpu.dcache.overall_misses::total 1626101 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 12928863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12928863 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8417278 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8417278 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461960 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461960 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21346141 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21346141 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21808101 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21808101 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070075 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070075 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037666 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037666 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872502 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872502 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057296 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057296 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074564 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074564 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,118 +491,148 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks -system.cpu.dcache.writebacks::total 1535815 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1536734 # number of writebacks +system.cpu.dcache.writebacks::total 1536734 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s) -system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes) -system.cpu.l2cache.tags.replacements 105997 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks. +system.cpu.toL2Bus.trans_dist::ReadReq 15972635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 15972635 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1540333 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 314785 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 314785 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584874 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32530908 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21541 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 34147285 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50715968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227701267 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # 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Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4020451 # Request fanout histogram +system.cpu.l2cache.tags.replacements 106060 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64822.097552 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3461863 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 170171 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.343437 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 51909.062113 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32243624 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32243624 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7334 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 779106 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1276189 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2065966 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1540333 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1540333 # 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number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 314780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 314780 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7335 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 792424 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1623195 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2426296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7335 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792424 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1623195 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2426296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024630 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021572 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987985 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987985 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428134 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.428134 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.102880 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.074318 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.102880 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.074318 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -516,8 +641,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks -system.cpu.l2cache.writebacks::total 98154 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 98213 # number of writebacks +system.cpu.l2cache.writebacks::total 98213 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 015764a13..0fe5602ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.192526 # Number of seconds simulated -sim_ticks 5192526233000 # Number of ticks simulated -final_tick 5192526233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.192511 # Number of seconds simulated +sim_ticks 5192511044000 # Number of ticks simulated +final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1492668 # Simulator instruction rate (inst/s) -host_op_rate 2877328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60393582039 # Simulator tick rate (ticks/s) -host_mem_usage 592376 # Number of bytes of host memory used -host_seconds 85.98 # Real time elapsed on the host -sim_insts 128336778 # Number of instructions simulated -sim_ops 247387190 # Number of ops (including micro ops) simulated +host_inst_rate 1018343 # Simulator instruction rate (inst/s) +host_op_rate 1963050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41210458750 # Simulator tick rate (ticks/s) +host_mem_usage 646888 # Number of bytes of host memory used +host_seconds 126.00 # Real time elapsed on the host +sim_insts 128310974 # Number of instructions simulated +sim_ops 247343919 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 829632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9090688 # Number of bytes read from this memory -system.physmem.bytes_read::total 9949056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 829632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 829632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5138240 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory +system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 8128320 # Number of bytes written to this memory +system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12963 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142042 # Number of read requests responded to by this memory -system.physmem.num_reads::total 155454 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 80285 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory +system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 127005 # Number of write requests responded to by this memory +system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1750725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1916034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 989545 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 575843 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1565388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 989545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 581303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1750725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3481422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 155454 # Number of read requests accepted -system.physmem.writeReqs 127005 # Number of write requests accepted -system.physmem.readBursts 155454 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 127005 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9932928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16128 # Total number of bytes read from write queue -system.physmem.bytesWritten 8126720 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9949056 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8128320 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 252 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 155196 # Number of read requests accepted +system.physmem.writeReqs 127063 # Number of write requests accepted +system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue +system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1602 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10234 # Per bank write bursts -system.physmem.perBankRdBursts::1 9830 # Per bank write bursts -system.physmem.perBankRdBursts::2 10412 # Per bank write bursts -system.physmem.perBankRdBursts::3 9937 # Per bank write bursts -system.physmem.perBankRdBursts::4 9788 # Per bank write bursts -system.physmem.perBankRdBursts::5 9348 # Per bank write bursts -system.physmem.perBankRdBursts::6 9238 # Per bank write bursts -system.physmem.perBankRdBursts::7 9473 # Per bank write bursts -system.physmem.perBankRdBursts::8 9270 # Per bank write bursts -system.physmem.perBankRdBursts::9 9085 # Per bank write bursts -system.physmem.perBankRdBursts::10 9528 # Per bank write bursts -system.physmem.perBankRdBursts::11 9619 # Per bank write bursts -system.physmem.perBankRdBursts::12 9707 # Per bank write bursts -system.physmem.perBankRdBursts::13 10058 # Per bank write bursts -system.physmem.perBankRdBursts::14 9877 # Per bank write bursts -system.physmem.perBankRdBursts::15 9798 # Per bank write bursts -system.physmem.perBankWrBursts::0 8316 # Per bank write bursts -system.physmem.perBankWrBursts::1 7729 # Per bank write bursts -system.physmem.perBankWrBursts::2 8212 # Per bank write bursts -system.physmem.perBankWrBursts::3 7860 # Per bank write bursts -system.physmem.perBankWrBursts::4 8063 # Per bank write bursts -system.physmem.perBankWrBursts::5 7657 # Per bank write bursts -system.physmem.perBankWrBursts::6 7184 # Per bank write bursts -system.physmem.perBankWrBursts::7 7824 # Per bank write bursts -system.physmem.perBankWrBursts::8 7616 # Per bank write bursts -system.physmem.perBankWrBursts::9 7570 # Per bank write bursts -system.physmem.perBankWrBursts::10 7824 # Per bank write bursts -system.physmem.perBankWrBursts::11 7928 # Per bank write bursts -system.physmem.perBankWrBursts::12 8040 # Per bank write bursts -system.physmem.perBankWrBursts::13 8642 # Per bank write bursts -system.physmem.perBankWrBursts::14 8420 # Per bank write bursts -system.physmem.perBankWrBursts::15 8095 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10479 # Per bank write bursts +system.physmem.perBankRdBursts::1 9637 # Per bank write bursts +system.physmem.perBankRdBursts::2 10137 # Per bank write bursts +system.physmem.perBankRdBursts::3 9789 # Per bank write bursts +system.physmem.perBankRdBursts::4 9555 # Per bank write bursts +system.physmem.perBankRdBursts::5 9513 # Per bank write bursts +system.physmem.perBankRdBursts::6 9351 # Per bank write bursts +system.physmem.perBankRdBursts::7 9512 # Per bank write bursts +system.physmem.perBankRdBursts::8 9073 # Per bank write bursts +system.physmem.perBankRdBursts::9 8991 # Per bank write bursts +system.physmem.perBankRdBursts::10 9630 # Per bank write bursts +system.physmem.perBankRdBursts::11 9438 # Per bank write bursts +system.physmem.perBankRdBursts::12 9550 # Per bank write bursts +system.physmem.perBankRdBursts::13 10095 # Per bank write bursts +system.physmem.perBankRdBursts::14 10146 # Per bank write bursts +system.physmem.perBankRdBursts::15 10025 # Per bank write bursts +system.physmem.perBankWrBursts::0 8301 # Per bank write bursts +system.physmem.perBankWrBursts::1 8002 # Per bank write bursts +system.physmem.perBankWrBursts::2 8301 # Per bank write bursts +system.physmem.perBankWrBursts::3 8212 # Per bank write bursts +system.physmem.perBankWrBursts::4 7990 # Per bank write bursts +system.physmem.perBankWrBursts::5 7535 # Per bank write bursts +system.physmem.perBankWrBursts::6 7392 # Per bank write bursts +system.physmem.perBankWrBursts::7 7734 # Per bank write bursts +system.physmem.perBankWrBursts::8 7444 # Per bank write bursts +system.physmem.perBankWrBursts::9 7612 # Per bank write bursts +system.physmem.perBankWrBursts::10 7970 # Per bank write bursts +system.physmem.perBankWrBursts::11 7896 # Per bank write bursts +system.physmem.perBankWrBursts::12 8102 # Per bank write bursts +system.physmem.perBankWrBursts::13 8416 # Per bank write bursts +system.physmem.perBankWrBursts::14 8297 # Per bank write bursts +system.physmem.perBankWrBursts::15 7835 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5192526169500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 5192510980500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 155454 # Read request sizes (log2) +system.physmem.readPktSize::6 155196 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 127005 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3023 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see +system.physmem.writePktSize::6 127063 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 151525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see @@ -159,232 +159,241 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7675 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 56259 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.007910 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.347718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.337897 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 20082 35.70% 35.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13652 24.27% 59.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5681 10.10% 70.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3443 6.12% 76.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2317 4.12% 80.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1632 2.90% 83.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1101 1.96% 85.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1008 1.79% 86.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7343 13.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 56259 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5896 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.315638 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 622.349689 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 5895 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57292 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.928814 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21127 36.88% 36.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13732 23.97% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5729 10.00% 70.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3461 6.04% 76.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2250 3.93% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1575 2.75% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1105 1.93% 85.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1008 1.76% 87.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57292 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 621.882480 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5896 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5896 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.536635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.431893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.049302 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4860 82.43% 82.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 44 0.75% 83.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 38 0.64% 83.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 287 4.87% 88.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 272 4.61% 93.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.34% 93.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 25 0.42% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.19% 94.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 27 0.46% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.07% 94.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 223 3.78% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.10% 98.80% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4886 82.74% 82.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.34% 93.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 10 0.17% 93.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 19 0.32% 94.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 22 0.37% 94.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.10% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 20 0.34% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.02% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 10 0.17% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 8 0.14% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 4 0.07% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 13 0.22% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.20% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5896 # Writes before turning the bus around for reads -system.physmem.totQLat 1473683250 # Total ticks spent queuing -system.physmem.totMemAccLat 4383720750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 776010000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9495.26 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads +system.physmem.totQLat 1558594500 # Total ticks spent queuing +system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28245.26 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.52 # Average write queue length when enqueuing -system.physmem.readRowHits 127189 # Number of row buffer hits during reads -system.physmem.writeRowHits 98733 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes -system.physmem.avgGap 18383291.63 # Average gap between requests -system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4971157882750 # Time in different power states -system.physmem.memoryStateTime::REF 173389840000 # Time in different power states +system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing +system.physmem.readRowHits 125976 # Number of row buffer hits during reads +system.physmem.writeRowHits 98691 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes +system.physmem.avgGap 18396263.65 # Average gap between requests +system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states +system.physmem.memoryStateTime::REF 173389320000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 47978395250 # Time in different power states +system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 3808612 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 623901 # Transaction distribution -system.membus.trans_dist::ReadResp 623901 # Transaction distribution +system.membus.trans_dist::ReadReq 623858 # Transaction distribution +system.membus.trans_dist::ReadResp 623858 # Transaction distribution system.membus.trans_dist::WriteReq 13773 # Transaction distribution system.membus.trans_dist::WriteResp 13773 # Transaction distribution -system.membus.trans_dist::Writeback 80285 # Transaction distribution +system.membus.trans_dist::Writeback 80343 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1602 # Transaction distribution -system.membus.trans_dist::ReadExReq 113400 # Transaction distribution -system.membus.trans_dist::ReadExResp 113400 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1594 # Transaction distribution +system.membus.trans_dist::ReadExReq 113180 # Transaction distribution +system.membus.trans_dist::ReadExResp 113180 # Transaction distribution system.membus.trans_dist::MessageReq 1654 # Transaction distribution system.membus.trans_dist::MessageResp 1654 # Transaction distribution system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394055 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584493 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94727 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1682528 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15058944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16725605 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 19750653 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 19750653 # Total data (bytes) -system.membus.snoop_data_through_bus 25664 # Total snoop data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1682057 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15046144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16712805 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 948 # Total snoops (count) +system.membus.snoop_fanout::samples 284802 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 284802 # Request fanout histogram system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1309717000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2621518398 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54330498 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47509 # number of replacements -system.iocache.tags.tagsinuse 0.112613 # Cycle average of tags in use +system.iocache.tags.replacements 47504 # number of replacements +system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47525 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045777659000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112613 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007038 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007038 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428076 # Number of tag accesses -system.iocache.tags.data_accesses 428076 # Number of data accesses +system.iocache.tags.tag_accesses 428031 # Number of tag accesses +system.iocache.tags.data_accesses 428031 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses -system.iocache.ReadReq_misses::total 844 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses -system.iocache.demand_misses::total 844 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses -system.iocache.overall_misses::total 844 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141199186 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 141199186 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 141199186 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 141199186 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 141199186 # number of overall miss cycles -system.iocache.overall_miss_latency::total 141199186 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 839 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 839 # number of demand (read+write) misses +system.iocache.demand_misses::total 839 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 839 # number of overall misses +system.iocache.overall_misses::total 839 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140842436 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 140842436 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 140842436 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 140842436 # number of overall miss cycles +system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 839 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 839 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 839 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 839 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167297.613744 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167297.613744 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167297.613744 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked @@ -393,22 +402,22 @@ system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 97286186 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2834928162 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2834928162 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 97286186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 97286186 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -417,14 +426,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115267.992891 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60679.113057 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60679.113057 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -438,9 +447,8 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 631746 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 230149 # Transaction distribution -system.iobus.trans_dist::ReadResp 230149 # Transaction distribution +system.iobus.trans_dist::ReadReq 230144 # Transaction distribution +system.iobus.trans_dist::ReadResp 230144 # Transaction distribution system.iobus.trans_dist::WriteReq 57579 # Transaction distribution system.iobus.trans_dist::WriteResp 57579 # Transaction distribution system.iobus.trans_dist::MessageReq 1654 # Transaction distribution @@ -464,36 +472,35 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 578764 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3280356 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3280356 # Total data (bytes) +system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) @@ -530,47 +537,47 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 421898846 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 421888846 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52228502 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52218502 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10385052466 # number of cpu cycles simulated +system.cpu.numCycles 10385022088 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128336778 # Number of instructions committed -system.cpu.committedOps 247387190 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 231979854 # Number of integer alu accesses +system.cpu.committedInsts 128310974 # Number of instructions committed +system.cpu.committedOps 247343919 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 231936467 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 2299861 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23168822 # number of instructions that are conditional controls -system.cpu.num_int_insts 231979854 # number of integer instructions +system.cpu.num_func_calls 2299885 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23161985 # number of instructions that are conditional controls +system.cpu.num_int_insts 231936467 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 434516750 # number of times the integer registers were read -system.cpu.num_int_register_writes 197854064 # number of times the integer registers were written +system.cpu.num_int_register_reads 434450917 # number of times the integer registers were read +system.cpu.num_int_register_writes 197819265 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 132811657 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95534544 # number of times the CC registers were written -system.cpu.num_mem_refs 22246380 # number of memory refs -system.cpu.num_load_insts 13880618 # Number of load instructions -system.cpu.num_store_insts 8365762 # Number of store instructions -system.cpu.num_idle_cycles 9788359567.998116 # Number of idle cycles -system.cpu.num_busy_cycles 596692898.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057457 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942543 # Percentage of idle cycles -system.cpu.Branches 26306776 # Number of branches fetched -system.cpu.op_class::No_OpClass 174693 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 224704760 90.83% 90.90% # Class of executed instruction -system.cpu.op_class::IntMult 139946 0.06% 90.96% # Class of executed instruction -system.cpu.op_class::IntDiv 122983 0.05% 91.01% # Class of executed instruction +system.cpu.num_cc_register_reads 132769519 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95505601 # number of times the CC registers were written +system.cpu.num_mem_refs 22243286 # number of memory refs +system.cpu.num_load_insts 13879256 # Number of load instructions +system.cpu.num_store_insts 8364030 # Number of store instructions +system.cpu.num_idle_cycles 9788400874.998116 # Number of idle cycles +system.cpu.num_busy_cycles 596621213.001885 # Number of busy cycles +system.cpu.not_idle_fraction 0.057450 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942550 # Percentage of idle cycles +system.cpu.Branches 26299942 # Number of branches fetched +system.cpu.op_class::No_OpClass 174748 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 224664535 90.83% 90.90% # Class of executed instruction +system.cpu.op_class::IntMult 139903 0.06% 90.96% # Class of executed instruction +system.cpu.op_class::IntDiv 122942 0.05% 91.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction @@ -597,66 +604,66 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction -system.cpu.op_class::MemRead 13880618 5.61% 96.62% # Class of executed instruction -system.cpu.op_class::MemWrite 8365762 3.38% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13879256 5.61% 96.62% # Class of executed instruction +system.cpu.op_class::MemWrite 8364030 3.38% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 247388762 # Class of executed instruction +system.cpu.op_class::total 247345414 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.icache.tags.replacements 794564 # number of replacements -system.cpu.icache.tags.tagsinuse 510.353610 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 144580687 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 795076 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 181.845115 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161037642250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.353610 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 790109 # number of replacements +system.cpu.icache.tags.tagsinuse 510.353605 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144545821 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 790621 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.825679 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161037022250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.353605 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146170853 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146170853 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 144580687 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 144580687 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 144580687 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 144580687 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 144580687 # number of overall hits -system.cpu.icache.overall_hits::total 144580687 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 795083 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 795083 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 795083 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 795083 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 795083 # number of overall misses -system.cpu.icache.overall_misses::total 795083 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11158319369 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11158319369 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11158319369 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11158319369 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11158319369 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11158319369 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145375770 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145375770 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145375770 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145375770 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145375770 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145375770 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005469 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005469 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005469 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005469 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005469 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005469 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.156647 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14034.156647 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14034.156647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14034.156647 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146127077 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146127077 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144545821 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144545821 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144545821 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144545821 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144545821 # number of overall hits +system.cpu.icache.overall_hits::total 144545821 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 790628 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 790628 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 790628 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 790628 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 790628 # number of overall misses +system.cpu.icache.overall_misses::total 790628 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108318120 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11108318120 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11108318120 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11108318120 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11108318120 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11108318120 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145336449 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145336449 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145336449 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145336449 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145336449 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145336449 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14049.993322 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14049.993322 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,87 +672,87 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795083 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 795083 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 795083 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 795083 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 795083 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 795083 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9563233631 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9563233631 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9563233631 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9563233631 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9563233631 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9563233631 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005469 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005469 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005469 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.968943 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.968943 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790628 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 790628 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 790628 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 790628 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 790628 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 790628 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9522182380 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9522182380 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9522182380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9522182380 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9522182380 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9522182380 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12043.821342 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12043.821342 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3511 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.067889 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7844 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3523 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.226511 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5164932679000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.067889 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191743 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191743 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28837 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28837 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7845 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7845 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 3485 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.066895 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7845 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 3494 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 2.245278 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5167508806000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066895 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191681 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191681 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.562500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 28811 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 28811 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7868 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7868 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7847 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7847 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7847 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7847 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4381 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4381 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4381 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4381 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4381 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4381 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43773750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43773750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43773750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 43773750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43773750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 43773750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12226 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7870 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7870 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7870 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7870 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4357 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 4357 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4357 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 4357 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4357 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 4357 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43584500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43584500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43584500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 43584500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43584500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 43584500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12228 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12228 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358335 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358335 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358276 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.358276 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358276 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.358276 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9991.725633 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9991.725633 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9991.725633 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9991.725633 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356401 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356401 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356343 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.356343 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356343 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.356343 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -754,86 +761,86 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 771 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 771 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4381 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4381 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4381 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4381 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4381 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35010250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35010250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35010250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35010250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35010250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35010250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358335 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358335 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358276 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358276 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7991.383246 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 747 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 747 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4357 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4357 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4357 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4357 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4357 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4357 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34868500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34868500 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34868500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34868500 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34868500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34868500 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356401 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356401 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356343 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356343 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8002.868947 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7447 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.051866 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13273 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7461 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.778984 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5163481853000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051866 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.replacements 7826 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.051872 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12792 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 7842 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.631217 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051872 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52546 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52546 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13289 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13289 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13289 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13289 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13289 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13289 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8656 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8656 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8656 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8656 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8656 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8656 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91979000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91979000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91979000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 91979000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91979000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 91979000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21945 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 21945 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21945 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 21945 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21945 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 21945 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394441 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394441 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394441 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394441 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394441 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394441 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10626.039741 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10626.039741 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10626.039741 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10626.039741 # average overall miss latency +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 52641 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 52641 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12792 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12792 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12792 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12792 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12792 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12792 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9019 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 9019 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9019 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 9019 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9019 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 9019 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95783000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95783000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95783000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 95783000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95783000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 95783000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21811 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 21811 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21811 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 21811 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21811 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 21811 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.413507 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.413507 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.413507 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.413507 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.413507 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.413507 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10620.135270 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -842,170 +849,169 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2980 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2980 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8656 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8656 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8656 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8656 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8656 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8656 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74666500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74666500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74666500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74666500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74666500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74666500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394441 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394441 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394441 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8625.981978 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 2842 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2842 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9019 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9019 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9019 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 9019 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9019 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 9019 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77744500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77744500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77744500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77744500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77744500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77744500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.413507 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.413507 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.413507 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8620.079831 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1620883 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.997130 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20027756 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1621395 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.352176 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1621218 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996934 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20024389 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1621730 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.347548 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.997130 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996934 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88256675 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88256675 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11935486 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11935486 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8030839 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8030839 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59261 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59261 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19966325 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19966325 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20025586 # number of overall hits -system.cpu.dcache.overall_hits::total 20025586 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906294 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906294 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 324617 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 324617 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402313 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402313 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1230911 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1230911 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1633224 # number of overall misses -system.cpu.dcache.overall_misses::total 1633224 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12712957750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12712957750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341720828 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11341720828 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24054678578 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24054678578 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24054678578 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24054678578 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12841780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12841780 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8355456 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8355456 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461574 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461574 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21197236 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21197236 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21658810 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21658810 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070574 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070574 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038851 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038851 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871611 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871611 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.058069 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.058069 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075407 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075407 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14027.410255 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14027.410255 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34938.776552 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34938.776552 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19542.175330 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19542.175330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14728.340128 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14728.340128 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7655 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88244906 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88244906 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11933720 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11933720 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8029176 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8029176 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 59323 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 59323 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19962896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19962896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20022219 # number of overall hits +system.cpu.dcache.overall_hits::total 20022219 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906567 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906567 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 324536 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 324536 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 402460 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 402460 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1231103 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1231103 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1633563 # number of overall misses +system.cpu.dcache.overall_misses::total 1633563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12726532750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12726532750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11379509067 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11379509067 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24106041817 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24106041817 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24106041817 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24106041817 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12840287 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12840287 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8353712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8353712 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 461783 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 461783 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21193999 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21193999 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21655782 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21655782 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070603 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070603 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038849 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038849 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871535 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.871535 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.058087 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.058087 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19580.848895 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14756.726136 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 8324 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 80 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.863014 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.050000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1537682 # number of writebacks -system.cpu.dcache.writebacks::total 1537682 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1537872 # number of writebacks +system.cpu.dcache.writebacks::total 1537872 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9297 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9297 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9584 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9584 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906007 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 906007 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 315320 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402278 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402278 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1221327 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1221327 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1623605 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1623605 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10893569500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10893569500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10209797624 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10209797624 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5351981750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5351981750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21103367124 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21103367124 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26455348874 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26455348874 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9293 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9580 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9580 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9580 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9580 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906280 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1623948 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245705379 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5368514000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21152007379 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537257000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537257000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751929000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751929000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070552 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070552 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037738 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037738 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871535 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871535 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057617 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057617 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074963 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074963 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.714497 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.714497 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32379.162831 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32379.162831 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13304.187030 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13304.187030 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17279.047400 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17279.047400 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16294.202638 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16294.202638 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1013,185 +1019,196 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 49844829 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2698695 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2698173 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1541433 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 313150 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 313150 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1590153 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5974271 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8035 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18003 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7590462 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50884480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203815525 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 233856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 598208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 255532069 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 255511461 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3309120 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3832514500 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53135 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3969426 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47560 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4016986 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3830670000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 478500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1195084369 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1188381870 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3051993102 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3052447844 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6572250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 6536500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 12984250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 13528750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 87211 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64746.136544 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3491181 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 151954 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.975249 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87289 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64708.241819 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3488268 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151942 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 22.957892 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50332.685507 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006414 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141265 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3220.709839 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11192.593518 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.012829 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3236.502324 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.766021 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049144 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170785 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64743 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57056 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987900 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32212608 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32212608 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6366 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2878 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 782107 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1278785 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2070136 # 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number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1200,90 +1217,90 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80285 # number of writebacks -system.cpu.l2cache.writebacks::total 80285 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80343 # number of writebacks +system.cpu.l2cache.writebacks::total 80343 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 138750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 792612500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8294890275 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9087943025 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655868500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655868500 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634000 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026502500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026502500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021907 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019705 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808420 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808420 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.363017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.363017 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.064039 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.064039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60525.341356 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.252496 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61869.631828 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.679245 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.679245 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56692.990024 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56692.990024 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021895 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019721 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808706 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362397 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.064033 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.064033 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61305.011989 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63324.536439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62696.401511 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.274450 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.274450 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57128.073025 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57128.073025 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 403e6b21a..3b5938eca 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -1,50 +1,81 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.200409 # Number of seconds simulated -sim_ticks 200409284500 # Number of ticks simulated -final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 200409271000 # Number of ticks simulated +final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 23274047 # Simulator instruction rate (inst/s) -host_op_rate 23274036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8904961694 # Simulator tick rate (ticks/s) -host_mem_usage 483300 # Number of bytes of host memory used -host_seconds 22.51 # Real time elapsed on the host -sim_insts 523790075 # Number of instructions simulated -sim_ops 523790075 # Number of ops (including micro ops) simulated +host_inst_rate 15445218 # Simulator instruction rate (inst/s) +host_op_rate 15445213 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5909651303 # Simulator tick rate (ticks/s) +host_mem_usage 534848 # Number of bytes of host memory used +host_seconds 33.91 # Real time elapsed on the host +sim_insts 523780905 # Number of instructions simulated +sim_ops 523780905 # Number of ops (including micro ops) simulated testsys.voltage_domain.voltage 1 # Voltage in Volts testsys.clk_domain.clock 1000 # Clock period in ticks -testsys.physmem.bytes_read::cpu.inst 81046720 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 27826276 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.inst 81044080 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 27825116 # Number of bytes read from this memory testsys.physmem.bytes_read::tsunami.ethernet 57260496 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 166133492 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 81046720 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 81046720 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 16606680 # Number of bytes written to this memory +testsys.physmem.bytes_read::total 166129692 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 81044080 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 81044080 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 16605404 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 16607582 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 20261680 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 3842559 # Number of read requests responded to by this memory +testsys.physmem.bytes_written::total 16606306 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 20261020 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 3842409 # Number of read requests responded to by this memory testsys.physmem.num_reads::tsunami.ethernet 2385836 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 26490075 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 2258392 # Number of write requests responded to by this memory +testsys.physmem.num_reads::total 26489265 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 2258228 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 2258423 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 404406014 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 138847240 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 285717781 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 828971035 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 404406014 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 404406014 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 82863826 # Write bandwidth from this memory (bytes/s) +testsys.physmem.num_writes::total 2258259 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 404392869 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 138841461 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 285717800 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 828952130 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 404392869 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 404392869 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 82857464 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 82868326 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 404406014 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 221711065 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 285722281 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 911839361 # Total bandwidth to/from this memory (bytes/s) -testsys.membus.throughput 916540501 # Throughput (bytes/s) -testsys.membus.data_through_bus 183683226 # Total data (bytes) -testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +testsys.physmem.bw_write::total 82861965 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 404392869 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 221698925 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 285722301 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 911814095 # Total bandwidth to/from this memory (bytes/s) +testsys.membus.trans_dist::ReadReq 26478762 # Transaction distribution +testsys.membus.trans_dist::ReadResp 26587372 # Transaction distribution +testsys.membus.trans_dist::WriteReq 2189273 # Transaction distribution +testsys.membus.trans_dist::WriteResp 2189273 # Transaction distribution +testsys.membus.trans_dist::LoadLockedReq 108610 # Transaction distribution +testsys.membus.trans_dist::StoreCondReq 108528 # Transaction distribution +testsys.membus.trans_dist::StoreCondResp 108528 # Transaction distribution +testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 40522040 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.icache_port::total 40522040 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 275298 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 12201274 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.dcache_port::total 12476572 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 4771734 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.iobridge.master::total 4771734 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count::total 57770346 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 81044080 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.icache_port::total 81044080 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 942152 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 44430520 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.dcache_port::total 45372672 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 57261398 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.snoops 0 # Total snoops (count) +testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram +testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram +testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram +testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram +testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram +testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram +testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram +testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -62,22 +93,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 3916918 # DTB read hits +testsys.cpu.dtb.read_hits 3916768 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 2316885 # DTB write hits +testsys.cpu.dtb.write_hits 2316721 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 6233803 # DTB hits +testsys.cpu.dtb.data_hits 6233489 # DTB hits testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 4052211 # ITB hits +testsys.cpu.itb.fetch_hits 4052237 # ITB hits testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 4053708 # ITB accesses +testsys.cpu.itb.fetch_accesses 4053734 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -90,31 +121,31 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 400804755 # number of cpu cycles simulated +testsys.cpu.numCycles 400825859 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 20257704 # Number of instructions committed -testsys.cpu.committedOps 20257704 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 18837017 # Number of integer alu accesses +testsys.cpu.committedInsts 20257044 # Number of instructions committed +testsys.cpu.committedOps 20257044 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 18836392 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses -testsys.cpu.num_func_calls 1221180 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 1442148 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 18837017 # number of integer instructions +testsys.cpu.num_func_calls 1221158 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 1442105 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 18836392 # number of integer instructions testsys.cpu.num_fp_insts 17380 # number of float instructions -testsys.cpu.num_int_register_reads 24787248 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 14693875 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 24786330 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 14693469 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written -testsys.cpu.num_mem_refs 6263046 # number of memory refs -testsys.cpu.num_load_insts 3944033 # Number of load instructions -testsys.cpu.num_store_insts 2319013 # Number of store instructions -testsys.cpu.num_idle_cycles 380542207.362158 # Number of idle cycles -testsys.cpu.num_busy_cycles 20262547.637842 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.050555 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles -testsys.cpu.Branches 2929848 # Number of branches fetched -testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction -testsys.cpu.op_class::IntAlu 12147338 59.95% 63.47% # Class of executed instruction +testsys.cpu.num_mem_refs 6262732 # number of memory refs +testsys.cpu.num_load_insts 3943883 # Number of load instructions +testsys.cpu.num_store_insts 2318849 # Number of store instructions +testsys.cpu.num_idle_cycles 380582482.461103 # Number of idle cycles +testsys.cpu.num_busy_cycles 20243376.538897 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.050504 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.949496 # Percentage of idle cycles +testsys.cpu.Branches 2929782 # Number of branches fetched +testsys.cpu.op_class::No_OpClass 712785 3.52% 3.52% # Class of executed instruction +testsys.cpu.op_class::IntAlu 12147004 59.95% 63.47% # Class of executed instruction testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction @@ -143,34 +174,34 @@ testsys.cpu.op_class::SimdFloatMisc 0 0.00% 63.60% # Cl testsys.cpu.op_class::SimdFloatMult 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.60% # Class of executed instruction testsys.cpu.op_class::SimdFloatSqrt 0 0.00% 63.60% # Class of executed instruction -testsys.cpu.op_class::MemRead 4230637 20.88% 84.48% # Class of executed instruction -testsys.cpu.op_class::MemWrite 2319552 11.45% 95.93% # Class of executed instruction -testsys.cpu.op_class::IprAccess 824102 4.07% 100.00% # Class of executed instruction +testsys.cpu.op_class::MemRead 4230485 20.88% 84.48% # Class of executed instruction +testsys.cpu.op_class::MemWrite 2319388 11.45% 95.93% # Class of executed instruction +testsys.cpu.op_class::IprAccess 824126 4.07% 100.00% # Class of executed instruction testsys.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -testsys.cpu.op_class::total 20261680 # Class of executed instruction +testsys.cpu.op_class::total 20261020 # Class of executed instruction testsys.cpu.kern.inst.arm 0 # number of arm instructions executed testsys.cpu.kern.inst.quiesce 19580 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 153667 # number of hwrei instructions executed +testsys.cpu.kern.inst.hwrei 153669 # number of hwrei instructions executed testsys.cpu.kern.ipl_count::0 62779 42.67% 42.67% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::21 19625 13.34% 56.01% # number of times we switched to this ipl testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 64509 43.85% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 147118 # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 64511 43.85% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 147120 # number of times we switched to this ipl testsys.cpu.kern.ipl_good::0 62773 43.18% 43.18% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::21 19625 13.50% 56.67% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::22 205 0.14% 56.82% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::31 62785 43.18% 100.00% # number of times we switched to this ipl from a different ipl testsys.cpu.kern.ipl_good::total 145388 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 194346512500 96.98% 96.98% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::0 194347611000 96.98% 96.98% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::21 1588986000 0.79% 97.77% # number of cycles we spent at this ipl testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 4458282500 2.22% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 200402596000 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 4457946500 2.22% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 200403358500 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.973275 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.988241 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.973245 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.988227 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -195,27 +226,27 @@ testsys.cpu.kern.syscall::118 2 2.41% 100.00% # nu testsys.cpu.kern.syscall::total 83 # number of syscalls executed testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 106830 83.26% 83.62% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 106832 83.26% 83.62% # number of callpals executed testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed testsys.cpu.kern.callpal::rdusp 3 0.00% 83.90% # number of callpals executed testsys.cpu.kern.callpal::rti 20470 15.95% 99.86% # number of callpals executed testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 128307 # number of callpals executed +testsys.cpu.kern.callpal::total 128309 # number of callpals executed testsys.cpu.kern.mode_switch::kernel 1280 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 706 # number of protection mode switches testsys.cpu.kern.mode_switch::idle 19629 # number of protection mode switches -testsys.cpu.kern.mode_good::kernel 707 -testsys.cpu.kern.mode_good::user 702 +testsys.cpu.kern.mode_good::kernel 711 +testsys.cpu.kern.mode_good::user 706 testsys.cpu.kern.mode_good::idle 5 -testsys.cpu.kern.mode_switch_good::kernel 0.552344 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::kernel 0.555469 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 0.065430 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 994603000 60.01% 60.01% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 533068000 32.16% 92.17% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 129740500 7.83% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_switch_good::total 0.065788 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks::kernel 994253000 59.96% 59.96% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 533088000 32.15% 92.11% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 130749000 7.89% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted @@ -267,14 +298,32 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post testsys.tsunami.ethernet.postedInterrupts 2385819 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.iobus.throughput 290423421 # Throughput (bytes/s) -testsys.iobus.data_through_bus 58203550 # Total data (bytes) +testsys.iobus.trans_dist::ReadReq 2483943 # Transaction distribution +testsys.iobus.trans_dist::ReadResp 2483943 # Transaction distribution +testsys.iobus.trans_dist::WriteReq 39573 # Transaction distribution +testsys.iobus.trans_dist::WriteResp 39573 # Transaction distribution +testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 196204 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.io.pio 336 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.uart.pio 428 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 78330 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.bridge.master::total 275298 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 4771734 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 4771734 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count::total 5047032 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 784816 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.io.pio 462 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.uart.pio 214 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 156660 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::total 942152 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 57261398 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 57261398 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size::total 58203550 # Cumulative packet size per connected master and slave (bytes) drivesys.voltage_domain.voltage 1 # Voltage in Volts drivesys.clk_domain.clock 1000 # Clock period in ticks drivesys.physmem.bytes_read::cpu.inst 76205572 # Number of bytes read from this memory drivesys.physmem.bytes_read::cpu.data 26284292 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 57260526 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 159750390 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 57260550 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 159750414 # Number of bytes read from this memory drivesys.physmem.bytes_inst_read::cpu.inst 76205572 # Number of instructions bytes read from this memory drivesys.physmem.bytes_inst_read::total 76205572 # Number of instructions bytes read from this memory drivesys.physmem.bytes_written::cpu.data 14619632 # Number of bytes written to this memory @@ -282,27 +331,58 @@ drivesys.physmem.bytes_written::tsunami.ethernet 1064 drivesys.physmem.bytes_written::total 14620696 # Number of bytes written to this memory drivesys.physmem.num_reads::cpu.inst 19051393 # Number of read requests responded to by this memory drivesys.physmem.num_reads::cpu.data 3647049 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 2385838 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 25084280 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 2385839 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 25084281 # Number of read requests responded to by this memory drivesys.physmem.num_writes::cpu.data 2024776 # Number of write requests responded to by this memory drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory drivesys.physmem.num_writes::total 2024813 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 380249708 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 131153065 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 285717930 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 797120704 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 380249708 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 380249708 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 72948876 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.inst 380249734 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 131153074 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 285718069 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 797120878 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 380249734 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 380249734 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 72948881 # Write bandwidth from this memory (bytes/s) drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 72954185 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 380249708 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 204101941 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 285723240 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 870074889 # Total bandwidth to/from this memory (bytes/s) -drivesys.membus.throughput 874808223 # Throughput (bytes/s) -drivesys.membus.data_through_bus 175319690 # Total data (bytes) -drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +drivesys.physmem.bw_write::total 72954190 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 380249734 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 204101955 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 285723379 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 870075068 # Total bandwidth to/from this memory (bytes/s) +drivesys.membus.trans_dist::ReadReq 25081955 # Transaction distribution +drivesys.membus.trans_dist::ReadResp 25182911 # Transaction distribution +drivesys.membus.trans_dist::WriteReq 1963575 # Transaction distribution +drivesys.membus.trans_dist::WriteResp 1963575 # Transaction distribution +drivesys.membus.trans_dist::LoadLockedReq 100956 # Transaction distribution +drivesys.membus.trans_dist::StoreCondReq 100924 # Transaction distribution +drivesys.membus.trans_dist::StoreCondResp 100924 # Transaction distribution +drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 38102786 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 38102786 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 276632 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 11343650 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 11620282 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 4771752 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.iobridge.master::total 4771752 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count::total 54494820 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 76205572 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 76205572 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 948604 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 40903924 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 41852528 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 57261614 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.snoops 0 # Total snoops (count) +drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram +drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram +drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram +drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram +drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram +drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram +drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram +drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -348,7 +428,7 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 801631448 # number of cpu cycles simulated +drivesys.cpu.numCycles 801651324 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed drivesys.cpu.committedInsts 19050784 # Number of instructions committed @@ -366,10 +446,10 @@ drivesys.cpu.num_fp_register_writes 766 # nu drivesys.cpu.num_mem_refs 5830788 # number of memory refs drivesys.cpu.num_load_insts 3746196 # Number of load instructions drivesys.cpu.num_store_insts 2084592 # Number of store instructions -drivesys.cpu.num_idle_cycles 782579974.227931 # Number of idle cycles -drivesys.cpu.num_busy_cycles 19051473.772069 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.023766 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles +drivesys.cpu.num_idle_cycles 782619252.927065 # Number of idle cycles +drivesys.cpu.num_busy_cycles 19032071.072935 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.023741 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.976259 # Percentage of idle cycles drivesys.cpu.Branches 2793313 # Number of branches fetched drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction drivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction @@ -476,9 +556,9 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.descDMAReads 2385809 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 2385810 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 57259416 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 57259440 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) drivesys.tsunami.ethernet.totPackets 13 # Total Packets @@ -505,7 +585,7 @@ drivesys.tsunami.ethernet.coalescedTxOk 0 # av drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR drivesys.tsunami.ethernet.postedTxIdle 19726 # number of TxIdle interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 2385809 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.totalTxIdle 2385810 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -513,25 +593,39 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 2385830 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 2385831 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.iobus.throughput 290456573 # Throughput (bytes/s) -drivesys.iobus.data_through_bus 58210194 # Total data (bytes) +drivesys.iobus.trans_dist::ReadReq 2484469 # Transaction distribution +drivesys.iobus.trans_dist::ReadResp 2484469 # Transaction distribution +drivesys.iobus.trans_dist::WriteReq 39723 # Transaction distribution +drivesys.iobus.trans_dist::WriteResp 39723 # Transaction distribution +drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 197670 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 78962 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.bridge.master::total 276632 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 4771752 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 4771752 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count::total 5048384 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 790680 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 157924 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.bridge.master::total 948604 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 57261614 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 57261614 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size::total 58210218 # Cumulative packet size per connected master and slave (bytes) ---------- End Simulation Statistics ---------- ---------- Begin Simulation Statistics ---------- sim_seconds 0.000407 # Number of seconds simulated sim_ticks 407341500 # Number of ticks simulated -final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11799945954 # Simulator instruction rate (inst/s) -host_op_rate 11797124974 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9171074905 # Simulator tick rate (ticks/s) -host_mem_usage 483300 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 523862353 # Number of instructions simulated -sim_ops 523862353 # Number of ops (including micro ops) simulated +host_inst_rate 7893991697 # Simulator instruction rate (inst/s) +host_op_rate 7892445581 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6135954870 # Simulator tick rate (ticks/s) +host_mem_usage 534848 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +sim_insts 523853183 # Number of instructions simulated +sim_ops 523853183 # Number of ops (including micro ops) simulated testsys.voltage_domain.voltage 1 # Voltage in Volts testsys.clk_domain.clock 1000 # Clock period in ticks testsys.physmem.bytes_read::cpu.inst 144504 # Number of bytes read from this memory @@ -560,9 +654,40 @@ testsys.physmem.bw_total::cpu.inst 354749025 # To testsys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::tsunami.ethernet 285696400 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.bw_total::total 831047168 # Total bandwidth to/from this memory (bytes/s) -testsys.membus.throughput 835780297 # Throughput (bytes/s) -testsys.membus.data_through_bus 340448 # Total data (bytes) -testsys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +testsys.membus.trans_dist::ReadReq 47876 # Transaction distribution +testsys.membus.trans_dist::ReadResp 48080 # Transaction distribution +testsys.membus.trans_dist::WriteReq 3691 # Transaction distribution +testsys.membus.trans_dist::WriteResp 3691 # Transaction distribution +testsys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution +testsys.membus.trans_dist::StoreCondReq 204 # Transaction distribution +testsys.membus.trans_dist::StoreCondResp 204 # Transaction distribution +testsys.membus.pkt_count_testsys.cpu.icache_port::testsys.physmem.port 72252 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.icache_port::total 72252 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.bridge.slave 562 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.dcache_port::testsys.physmem.port 21438 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.cpu.dcache_port::total 22000 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.iobridge.master::testsys.physmem.port 9698 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count_testsys.iobridge.master::total 9698 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_count::total 103950 # Packet count per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.icache_port::testsys.physmem.port 144504 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.icache_port::total 144504 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.dcache_port::testsys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.iobridge.master::testsys.physmem.port 116376 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes) +testsys.membus.snoops 0 # Total snoops (count) +testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram +testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram +testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram +testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram +testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram +testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram +testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram +testsys.membus.snoop_fanout::total 51694 # Request fanout histogram testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -608,7 +733,7 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 821016 # number of cpu cycles simulated +testsys.cpu.numCycles 821056 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed testsys.cpu.committedInsts 36126 # Number of instructions committed @@ -626,10 +751,10 @@ testsys.cpu.num_fp_register_writes 0 # nu testsys.cpu.num_mem_refs 11041 # number of memory refs testsys.cpu.num_load_insts 7105 # Number of load instructions testsys.cpu.num_store_insts 3936 # Number of store instructions -testsys.cpu.num_idle_cycles 784609.171892 # Number of idle cycles -testsys.cpu.num_busy_cycles 36406.828108 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.044344 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.955656 # Percentage of idle cycles +testsys.cpu.num_idle_cycles 784687.711054 # Number of idle cycles +testsys.cpu.num_busy_cycles 36368.288946 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.044295 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.955705 # Percentage of idle cycles testsys.cpu.Branches 5238 # Number of branches fetched testsys.cpu.op_class::No_OpClass 1261 3.49% 3.49% # Class of executed instruction testsys.cpu.op_class::IntAlu 21664 59.97% 63.46% # Class of executed instruction @@ -739,8 +864,22 @@ testsys.tsunami.ethernet.totalRxOrn 0 # to testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post testsys.tsunami.ethernet.postedInterrupts 4849 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -testsys.iobus.throughput 290429529 # Throughput (bytes/s) -testsys.iobus.data_through_bus 118304 # Total data (bytes) +testsys.iobus.trans_dist::ReadReq 5049 # Transaction distribution +testsys.iobus.trans_dist::ReadResp 5049 # Transaction distribution +testsys.iobus.trans_dist::WriteReq 81 # Transaction distribution +testsys.iobus.trans_dist::WriteResp 81 # Transaction distribution +testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.bridge.master::testsys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.bridge.master::total 562 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 9698 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count_testsys.tsunami.ethernet.dma::total 9698 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_count::total 10260 # Packet count per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::testsys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::testsys.iobridge.slave 116376 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size_testsys.tsunami.ethernet.dma::total 116376 # Cumulative packet size per connected master and slave (bytes) +testsys.iobus.pkt_size::total 118304 # Cumulative packet size per connected master and slave (bytes) drivesys.voltage_domain.voltage 1 # Voltage in Volts drivesys.clk_domain.clock 1000 # Clock period in ticks drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory @@ -769,9 +908,40 @@ drivesys.physmem.bw_total::cpu.inst 355004339 # To drivesys.physmem.bw_total::cpu.data 190601743 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::tsunami.ethernet 285755318 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.bw_total::total 831361401 # Total bandwidth to/from this memory (bytes/s) -drivesys.membus.throughput 836094530 # Throughput (bytes/s) -drivesys.membus.data_through_bus 340576 # Total data (bytes) -drivesys.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +drivesys.membus.trans_dist::ReadReq 47907 # Transaction distribution +drivesys.membus.trans_dist::ReadResp 48111 # Transaction distribution +drivesys.membus.trans_dist::WriteReq 3689 # Transaction distribution +drivesys.membus.trans_dist::WriteResp 3689 # Transaction distribution +drivesys.membus.trans_dist::LoadLockedReq 204 # Transaction distribution +drivesys.membus.trans_dist::StoreCondReq 204 # Transaction distribution +drivesys.membus.trans_dist::StoreCondResp 204 # Transaction distribution +drivesys.membus.pkt_count_drivesys.cpu.icache_port::drivesys.physmem.port 72304 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.icache_port::total 72304 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.bridge.slave 562 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.dcache_port::drivesys.physmem.port 21442 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.cpu.dcache_port::total 22004 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.iobridge.master::drivesys.physmem.port 9700 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count_drivesys.iobridge.master::total 9700 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_count::total 104008 # Packet count per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.icache_port::drivesys.physmem.port 144608 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.icache_port::total 144608 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.bridge.slave 1928 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.dcache_port::drivesys.physmem.port 77640 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.cpu.dcache_port::total 79568 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.iobridge.master::drivesys.physmem.port 116400 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes) +drivesys.membus.snoops 0 # Total snoops (count) +drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram +drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram +drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram +drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram +drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram +drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram +drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram +drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -817,7 +987,7 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 1626240 # number of cpu cycles simulated +drivesys.cpu.numCycles 1626281 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed drivesys.cpu.committedInsts 36152 # Number of instructions committed @@ -835,10 +1005,10 @@ drivesys.cpu.num_fp_register_writes 0 # nu drivesys.cpu.num_mem_refs 11043 # number of memory refs drivesys.cpu.num_load_insts 7109 # Number of load instructions drivesys.cpu.num_store_insts 3934 # Number of store instructions -drivesys.cpu.num_idle_cycles 1590157.359061 # Number of idle cycles -drivesys.cpu.num_busy_cycles 36082.640939 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.022188 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.977812 # Percentage of idle cycles +drivesys.cpu.num_idle_cycles 1590238.371734 # Number of idle cycles +drivesys.cpu.num_busy_cycles 36042.628266 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.022163 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.977837 # Percentage of idle cycles drivesys.cpu.Branches 5243 # Number of branches fetched drivesys.cpu.op_class::No_OpClass 1262 3.49% 3.49% # Class of executed instruction drivesys.cpu.op_class::IntAlu 21687 59.99% 63.48% # Class of executed instruction @@ -948,7 +1118,21 @@ drivesys.tsunami.ethernet.totalRxOrn 0 # to drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post drivesys.tsunami.ethernet.postedInterrupts 4850 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.iobus.throughput 290488448 # Throughput (bytes/s) -drivesys.iobus.data_through_bus 118328 # Total data (bytes) +drivesys.iobus.trans_dist::ReadReq 5050 # Transaction distribution +drivesys.iobus.trans_dist::ReadResp 5050 # Transaction distribution +drivesys.iobus.trans_dist::WriteReq 81 # Transaction distribution +drivesys.iobus.trans_dist::WriteResp 81 # Transaction distribution +drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.cchip.pio 402 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 160 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.bridge.master::total 562 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 9700 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count_drivesys.tsunami.ethernet.dma::total 9700 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_count::total 10262 # Packet count per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.cchip.pio 1608 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.bridge.master::drivesys.tsunami.ethernet.pio 320 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.bridge.master::total 1928 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::drivesys.iobridge.slave 116400 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size_drivesys.tsunami.ethernet.dma::total 116400 # Cumulative packet size per connected master and slave (bytes) +drivesys.iobus.pkt_size::total 118328 # Cumulative packet size per connected master and slave (bytes) ---------- End Simulation Statistics ---------- |