diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-05-10 18:04:29 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-05-10 18:04:29 -0500 |
| commit | e62beaaa8ff9a87bf7523ebb18c5a7559f369eb0 (patch) | |
| tree | c00509eb4c382ab464584ec958f1122bed9bf45c /tests/quick/fs | |
| parent | 0b2d5e20d1ae2373e86786333c8f434583e265d1 (diff) | |
| download | gem5-e62beaaa8ff9a87bf7523ebb18c5a7559f369eb0.tar.xz | |
ARM: update stats for clock frequency fix.
Diffstat (limited to 'tests/quick/fs')
12 files changed, 1883 insertions, 1889 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index e36b1902c..17a6394ef 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:57 -gem5 executing on piton +gem5 compiled May 10 2012 12:36:36 +gem5 started May 10 2012 12:36:42 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2411694099500 because m5_exit instruction encountered +Exiting @ tick 911653589000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 505cf865e..96669edc4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,202 +1,202 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.411694 # Number of seconds simulated -sim_ticks 2411694099500 # Number of ticks simulated -final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.911654 # Number of seconds simulated +sim_ticks 911653589000 # Number of ticks simulated +final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 781676 # Simulator instruction rate (inst/s) -host_op_rate 1010494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30629621173 # Simulator tick rate (ticks/s) -host_mem_usage 383944 # Number of bytes of host memory used -host_seconds 78.74 # Real time elapsed on the host -sim_insts 61547057 # Number of instructions simulated -sim_ops 79563547 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 123270308 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10185232 # Number of bytes written to this memory -system.physmem.num_reads 14146769 # Number of read requests responded to by this memory -system.physmem.num_writes 869038 # Number of write requests responded to by this memory +host_inst_rate 1682178 # Simulator instruction rate (inst/s) +host_op_rate 2174115 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25299801897 # Simulator tick rate (ticks/s) +host_mem_usage 379752 # Number of bytes of host memory used +host_seconds 36.03 # Real time elapsed on the host +sim_insts 60615585 # Number of instructions simulated +sim_ops 78342060 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 50963556 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1003776 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10224784 # Number of bytes written to this memory +system.physmem.num_reads 5103504 # Number of read requests responded to by this memory +system.physmem.num_writes 869236 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 55902326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1101050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 11215646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 67117972 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127720 # number of replacements -system.l2c.tagsinuse 25547.920882 # Cycle average of tags in use -system.l2c.total_refs 1498993 # Total number of references to valid blocks. -system.l2c.sampled_refs 156132 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.600806 # Average number of references to valid blocks. +system.realview.nvmem.bw_read 75 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read 75 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total 75 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 127935 # number of replacements +system.l2c.tagsinuse 26245.835103 # Cycle average of tags in use +system.l2c.total_refs 1477463 # Total number of references to valid blocks. +system.l2c.sampled_refs 156884 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.417551 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14919.913613 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 1.146267 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.046172 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3116.154275 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 1287.935036 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 4.789000 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.017808 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2080.961372 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4136.957340 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.227660 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000017 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.047549 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.019652 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.031753 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.063125 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.389830 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 5051 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2156 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 493019 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 213171 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4123 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 368111 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 131707 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1218928 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 580462 # number of Writeback hits -system.l2c.Writeback_hits::total 580462 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 776 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 523 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 147 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 64831 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 37797 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5051 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 493019 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 278002 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4123 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 368111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 169504 # number of demand (read+write) hits -system.l2c.demand_hits::total 1321556 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5051 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2156 # number of overall hits -system.l2c.overall_hits::cpu0.inst 493019 # number of overall hits -system.l2c.overall_hits::cpu0.data 278002 # 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3492 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 791 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 531 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99048 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48785 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10289 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 108434 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 21 # 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miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843284 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.724420 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.604397 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.563454 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.003236 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.020443 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.280600 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.008110 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.013649 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.257925 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.003236 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.020443 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.280600 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005068 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.008110 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.013649 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.257925 # miss rate for overall accesses +system.l2c.occ_blocks::writebacks 16687.001530 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 1.397314 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.122168 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2780.380300 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 1123.317941 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 4.426009 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.092136 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1942.464102 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3706.633603 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.254623 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.042425 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.017140 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.029640 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.056559 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.400480 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 5294 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2199 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 485527 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 213776 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4291 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1552 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 359854 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 128180 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1200673 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 578200 # number of Writeback hits +system.l2c.Writeback_hits::total 578200 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 835 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 757 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1592 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 134 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 214 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 348 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 68011 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 101244 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5294 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2199 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 485527 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 281787 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4291 # 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number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 9928 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 9109 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 18 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 5336 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 10106 # number of ReadReq misses +system.l2c.ReadReq_misses::total 34533 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 6262 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3142 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9404 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 731 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1139 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 98092 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 50861 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 148953 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 9928 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 107201 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 18 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 5336 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 60967 # number of demand (read+write) misses +system.l2c.demand_misses::total 183486 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu0.inst 9928 # number of overall misses +system.l2c.overall_misses::cpu0.data 107201 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 18 # number of overall misses +system.l2c.overall_misses::cpu1.inst 5336 # number of overall misses +system.l2c.overall_misses::cpu1.data 60967 # number of overall misses +system.l2c.overall_misses::total 183486 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2207 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 495455 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 222885 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 4307 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1570 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 365190 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 138286 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1235206 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 578200 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 578200 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 7097 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3899 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10996 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 865 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 622 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1487 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166103 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 84094 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 250197 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2207 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 495455 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 388988 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4307 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 365190 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 222380 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1485403 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5306 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2207 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 495455 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 388988 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4307 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1570 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 365190 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 222380 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1485403 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003625 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.020038 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.040869 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.275589 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.275589 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -205,8 +205,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 111818 # number of writebacks -system.l2c.writebacks::total 111818 # number of writebacks +system.l2c.writebacks::writebacks 112464 # number of writebacks +system.l2c.writebacks::total 112464 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -216,27 +216,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9339290 # DTB read hits -system.cpu0.dtb.read_misses 5153 # DTB read misses -system.cpu0.dtb.write_hits 6907877 # DTB write hits -system.cpu0.dtb.write_misses 1048 # DTB write misses +system.cpu0.dtb.read_hits 9312139 # DTB read hits +system.cpu0.dtb.read_misses 5476 # DTB read misses +system.cpu0.dtb.write_hits 6895585 # DTB write hits +system.cpu0.dtb.write_misses 1137 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9344443 # DTB read accesses -system.cpu0.dtb.write_accesses 6908925 # DTB write accesses +system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9317615 # DTB read accesses +system.cpu0.dtb.write_accesses 6896722 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 16247167 # DTB hits -system.cpu0.dtb.misses 6201 # DTB misses -system.cpu0.dtb.accesses 16253368 # DTB accesses -system.cpu0.itb.inst_hits 34822572 # ITB inst hits -system.cpu0.itb.inst_misses 2978 # ITB inst misses +system.cpu0.dtb.hits 16207724 # DTB hits +system.cpu0.dtb.misses 6613 # DTB misses +system.cpu0.dtb.accesses 16214337 # DTB accesses +system.cpu0.itb.inst_hits 34683994 # ITB inst hits +system.cpu0.itb.inst_misses 3170 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -245,71 +245,71 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 34825550 # ITB inst accesses -system.cpu0.itb.hits 34822572 # DTB hits -system.cpu0.itb.misses 2978 # DTB misses -system.cpu0.itb.accesses 34825550 # DTB accesses -system.cpu0.numCycles 4823340800 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 34687164 # ITB inst accesses +system.cpu0.itb.hits 34683994 # DTB hits +system.cpu0.itb.misses 3170 # DTB misses +system.cpu0.itb.accesses 34687164 # DTB accesses +system.cpu0.numCycles 1823259919 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 34068123 # Number of instructions committed -system.cpu0.committedOps 44975817 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39858141 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses -system.cpu0.num_func_calls 1311755 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4519198 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39858141 # number of integer instructions -system.cpu0.num_fp_insts 4945 # number of float instructions -system.cpu0.num_int_register_reads 202125837 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42204153 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written -system.cpu0.num_mem_refs 17030949 # number of memory refs -system.cpu0.num_load_insts 9786551 # Number of load instructions -system.cpu0.num_store_insts 7244398 # Number of store instructions -system.cpu0.num_idle_cycles 4777543048.852804 # Number of idle cycles -system.cpu0.num_busy_cycles 45797751.147196 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles +system.cpu0.committedInsts 33900598 # Number of instructions committed +system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses +system.cpu0.num_func_calls 1296918 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls +system.cpu0.num_int_insts 39685287 # number of integer instructions +system.cpu0.num_fp_insts 5074 # number of float instructions +system.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read +system.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written +system.cpu0.num_mem_refs 16978573 # number of memory refs +system.cpu0.num_load_insts 9760184 # Number of load instructions +system.cpu0.num_store_insts 7218389 # Number of store instructions +system.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles +system.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles +system.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed -system.cpu0.icache.replacements 504460 # number of replacements -system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use -system.cpu0.icache.total_refs 34319175 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.962531 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.627588 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999273 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999273 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 34319175 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34319175 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34319175 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34319175 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34319175 # number of overall hits -system.cpu0.icache.overall_hits::total 34319175 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 504973 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 504973 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 504973 # number of overall misses -system.cpu0.icache.overall_misses::total 504973 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 34824148 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 34824148 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 34824148 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 34824148 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 34824148 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 34824148 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014501 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014501 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014501 # miss rate for overall accesses +system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed +system.cpu0.icache.replacements 497177 # number of replacements +system.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use +system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34187980 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34187980 # number of overall hits +system.cpu0.icache.overall_hits::total 34187980 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 497690 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 497690 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 497690 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 497690 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 497690 # number of overall misses +system.cpu0.icache.overall_misses::total 497690 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 34685670 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 34685670 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 34685670 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -318,60 +318,60 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 24728 # number of writebacks -system.cpu0.icache.writebacks::total 24728 # number of writebacks +system.cpu0.icache.writebacks::writebacks 26062 # number of writebacks +system.cpu0.icache.writebacks::total 26062 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 380107 # number of replacements -system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14708289 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.643076 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 385595 # number of replacements +system.cpu0.dcache.tagsinuse 475.569441 # Cycle average of tags in use +system.cpu0.dcache.total_refs 14667576 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.716402 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.936946 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.936946 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7803298 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7803298 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6534060 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6534060 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172314 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 174866 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 14337358 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14337358 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 14337358 # number of overall hits -system.cpu0.dcache.overall_hits::total 14337358 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 237350 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9878 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7293 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 420930 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 420930 # number of overall misses -system.cpu0.dcache.overall_misses::total 420930 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8040648 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8040648 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6717640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6717640 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182192 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182159 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14758288 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14758288 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14758288 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14758288 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029519 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027328 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054218 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040036 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028522 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028522 # miss rate for overall accesses +system.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.928847 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 6519223 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 6519223 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 172927 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175483 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 14295015 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 14295015 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 14295015 # number of overall hits +system.cpu0.dcache.overall_hits::total 14295015 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses +system.cpu0.dcache.overall_misses::total 426577 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,32 +380,32 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 339627 # number of writebacks -system.cpu0.dcache.writebacks::total 339627 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks +system.cpu0.dcache.writebacks::total 342703 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6258240 # DTB read hits -system.cpu1.dtb.read_misses 2159 # DTB read misses -system.cpu1.dtb.write_hits 4713968 # DTB write hits -system.cpu1.dtb.write_misses 1181 # DTB write misses +system.cpu1.dtb.read_hits 6036043 # DTB read hits +system.cpu1.dtb.read_misses 1895 # DTB read misses +system.cpu1.dtb.write_hits 4565126 # DTB write hits +system.cpu1.dtb.write_misses 1147 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6260399 # DTB read accesses -system.cpu1.dtb.write_accesses 4715149 # DTB write accesses +system.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6037938 # DTB read accesses +system.cpu1.dtb.write_accesses 4566273 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10972208 # DTB hits -system.cpu1.dtb.misses 3340 # DTB misses -system.cpu1.dtb.accesses 10975548 # DTB accesses -system.cpu1.itb.inst_hits 27739473 # ITB inst hits -system.cpu1.itb.inst_misses 1388 # ITB inst misses +system.cpu1.dtb.hits 10601169 # DTB hits +system.cpu1.dtb.misses 3042 # DTB misses +system.cpu1.dtb.accesses 10604211 # DTB accesses +system.cpu1.itb.inst_hits 26944447 # ITB inst hits +system.cpu1.itb.inst_misses 1203 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -414,71 +414,71 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 27740861 # ITB inst accesses -system.cpu1.itb.hits 27739473 # DTB hits -system.cpu1.itb.misses 1388 # DTB misses -system.cpu1.itb.accesses 27740861 # DTB accesses -system.cpu1.numCycles 4822838236 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 26945650 # ITB inst accesses +system.cpu1.itb.hits 26944447 # DTB hits +system.cpu1.itb.misses 1203 # DTB misses +system.cpu1.itb.accesses 26945650 # DTB accesses +system.cpu1.numCycles 1822760078 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 27478934 # Number of instructions committed -system.cpu1.committedOps 34587730 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 30998282 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses -system.cpu1.num_func_calls 758024 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3403316 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30998282 # number of integer instructions -system.cpu1.num_fp_insts 5772 # number of float instructions -system.cpu1.num_int_register_reads 156835224 # number of times the integer registers were read -system.cpu1.num_int_register_writes 33469234 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written -system.cpu1.num_mem_refs 11415851 # number of memory refs -system.cpu1.num_load_insts 6479004 # Number of load instructions -system.cpu1.num_store_insts 4936847 # Number of store instructions -system.cpu1.num_idle_cycles 4787960139.182108 # Number of idle cycles -system.cpu1.num_busy_cycles 34878096.817892 # Number of busy cycles -system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles +system.cpu1.committedInsts 26714987 # Number of instructions committed +system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses +system.cpu1.num_func_calls 723750 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls +system.cpu1.num_int_insts 30087808 # number of integer instructions +system.cpu1.num_fp_insts 5643 # number of float instructions +system.cpu1.num_int_register_reads 152234781 # number of times the integer registers were read +system.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written +system.cpu1.num_mem_refs 11031013 # number of memory refs +system.cpu1.num_load_insts 6247466 # Number of load instructions +system.cpu1.num_store_insts 4783547 # Number of store instructions +system.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles +system.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles +system.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.981453 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed -system.cpu1.icache.replacements 374408 # number of replacements -system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use -system.cpu1.icache.total_refs 27365609 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 374920 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 72.990529 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69956153000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.143079 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.972936 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.972936 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 27365609 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 27365609 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 27365609 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 27365609 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 27365609 # number of overall hits -system.cpu1.icache.overall_hits::total 27365609 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 374922 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 374922 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 374922 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 374922 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 374922 # number of overall misses -system.cpu1.icache.overall_misses::total 374922 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 27740531 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 27740531 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 27740531 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 27740531 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 27740531 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 27740531 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013515 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013515 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013515 # miss rate for overall accesses +system.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed +system.cpu1.icache.replacements 365832 # number of replacements +system.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use +system.cpu1.icache.total_refs 26579068 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 475.430525 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.928575 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.928575 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 26579068 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 26579068 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 26579068 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 26579068 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 26579068 # number of overall hits +system.cpu1.icache.overall_hits::total 26579068 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 366344 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 366344 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 366344 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 366344 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 366344 # number of overall misses +system.cpu1.icache.overall_misses::total 366344 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 26945412 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 26945412 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 26945412 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 26945412 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,60 +487,60 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 13905 # number of writebacks -system.cpu1.icache.writebacks::total 13905 # number of writebacks +system.cpu1.icache.writebacks::writebacks 12806 # number of writebacks +system.cpu1.icache.writebacks::total 12806 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 247435 # number of replacements -system.cpu1.dcache.tagsinuse 444.903487 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9876841 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 247806 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.857150 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 69253216000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 444.903487 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.868952 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.868952 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 5955982 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5955982 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3777044 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3777044 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 59593 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 60090 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9733026 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9733026 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9733026 # number of overall hits -system.cpu1.dcache.overall_hits::total 9733026 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 165800 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 165800 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 111467 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10725 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10198 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 277267 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 277267 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 277267 # number of overall misses -system.cpu1.dcache.overall_misses::total 277267 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 6121782 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6121782 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3888511 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3888511 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 70318 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 70288 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 10010293 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10010293 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 10010293 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10010293 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027084 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028666 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152521 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.145089 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027698 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027698 # miss rate for overall accesses +system.cpu1.dcache.replacements 240038 # number of replacements +system.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use +system.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.568554 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.761013 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 5740038 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 5740038 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3634687 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3634687 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56514 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 56514 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 57060 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 57060 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 9374725 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 9374725 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 9374725 # number of overall hits +system.cpu1.dcache.overall_hits::total 9374725 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 161066 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 161066 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108913 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10616 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 10616 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10014 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses +system.cpu1.dcache.overall_misses::total 269979 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -549,8 +549,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 202202 # number of writebacks -system.cpu1.dcache.writebacks::total 202202 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks +system.cpu1.dcache.writebacks::total 196629 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal Binary files differindex ac162c148..17e9c9abf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index d76ea9eaa..4b3b38463 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:57 -gem5 executing on piton +gem5 compiled May 10 2012 12:36:36 +gem5 started May 10 2012 12:36:42 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2332316587000 because m5_exit instruction encountered +Exiting @ tick 2332330037000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 75b897a18..e1058fc4f 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332317 # Number of seconds simulated -sim_ticks 2332316587000 # Number of ticks simulated -final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332330 # Number of seconds simulated +sim_ticks 2332330037000 # Number of ticks simulated +final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 864582 # Simulator instruction rate (inst/s) -host_op_rate 1116533 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34025972839 # Simulator tick rate (ticks/s) -host_mem_usage 383900 # Number of bytes of host memory used -host_seconds 68.55 # Real time elapsed on the host -sim_insts 59262896 # Number of instructions simulated -sim_ops 76532951 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 122663536 # Number of bytes read from this memory -system.physmem.bytes_inst_read 941280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9577800 # Number of bytes written to this memory -system.physmem.num_reads 14137126 # Number of read requests responded to by this memory -system.physmem.num_writes 856485 # Number of write requests responded to by this memory +host_inst_rate 1538399 # Simulator instruction rate (inst/s) +host_op_rate 1985816 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60412799239 # Simulator tick rate (ticks/s) +host_mem_usage 379756 # Number of bytes of host memory used +host_seconds 38.61 # Real time elapsed on the host +sim_insts 59392246 # Number of instructions simulated +sim_ops 76665494 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 122661296 # Number of bytes read from this memory +system.physmem.bytes_inst_read 941920 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9590216 # Number of bytes written to this memory +system.physmem.num_reads 14137091 # Number of read requests responded to by this memory +system.physmem.num_writes 856679 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52593004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 403582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4106561 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56699565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 52591740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 403854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 4111861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56703601 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -30,98 +30,98 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 9 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 9 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 116822 # number of replacements -system.l2c.tagsinuse 24240.388395 # Cycle average of tags in use -system.l2c.total_refs 1520830 # Total number of references to valid blocks. -system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. +system.l2c.replacements 117012 # number of replacements +system.l2c.tagsinuse 24288.656748 # Cycle average of tags in use +system.l2c.total_refs 1527554 # Total number of references to valid blocks. +system.l2c.sampled_refs 146810 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.404972 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 13639.466229 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5344.680068 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 13693.996987 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 7.872000 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 1.975558 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5248.163956 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5336.648246 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.208954 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits -system.l2c.Writeback_hits::total 604613 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.080081 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.081431 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.370615 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7515 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 835264 # 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number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses +system.l2c.ReadExReq_hits::cpu.data 106156 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106156 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 7515 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 835264 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 463541 # number of demand (read+write) hits +system.l2c.demand_hits::total 1309459 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 7515 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3139 # number of overall hits +system.l2c.overall_hits::cpu.inst 835264 # number of overall hits +system.l2c.overall_hits::cpu.data 463541 # number of overall hits +system.l2c.overall_hits::total 1309459 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14304 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 17465 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31808 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 141050 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 141050 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14304 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 158515 # number of demand (read+write) misses +system.l2c.demand_misses::total 172858 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 15 # number of overall misses +system.l2c.overall_misses::cpu.inst 14304 # number of overall misses +system.l2c.overall_misses::cpu.data 158515 # number of overall misses +system.l2c.overall_misses::total 172858 # number of overall misses +system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 849568 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 374850 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1235111 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 605735 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 605735 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 849568 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 622056 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1482317 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 849568 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 622056 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1482317 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.003183 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.004756 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016837 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.002520 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.002536 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016896 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.570577 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.003183 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.004756 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016837 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.254824 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.003183 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.004756 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016837 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.254824 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -130,8 +130,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 102531 # number of writebacks -system.l2c.writebacks::total 102531 # number of writebacks +system.l2c.writebacks::writebacks 102725 # number of writebacks +system.l2c.writebacks::total 102725 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -141,26 +141,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14940568 # DTB read hits -system.cpu.dtb.read_misses 7288 # DTB read misses -system.cpu.dtb.write_hits 11198206 # DTB write hits -system.cpu.dtb.write_misses 2199 # DTB write misses +system.cpu.dtb.read_hits 14971229 # DTB read hits +system.cpu.dtb.read_misses 7293 # DTB read misses +system.cpu.dtb.write_hits 11217018 # DTB write hits +system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 189 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14947856 # DTB read accesses -system.cpu.dtb.write_accesses 11200405 # DTB write accesses +system.cpu.dtb.read_accesses 14978522 # DTB read accesses +system.cpu.dtb.write_accesses 11219199 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26138774 # DTB hits -system.cpu.dtb.misses 9487 # DTB misses -system.cpu.dtb.accesses 26148261 # DTB accesses -system.cpu.itb.inst_hits 60273909 # ITB inst hits +system.cpu.dtb.hits 26188247 # DTB hits +system.cpu.dtb.misses 9474 # DTB misses +system.cpu.dtb.accesses 26197721 # DTB accesses +system.cpu.itb.inst_hits 60403303 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -177,64 +177,64 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60278380 # ITB inst accesses -system.cpu.itb.hits 60273909 # DTB hits +system.cpu.itb.inst_accesses 60407774 # ITB inst accesses +system.cpu.itb.hits 60403303 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60278380 # DTB accesses -system.cpu.numCycles 4664556206 # number of cpu cycles simulated +system.cpu.itb.accesses 60407774 # DTB accesses +system.cpu.numCycles 4664583062 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59262896 # Number of instructions committed -system.cpu.committedOps 76532951 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68161195 # Number of integer alu accesses +system.cpu.committedInsts 59392246 # Number of instructions committed +system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1971944 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7636089 # number of instructions that are conditional controls -system.cpu.num_int_insts 68161195 # number of integer instructions +system.cpu.num_func_calls 1972385 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls +system.cpu.num_int_insts 68281415 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 345365700 # number of times the integer registers were read -system.cpu.num_int_register_writes 72877714 # number of times the integer registers were written +system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read +system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27310787 # number of memory refs -system.cpu.num_load_insts 15607076 # Number of load instructions -system.cpu.num_store_insts 11703711 # Number of store instructions -system.cpu.num_idle_cycles 4586920130.978250 # Number of idle cycles -system.cpu.num_busy_cycles 77636075.021750 # Number of busy cycles -system.cpu.not_idle_fraction 0.016644 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983356 # Percentage of idle cycles +system.cpu.num_mem_refs 27361692 # number of memory refs +system.cpu.num_load_insts 15639569 # Number of load instructions +system.cpu.num_store_insts 11722123 # Number of store instructions +system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles +system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles +system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983328 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82751 # number of quiesce instructions executed -system.cpu.icache.replacements 847054 # number of replacements -system.cpu.icache.tagsinuse 511.678552 # Cycle average of tags in use -system.cpu.icache.total_refs 59429103 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.117375 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5705462000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed +system.cpu.icache.replacements 850612 # number of replacements +system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use +system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59429103 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59429103 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59429103 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59429103 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59429103 # number of overall hits -system.cpu.icache.overall_hits::total 59429103 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses -system.cpu.icache.overall_misses::total 847566 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60276669 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60276669 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60276669 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60276669 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60276669 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60276669 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses +system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits +system.cpu.icache.overall_hits::total 59554939 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses +system.cpu.icache.overall_misses::total 851124 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -243,57 +243,57 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 44721 # number of writebacks -system.cpu.icache.writebacks::total 44721 # number of writebacks +system.cpu.icache.writebacks::writebacks 44595 # number of writebacks +system.cpu.icache.writebacks::total 44595 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 622134 # number of replacements +system.cpu.dcache.replacements 623347 # number of replacements system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.total_refs 23580072 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.870752 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13150368 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13150368 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9943632 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9943632 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23094000 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23094000 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23094000 # number of overall hits -system.cpu.dcache.overall_hits::total 23094000 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses -system.cpu.dcache.overall_misses::total 614445 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13514916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13514916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10193529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10193529 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23708445 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23708445 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23708445 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23708445 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits +system.cpu.dcache.overall_hits::total 23142161 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses +system.cpu.dcache.overall_misses::total 615615 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,8 +302,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks -system.cpu.dcache.writebacks::total 559892 # number of writebacks +system.cpu.dcache.writebacks::writebacks 561140 # number of writebacks +system.cpu.dcache.writebacks::total 561140 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal Binary files differindex eabb40181..c810346c6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index ae01846e4..d6c8fa18c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:58 -gem5 executing on piton +gem5 compiled May 10 2012 12:36:36 +gem5 started May 10 2012 12:36:42 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2669611225000 because m5_exit instruction encountered +Exiting @ tick 1169707043000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 0ac70eccc..4dc707863 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,268 +1,268 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.669611 # Number of seconds simulated -sim_ticks 2669611225000 # Number of ticks simulated -final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.169707 # Number of seconds simulated +sim_ticks 1169707043000 # Number of ticks simulated +final_tick 1169707043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 280373 # Simulator instruction rate (inst/s) -host_op_rate 358676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12211141498 # Simulator tick rate (ticks/s) -host_mem_usage 385748 # Number of bytes of host memory used -host_seconds 218.62 # Real time elapsed on the host -sim_insts 61295282 # Number of instructions simulated -sim_ops 78413979 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 134334820 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1003520 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10194256 # Number of bytes written to this memory -system.physmem.num_reads 15523876 # Number of read requests responded to by this memory -system.physmem.num_writes 869239 # Number of write requests responded to by this memory +host_inst_rate 754175 # Simulator instruction rate (inst/s) +host_op_rate 964493 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 14598169556 # Simulator tick rate (ticks/s) +host_mem_usage 379804 # Number of bytes of host memory used +host_seconds 80.13 # Real time elapsed on the host +sim_insts 60429704 # Number of instructions simulated +sim_ops 77281862 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 61898788 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1004992 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10078928 # Number of bytes written to this memory +system.physmem.num_reads 6478591 # Number of read requests responded to by this memory +system.physmem.num_writes 867017 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 50319994 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 375905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3818629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 54138623 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 52918197 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 859183 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 8616626 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 61534823 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read 68 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory system.realview.nvmem.num_reads 17 # Number of read requests responded to by this memory system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127749 # number of replacements -system.l2c.tagsinuse 26172.513447 # Cycle average of tags in use -system.l2c.total_refs 1540413 # Total number of references to valid blocks. -system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.801684 # Average number of references to valid blocks. +system.realview.nvmem.bw_read 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total 58 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 125934 # number of replacements +system.l2c.tagsinuse 27532.100282 # Cycle average of tags in use +system.l2c.total_refs 1500548 # Total number of references to valid blocks. +system.l2c.sampled_refs 155551 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.646663 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 15197.869082 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2680.486070 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3670.979881 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2441.904061 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2173.000034 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 17789.012398 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 1.363432 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.117594 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2294.743571 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2778.537805 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 5.252408 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.023319 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2406.434925 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2256.614830 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.271439 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.040901 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.056015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.035015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.042397 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000080 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.037260 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.033157 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.399361 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1502 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40151.618184 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40050.655795 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40222.222222 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40272.541542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40120.061509 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -446,27 +443,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7857580 # DTB read hits -system.cpu0.dtb.read_misses 1898 # DTB read misses -system.cpu0.dtb.write_hits 6224259 # DTB write hits -system.cpu0.dtb.write_misses 1143 # DTB write misses +system.cpu0.dtb.read_hits 7070142 # DTB read hits +system.cpu0.dtb.read_misses 3739 # DTB read misses +system.cpu0.dtb.write_hits 5655287 # DTB write hits +system.cpu0.dtb.write_misses 802 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1404 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 1791 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 79 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 191 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7859478 # DTB read accesses -system.cpu0.dtb.write_accesses 6225402 # DTB write accesses +system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7073881 # DTB read accesses +system.cpu0.dtb.write_accesses 5656089 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14081839 # DTB hits -system.cpu0.dtb.misses 3041 # DTB misses -system.cpu0.dtb.accesses 14084880 # DTB accesses -system.cpu0.itb.inst_hits 35747911 # ITB inst hits -system.cpu0.itb.inst_misses 1204 # ITB inst misses +system.cpu0.dtb.hits 12725429 # DTB hits +system.cpu0.dtb.misses 4541 # DTB misses +system.cpu0.dtb.accesses 12729970 # DTB accesses +system.cpu0.itb.inst_hits 29439632 # ITB inst hits +system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -475,80 +472,80 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1262 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 35749115 # ITB inst accesses -system.cpu0.itb.hits 35747911 # DTB hits -system.cpu0.itb.misses 1204 # DTB misses -system.cpu0.itb.accesses 35749115 # DTB accesses -system.cpu0.numCycles 5337805216 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 29441837 # ITB inst accesses +system.cpu0.itb.hits 29439632 # DTB hits +system.cpu0.itb.misses 2205 # DTB misses +system.cpu0.itb.accesses 29441837 # DTB accesses +system.cpu0.numCycles 2339414086 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 35373502 # Number of instructions committed -system.cpu0.committedOps 43969024 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses -system.cpu0.num_func_calls 977479 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4455595 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39881498 # number of integer instructions -system.cpu0.num_fp_insts 4107 # number of float instructions -system.cpu0.num_int_register_reads 225043856 # number of times the integer registers were read -system.cpu0.num_int_register_writes 43158045 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3851 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 256 # number of times the floating registers were written -system.cpu0.num_mem_refs 14677999 # number of memory refs -system.cpu0.num_load_insts 8148547 # Number of load instructions -system.cpu0.num_store_insts 6529452 # Number of store instructions -system.cpu0.num_idle_cycles 5107410767.568501 # Number of idle cycles -system.cpu0.num_busy_cycles 230394448.431500 # Number of busy cycles -system.cpu0.not_idle_fraction 0.043163 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.956837 # Percentage of idle cycles +system.cpu0.committedInsts 28747266 # Number of instructions committed +system.cpu0.committedOps 37085213 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33031535 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses +system.cpu0.num_func_calls 1116936 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4321526 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33031535 # number of integer instructions +system.cpu0.num_fp_insts 3860 # number of float instructions +system.cpu0.num_int_register_reads 189616194 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36089294 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written +system.cpu0.num_mem_refs 13393398 # number of memory refs +system.cpu0.num_load_insts 7407664 # Number of load instructions +system.cpu0.num_store_insts 5985734 # Number of store instructions +system.cpu0.num_idle_cycles 2203122575.338117 # Number of idle cycles +system.cpu0.num_busy_cycles 136291510.661883 # Number of busy cycles +system.cpu0.not_idle_fraction 0.058259 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.941741 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 38525 # number of quiesce instructions executed -system.cpu0.icache.replacements 380070 # number of replacements -system.cpu0.icache.tagsinuse 510.849663 # Cycle average of tags in use -system.cpu0.icache.total_refs 35367310 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 380582 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 92.929539 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 35367310 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 35367310 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 35367310 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 35367310 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 35367310 # number of overall hits -system.cpu0.icache.overall_hits::total 35367310 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 380584 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 380584 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 380584 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 380584 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 380584 # number of overall misses -system.cpu0.icache.overall_misses::total 380584 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651447000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5651447000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5651447000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5651447000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5651447000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5651447000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 35747894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 35747894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.407752 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.407752 # average overall miss latency +system.cpu0.kern.inst.quiesce 46688 # number of quiesce instructions executed +system.cpu0.icache.replacements 408172 # number of replacements +system.cpu0.icache.tagsinuse 509.512645 # Cycle average of tags in use +system.cpu0.icache.total_refs 29030930 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 408684 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.035152 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 74928815000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.512645 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995142 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995142 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29030930 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29030930 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29030930 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29030930 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29030930 # number of overall hits +system.cpu0.icache.overall_hits::total 29030930 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 408685 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 408685 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 408685 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 408685 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 408685 # number of overall misses +system.cpu0.icache.overall_misses::total 408685 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6059464500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6059464500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 6059464500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6059464500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 6059464500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6059464500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29439615 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29439615 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29439615 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29439615 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29439615 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29439615 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013882 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013882 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013882 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14826.735750 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14826.735750 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -557,102 +554,102 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks -system.cpu0.icache.writebacks::total 12960 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380584 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 380584 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 380584 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 380584 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 380584 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 380584 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509193500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509193500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509193500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4509193500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509193500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4509193500 # number of overall MSHR miss cycles +system.cpu0.icache.writebacks::writebacks 16458 # number of writebacks +system.cpu0.icache.writebacks::total 16458 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 408685 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 408685 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 408685 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 408685 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 408685 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 408685 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4832163500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4832163500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4832163500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4832163500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4832163500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4832163500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.090041 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013882 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11823.686947 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 334596 # number of replacements -system.cpu0.dcache.tagsinuse 450.118379 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12875674 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 335831 # number of replacements +system.cpu0.dcache.tagsinuse 404.122879 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12265513 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 336343 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.467276 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 450.118379 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.879137 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7428609 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5172633 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126778 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127996 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12601242 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12601242 # number of overall hits -system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 217330 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 155538 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9456 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8189 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 372868 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 372868 # number of overall misses -system.cpu0.dcache.overall_misses::total 372868 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3330686000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3330686000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6317758500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6317758500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100249000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100249000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 70240000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 70240000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 9648444500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 9648444500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 9648444500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 9648444500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7645939 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5328171 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 136234 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 136185 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028424 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029192 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.069410 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.060131 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028739 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028739 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15325.477385 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40618.745901 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 404.122879 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.789302 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.789302 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6596660 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6596660 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5349249 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5349249 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147717 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147717 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149695 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149695 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11945909 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11945909 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11945909 # number of overall hits +system.cpu0.dcache.overall_hits::total 11945909 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 231189 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 231189 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 142616 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 142616 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9505 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9505 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 373805 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 373805 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 373805 # number of overall misses +system.cpu0.dcache.overall_misses::total 373805 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3541904000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3541904000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5075999000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5075999000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104931000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 104931000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 68264000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 68264000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8617903000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8617903000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8617903000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8617903000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827849 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6827849 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5491865 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5491865 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157222 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157222 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157159 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12319714 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12319714 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12319714 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12319714 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033860 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025969 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060456 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030342 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.030342 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15320.382890 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35592.072418 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11039.558127 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9145.766345 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23054.541807 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,80 +658,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks -system.cpu0.dcache.writebacks::total 294891 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8184 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 8184 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 372868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 372868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 372868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 372868 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678673500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678673500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5851029000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5851029000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71881000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71881000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45691000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45691000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8529702500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8529702500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8529702500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 8529702500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9171180500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9171180500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 40129379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 40129379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 49300560000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 49300560000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069410 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.060095 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7601.628596 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5582.966764 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 287163 # number of writebacks +system.cpu0.dcache.writebacks::total 287163 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 231189 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 231189 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 142616 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 142616 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9505 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9505 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7461 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7461 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 373805 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 373805 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7496285500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7496285500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7496285500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7496285500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423748000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 822757000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 822757000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11246505000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11246505000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033860 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025969 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060456 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047474 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030342 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12319.946018 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32591.360717 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.558127 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6149.443774 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20054.000080 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7762498 # DTB read hits -system.cpu1.dtb.read_misses 5432 # DTB read misses -system.cpu1.dtb.write_hits 5411649 # DTB write hits -system.cpu1.dtb.write_misses 1096 # DTB write misses +system.cpu1.dtb.read_hits 8313009 # DTB read hits +system.cpu1.dtb.read_misses 3663 # DTB read misses +system.cpu1.dtb.write_hits 5829499 # DTB write hits +system.cpu1.dtb.write_misses 1439 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2346 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1967 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 166 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 136 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 261 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7767930 # DTB read accesses -system.cpu1.dtb.write_accesses 5412745 # DTB write accesses +system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 8316672 # DTB read accesses +system.cpu1.dtb.write_accesses 5830938 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13174147 # DTB hits -system.cpu1.dtb.misses 6528 # DTB misses -system.cpu1.dtb.accesses 13180675 # DTB accesses -system.cpu1.itb.inst_hits 26848300 # ITB inst hits -system.cpu1.itb.inst_misses 3154 # ITB inst misses +system.cpu1.dtb.hits 14142508 # DTB hits +system.cpu1.dtb.misses 5102 # DTB misses +system.cpu1.dtb.accesses 14147610 # DTB accesses +system.cpu1.itb.inst_hits 32286240 # ITB inst hits +system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -743,80 +737,80 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1544 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 26851454 # ITB inst accesses -system.cpu1.itb.hits 26848300 # DTB hits -system.cpu1.itb.misses 3154 # DTB misses -system.cpu1.itb.accesses 26851454 # DTB accesses -system.cpu1.numCycles 5339222450 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 32288411 # ITB inst accesses +system.cpu1.itb.hits 32286240 # DTB hits +system.cpu1.itb.misses 2171 # DTB misses +system.cpu1.itb.accesses 32288411 # DTB accesses +system.cpu1.numCycles 2338003468 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 25921780 # Number of instructions committed -system.cpu1.committedOps 34444955 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 31033271 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses -system.cpu1.num_func_calls 1093852 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3472619 # number of instructions that are conditional controls -system.cpu1.num_int_insts 31033271 # number of integer instructions -system.cpu1.num_fp_insts 5714 # number of float instructions -system.cpu1.num_int_register_reads 181157292 # number of times the integer registers were read -system.cpu1.num_int_register_writes 32585326 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3770 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1948 # number of times the floating registers were written -system.cpu1.num_mem_refs 13796846 # number of memory refs -system.cpu1.num_load_insts 8139021 # Number of load instructions -system.cpu1.num_store_insts 5657825 # Number of store instructions -system.cpu1.num_idle_cycles 4950307196.068146 # Number of idle cycles -system.cpu1.num_busy_cycles 388915253.931854 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072841 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927159 # Percentage of idle cycles +system.cpu1.committedInsts 31682438 # Number of instructions committed +system.cpu1.committedOps 40196649 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 36868206 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses +system.cpu1.num_func_calls 909270 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3487065 # number of instructions that are conditional controls +system.cpu1.num_int_insts 36868206 # number of integer instructions +system.cpu1.num_fp_insts 6793 # number of float instructions +system.cpu1.num_int_register_reads 210764243 # number of times the integer registers were read +system.cpu1.num_int_register_writes 38547083 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written +system.cpu1.num_mem_refs 14680299 # number of memory refs +system.cpu1.num_load_insts 8634860 # Number of load instructions +system.cpu1.num_store_insts 6045439 # Number of store instructions +system.cpu1.num_idle_cycles 1858954745.472398 # Number of idle cycles +system.cpu1.num_busy_cycles 479048722.527602 # Number of busy cycles +system.cpu1.not_idle_fraction 0.204896 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.795104 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53838 # number of quiesce instructions executed -system.cpu1.icache.replacements 508221 # number of replacements -system.cpu1.icache.tagsinuse 497.375159 # Cycle average of tags in use -system.cpu1.icache.total_refs 26339563 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 51.774827 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 26339563 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26339563 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26339563 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26339563 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26339563 # number of overall hits -system.cpu1.icache.overall_hits::total 26339563 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses -system.cpu1.icache.overall_misses::total 508733 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436443000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7436443000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7436443000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7436443000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7436443000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7436443000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 26848296 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 26848296 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 26848296 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 26848296 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 26848296 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.575428 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.575428 # average overall miss latency +system.cpu1.kern.inst.quiesce 43911 # number of quiesce instructions executed +system.cpu1.icache.replacements 454317 # number of replacements +system.cpu1.icache.tagsinuse 478.423780 # Cycle average of tags in use +system.cpu1.icache.total_refs 31831407 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454829 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.985438 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 91926225000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.423780 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934421 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934421 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31831407 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31831407 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31831407 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31831407 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31831407 # number of overall hits +system.cpu1.icache.overall_hits::total 31831407 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 454829 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 454829 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 454829 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 454829 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 454829 # number of overall misses +system.cpu1.icache.overall_misses::total 454829 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6679957000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6679957000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6679957000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6679957000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6679957000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6679957000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32286236 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32286236 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32286236 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32286236 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32286236 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32286236 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014087 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014087 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014087 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14686.743809 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14686.743809 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -825,102 +819,102 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks -system.cpu1.icache.writebacks::total 27998 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908061000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908061000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908061000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5908061000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908061000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5908061000 # number of overall MSHR miss cycles +system.cpu1.icache.writebacks::writebacks 19149 # number of writebacks +system.cpu1.icache.writebacks::total 19149 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454829 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 454829 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 454829 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 454829 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 454829 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 454829 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5314262500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5314262500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5314262500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5314262500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5314262500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5314262500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.284375 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014087 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11684.088965 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 295754 # number of replacements -system.cpu1.dcache.tagsinuse 467.166428 # Cycle average of tags in use -system.cpu1.dcache.total_refs 11737110 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.616797 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 467.166428 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 6345292 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6345292 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5152611 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5152611 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11497903 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11497903 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11497903 # number of overall hits -system.cpu1.dcache.overall_hits::total 11497903 # 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average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24134.585035 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -929,50 +923,50 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks -system.cpu1.dcache.writebacks::total 253551 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # 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mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.480650 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.421476 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.875532 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 254584 # number of writebacks +system.cpu1.dcache.writebacks::total 254584 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172105 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 172105 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 150416 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 150416 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11123 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11123 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9710 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9710 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 322521 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 322521 # 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number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176267834000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024175 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030209 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119732 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104604 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026659 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11503.175387 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32153.756914 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8199.721298 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4583.110196 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21134.107546 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -991,10 +985,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550616164273 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550616164273 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550616164273 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550616164273 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal Binary files differindex 7e7f32a27..4f02e6414 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 480141f03..db3a98367 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:58 -gem5 executing on piton +gem5 compiled May 10 2012 12:36:36 +gem5 started May 10 2012 12:36:42 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2591441692000 because m5_exit instruction encountered +Exiting @ tick 2591419000000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 4b750a42d..c192aecc6 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,26 +1,26 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.591442 # Number of seconds simulated -sim_ticks 2591441692000 # Number of ticks simulated -final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.591419 # Number of seconds simulated +sim_ticks 2591419000000 # Number of ticks simulated +final_tick 2591419000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 302887 # Simulator instruction rate (inst/s) -host_op_rate 386981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13286578938 # Simulator tick rate (ticks/s) -host_mem_usage 384192 # Number of bytes of host memory used -host_seconds 195.04 # Real time elapsed on the host -sim_insts 59075703 # Number of instructions simulated -sim_ops 75477535 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 133655408 # Number of bytes read from this memory -system.physmem.bytes_inst_read 949920 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9634312 # Number of bytes written to this memory -system.physmem.num_reads 15513098 # Number of read requests responded to by this memory -system.physmem.num_writes 857428 # Number of write requests responded to by this memory +host_inst_rate 632591 # Simulator instruction rate (inst/s) +host_op_rate 807921 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 27699122939 # Simulator tick rate (ticks/s) +host_mem_usage 380048 # Number of bytes of host memory used +host_seconds 93.56 # Real time elapsed on the host +sim_insts 59182652 # Number of instructions simulated +sim_ops 75585847 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 133632176 # Number of bytes read from this memory +system.physmem.bytes_inst_read 955744 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9600072 # Number of bytes written to this memory +system.physmem.num_reads 15512735 # Number of read requests responded to by this memory +system.physmem.num_writes 856893 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51575696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 366560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3717742 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55293438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 51567182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 368811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3704562 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 55271744 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -30,131 +30,131 @@ system.realview.nvmem.num_other 0 # Nu system.realview.nvmem.bw_read 8 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 117809 # number of replacements -system.l2c.tagsinuse 24929.234619 # Cycle average of tags in use -system.l2c.total_refs 1535239 # Total number of references to valid blocks. -system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. -system.l2c.avg_refs 10.464518 # Average number of references to valid blocks. +system.l2c.replacements 117210 # number of replacements +system.l2c.tagsinuse 24850.634634 # Cycle average of tags in use +system.l2c.total_refs 1536782 # Total number of references to valid blocks. +system.l2c.sampled_refs 146347 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.500946 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 14588.908290 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.970411 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 5159.303507 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 5173.088486 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.222609 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 14582.980264 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 6.964045 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.968003 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5130.485110 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5129.237211 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.222519 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.078725 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.078935 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.380390 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 8825 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 837469 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 360891 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 610049 # number of Writeback hits -system.l2c.Writeback_hits::total 610049 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.078285 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.078266 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.379191 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8714 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3541 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 839785 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 361146 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1213186 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 611793 # number of Writeback hits +system.l2c.Writeback_hits::total 611793 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 106473 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 8825 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3670 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 837469 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 467364 # number of demand (read+write) hits -system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 8825 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3670 # number of overall hits -system.l2c.overall_hits::cpu.inst 837469 # number of overall hits -system.l2c.overall_hits::cpu.data 467364 # number of overall hits -system.l2c.overall_hits::total 1317328 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 14429 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 17256 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 140928 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 14429 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 158184 # number of demand (read+write) misses -system.l2c.demand_misses::total 172650 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu.inst 14429 # number of overall misses -system.l2c.overall_misses::cpu.data 158184 # number of overall misses -system.l2c.overall_misses::total 172650 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 1250000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 676000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 753120500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 899469500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1654516000 # number of ReadReq miss cycles +system.l2c.ReadExReq_hits::cpu.data 106840 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106840 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 8714 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3541 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 839785 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 467986 # number of demand (read+write) hits +system.l2c.demand_hits::total 1320026 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 8714 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3541 # number of overall hits +system.l2c.overall_hits::cpu.inst 839785 # number of overall hits +system.l2c.overall_hits::cpu.data 467986 # number of overall hits +system.l2c.overall_hits::total 1320026 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 22 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14520 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 16989 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31543 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2871 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2871 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 140746 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140746 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 22 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14520 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 157735 # number of demand (read+write) misses +system.l2c.demand_misses::total 172289 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 22 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu.inst 14520 # number of overall misses +system.l2c.overall_misses::cpu.data 157735 # number of overall misses +system.l2c.overall_misses::total 172289 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 1144000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 624000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 758001000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 885358500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1645127500 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7338006500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7338006500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 1250000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 676000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 753120500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8237476000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8992522500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 1250000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 676000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 753120500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8237476000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8992522500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 8849 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 3683 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 851898 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 378147 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 610049 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 247401 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 8849 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 3683 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 851898 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 625548 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 8849 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 3683 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 851898 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 625548 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002712 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003530 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.016937 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.045633 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.569634 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.002712 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.003530 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.016937 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.252873 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.002712 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.003530 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.016937 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.252873 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52083.333333 # average ReadReq miss latency +system.l2c.ReadExReq_miss_latency::cpu.data 7328827500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7328827500 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131544749000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131809589000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31207839500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31207839500 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162759439500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163024279500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.045633 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569634 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.252873 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.252873 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40194.469471 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.266778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40203.512397 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.855073 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -253,26 +253,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14970649 # DTB read hits -system.cpu.dtb.read_misses 7343 # DTB read misses -system.cpu.dtb.write_hits 11215606 # DTB write hits -system.cpu.dtb.write_misses 2208 # DTB write misses +system.cpu.dtb.read_hits 14995950 # DTB read hits +system.cpu.dtb.read_misses 7342 # DTB read misses +system.cpu.dtb.write_hits 11230967 # DTB write hits +system.cpu.dtb.write_misses 2209 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 183 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14977992 # DTB read accesses -system.cpu.dtb.write_accesses 11217814 # DTB write accesses +system.cpu.dtb.read_accesses 15003292 # DTB read accesses +system.cpu.dtb.write_accesses 11233176 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26186255 # DTB hits +system.cpu.dtb.hits 26226917 # DTB hits system.cpu.dtb.misses 9551 # DTB misses -system.cpu.dtb.accesses 26195806 # DTB accesses -system.cpu.itb.inst_hits 60357742 # ITB inst hits +system.cpu.dtb.accesses 26236468 # DTB accesses +system.cpu.itb.inst_hits 60464458 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -289,73 +289,73 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60362213 # ITB inst accesses -system.cpu.itb.hits 60357742 # DTB hits +system.cpu.itb.inst_accesses 60468929 # ITB inst accesses +system.cpu.itb.hits 60464458 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60362213 # DTB accesses -system.cpu.numCycles 5182883384 # number of cpu cycles simulated +system.cpu.itb.accesses 60468929 # DTB accesses +system.cpu.numCycles 5182838000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59075703 # Number of instructions committed -system.cpu.committedOps 75477535 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68255288 # Number of integer alu accesses +system.cpu.committedInsts 59182652 # Number of instructions committed +system.cpu.committedOps 75585847 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68355333 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 1975579 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7643992 # number of instructions that are conditional controls -system.cpu.num_int_insts 68255288 # number of integer instructions +system.cpu.num_func_calls 1976025 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7653656 # number of instructions that are conditional controls +system.cpu.num_int_insts 68355333 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 390835490 # number of times the integer registers were read -system.cpu.num_int_register_writes 72984180 # number of times the integer registers were written +system.cpu.num_int_register_reads 391421263 # number of times the integer registers were read +system.cpu.num_int_register_writes 73137347 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27351737 # number of memory refs -system.cpu.num_load_insts 15632523 # Number of load instructions -system.cpu.num_store_insts 11719214 # Number of store instructions -system.cpu.num_idle_cycles 4574345726.482235 # Number of idle cycles -system.cpu.num_busy_cycles 608537657.517765 # Number of busy cycles -system.cpu.not_idle_fraction 0.117413 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.882587 # Percentage of idle cycles +system.cpu.num_mem_refs 27394170 # number of memory refs +system.cpu.num_load_insts 15659823 # Number of load instructions +system.cpu.num_store_insts 11734347 # Number of store instructions +system.cpu.num_idle_cycles 4573988502.570235 # Number of idle cycles +system.cpu.num_busy_cycles 608849497.429765 # Number of busy cycles +system.cpu.not_idle_fraction 0.117474 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.882526 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 82953 # number of quiesce instructions executed -system.cpu.icache.replacements 852971 # number of replacements -system.cpu.icache.tagsinuse 510.943281 # Cycle average of tags in use -system.cpu.icache.total_refs 59504259 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.719325 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18513021000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.943281 # Average occupied blocks per requestor +system.cpu.kern.inst.quiesce 82997 # number of quiesce instructions executed +system.cpu.icache.replacements 855402 # number of replacements +system.cpu.icache.tagsinuse 510.943261 # Cycle average of tags in use +system.cpu.icache.total_refs 59608544 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855914 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 69.643146 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18524424000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.943261 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59504259 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59504259 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59504259 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59504259 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59504259 # number of overall hits -system.cpu.icache.overall_hits::total 59504259 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 853483 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 853483 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 853483 # number of overall misses -system.cpu.icache.overall_misses::total 853483 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12547128000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12547128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12547128000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12547128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12547128000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12547128000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60357742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60357742 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60357742 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60357742 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60357742 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60357742 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014140 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014140 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14701.087192 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 59608544 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 59608544 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 59608544 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 59608544 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 59608544 # number of overall hits +system.cpu.icache.overall_hits::total 59608544 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855914 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855914 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855914 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855914 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855914 # number of overall misses +system.cpu.icache.overall_misses::total 855914 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12584924000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12584924000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12584924000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12584924000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12584924000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12584924000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60464458 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 60464458 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 60464458 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 60464458 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60464458 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 60464458 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014156 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014156 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014156 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14703.491239 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14703.491239 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -364,96 +364,96 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 45661 # number of writebacks -system.cpu.icache.writebacks::total 45661 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 853483 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 853483 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 853483 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 853483 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 853483 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 853483 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9984295500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9984295500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9984295500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9984295500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9984295500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9984295500 # number of overall MSHR miss cycles +system.cpu.icache.writebacks::writebacks 45705 # number of writebacks +system.cpu.icache.writebacks::total 45705 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855914 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855914 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855914 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855914 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855914 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855914 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10014791000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10014791000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10014791000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10014791000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10014791000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10014791000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.294518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014156 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11700.697734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11700.697734 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 626903 # number of replacements -system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use -system.cpu.dcache.total_refs 23615099 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.638722 # Average number of references to valid blocks. +system.cpu.dcache.replacements 627094 # number of replacements +system.cpu.dcache.tagsinuse 511.875591 # Cycle average of tags in use +system.cpu.dcache.total_refs 23655637 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627606 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.691859 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.875592 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.875591 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13170369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13170369 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9958095 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9958095 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236142 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247592 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23128464 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23128464 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23128464 # number of overall hits -system.cpu.dcache.overall_hits::total 23128464 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 368563 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250302 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11451 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 618865 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 618865 # number of overall misses -system.cpu.dcache.overall_misses::total 618865 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5846897000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5846897000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9551170500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9551170500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186076500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 186076500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15398067500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15398067500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15398067500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15398067500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13538932 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13538932 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10208397 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10208397 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247593 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247592 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23747329 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23747329 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23747329 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23747329 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046249 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15864.036813 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 13195546 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13195546 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9973168 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9973168 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236327 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236327 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247699 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247699 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23168714 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23168714 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23168714 # number of overall hits +system.cpu.dcache.overall_hits::total 23168714 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 368647 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 368647 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250483 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250483 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11373 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11373 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 619130 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 619130 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 619130 # number of overall misses +system.cpu.dcache.overall_misses::total 619130 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5836151500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5836151500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9546175500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9546175500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185299500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185299500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15382327000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15382327000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15382327000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15382327000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13564193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13564193 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10223651 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10223651 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247700 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247700 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247699 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247699 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23787844 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23787844 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23787844 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23787844 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027178 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024500 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045914 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026027 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026027 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15831.273549 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38111.071410 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16292.930625 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24845.068079 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,44 +462,44 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 564388 # number of writebacks -system.cpu.dcache.writebacks::total 564388 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368563 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368563 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250302 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250302 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11451 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 11451 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 618865 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 618865 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 618865 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 618865 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741074500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741074500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800219500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800219500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151723500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151723500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13541294000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13541294000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13541294000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13541294000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146946835000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146946835000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367455500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367455500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187314290500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187314290500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024519 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046249 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12863.674596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35158.406645 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13249.803511 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 566088 # number of writebacks +system.cpu.dcache.writebacks::total 566088 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368647 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368647 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250483 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250483 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11373 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11373 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619130 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619130 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619130 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619130 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4730079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4730079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8794683000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8794683000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151180500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151180500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13524762000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13524762000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13524762000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13524762000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146938040000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146938040000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40368528500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40368528500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187306568500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187306568500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027178 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024500 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.045914 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026027 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12830.916839 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35110.897746 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13292.930625 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21844.785425 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency @@ -518,10 +518,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1341941439938 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1342278175263 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342278175263 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1342278175263 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal Binary files differindex 33e436852..3191ccab8 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal |