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authorAndreas Hansson <andreas.hansson@arm.com>2013-03-26 14:46:49 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-03-26 14:46:49 -0400
commit08f7a8bc005507117ffda41f283adecf7e4d24f2 (patch)
treed3588f01b572538601360998b89e23607549934c /tests/quick/fs
parent93a8423dea8f8194d83df85a5b3043f9beaf0a1e (diff)
downloadgem5-08f7a8bc005507117ffda41f283adecf7e4d24f2.tar.xz
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into waiting for the bus and waiting for the peer.
Diffstat (limited to 'tests/quick/fs')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt800
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt454
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt716
3 files changed, 985 insertions, 985 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 3e3128027..91c2fb18d 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.954691 # Nu
sim_ticks 1954691371500 # Number of ticks simulated
final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 798728 # Simulator instruction rate (inst/s)
-host_op_rate 798728 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26318676085 # Simulator tick rate (ticks/s)
-host_mem_usage 332420 # Number of bytes of host memory used
-host_seconds 74.27 # Real time elapsed on the host
+host_inst_rate 888978 # Simulator instruction rate (inst/s)
+host_op_rate 888978 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29292473013 # Simulator tick rate (ticks/s)
+host_mem_usage 331536 # Number of bytes of host memory used
+host_seconds 66.73 # Real time elapsed on the host
sim_insts 59321614 # Number of instructions simulated
sim_ops 59321614 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory
@@ -50,13 +50,13 @@ system.physmem.bw_total::cpu1.data 199364 # To
system.physmem.bw_total::total 18590401 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 447836 # Total number of read requests seen
system.physmem.writeReqs 119953 # Total number of write requests seen
-system.physmem.cpureqs 572898 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 570963 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28661504 # Total number of bytes read from memory
system.physmem.bytesWritten 7676992 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28661504 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 7676992 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 3161 # Reqs where no action is needed
+system.physmem.neitherReadNorWrite 3162 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 28180 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 28120 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 28097 # Track reads on a per bank basis
@@ -90,7 +90,7 @@ system.physmem.perBankWrReqs::13 7492 # Tr
system.physmem.perBankWrReqs::14 7142 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7280 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1948 # Number of times wr buffer was full causing retry
+system.physmem.numWrRetry 12 # Number of times wr buffer was full causing retry
system.physmem.totGap 1954684300500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@@ -106,26 +106,26 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 119953 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 407021 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4814 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3665 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2219 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3122 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2946 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2699 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2701 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2643 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2593 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1538 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1424 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 1347 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1387 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1607 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1512 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 407019 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4805 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 3654 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2220 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3121 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2947 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2702 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2596 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1540 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1465 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1427 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1370 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 1349 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1510 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 904 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 783 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 781 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
@@ -138,15 +138,15 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 3709 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 3875 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 4276 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 4328 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4843 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5193 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5199 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5202 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5201 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 3708 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 3873 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 4272 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 4324 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4841 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5192 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5198 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5201 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5200 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5215 # What write queue length does an incoming req see
@@ -161,23 +161,23 @@ system.physmem.wrQLenPdf::19 5215 # Wh
system.physmem.wrQLenPdf::20 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5215 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1507 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 940 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 888 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 373 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 23 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
-system.physmem.totQLat 4783798250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13397999500 # Sum of mem lat for all requests
+system.physmem.wrQLenPdf::23 1508 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 1343 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 944 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 892 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 375 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
+system.physmem.totQLat 4783941000 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13398087250 # Sum of mem lat for all requests
system.physmem.totBusLat 2238835000 # Total cycles spent in databus access
-system.physmem.totBankLat 6375366250 # Total cycles spent in bank access
-system.physmem.avgQLat 10683.68 # Average queueing delay per request
-system.physmem.avgBankLat 14238.13 # Average bank access latency per request
+system.physmem.totBankLat 6375311250 # Total cycles spent in bank access
+system.physmem.avgQLat 10684.00 # Average queueing delay per request
+system.physmem.avgBankLat 14238.01 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29921.81 # Average memory access latency
+system.physmem.avgMemAccLat 29922.01 # Average memory access latency
system.physmem.avgRdBW 14.66 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.93 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.66 # Average consumed read bandwidth in MB/s
@@ -192,14 +192,14 @@ system.physmem.readRowHitRate 93.77 # Ro
system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes
system.physmem.avgGap 3442624.46 # Average gap between requests
system.l2c.replacements 340771 # number of replacements
-system.l2c.tagsinuse 65303.436480 # Cycle average of tags in use
-system.l2c.total_refs 2493415 # Total number of references to valid blocks.
+system.l2c.tagsinuse 65303.436431 # Cycle average of tags in use
+system.l2c.total_refs 2493405 # Total number of references to valid blocks.
system.l2c.sampled_refs 405943 # Sample count of references to valid blocks.
-system.l2c.avg_refs 6.142279 # Average number of references to valid blocks.
+system.l2c.avg_refs 6.142254 # Average number of references to valid blocks.
system.l2c.warmup_cycle 6937754751 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 55559.705668 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst 4839.489270 # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data 4775.815267 # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks 55559.705591 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4839.489284 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 4775.815281 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.inst 117.980929 # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1.data 10.445347 # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks 0.847774 # Average percentage of cache occupancy
@@ -209,39 +209,39 @@ system.l2c.occ_percent::cpu1.inst 0.001800 # Av
system.l2c.occ_percent::cpu1.data 0.000159 # Average percentage of cache occupancy
system.l2c.occ_percent::total 0.996451 # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0.inst 902966 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 773506 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 773500 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 86370 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 33767 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1796609 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 820435 # number of Writeback hits
-system.l2c.Writeback_hits::total 820435 # number of Writeback hits
+system.l2c.ReadReq_hits::total 1796603 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 820431 # number of Writeback hits
+system.l2c.Writeback_hits::total 820431 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 163 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 219 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 21 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 40 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 171833 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data 171831 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 12858 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 184691 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 184689 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.inst 902966 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 945339 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 945331 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 86370 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 46625 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1981300 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1981292 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.inst 902966 # number of overall hits
-system.l2c.overall_hits::cpu0.data 945339 # number of overall hits
+system.l2c.overall_hits::cpu0.data 945331 # number of overall hits
system.l2c.overall_hits::cpu1.inst 86370 # number of overall hits
system.l2c.overall_hits::cpu1.data 46625 # number of overall hits
-system.l2c.overall_hits::total 1981300 # number of overall hits
+system.l2c.overall_hits::total 1981292 # number of overall hits
system.l2c.ReadReq_misses::cpu0.inst 12959 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 271596 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 545 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 189 # number of ReadReq misses
system.l2c.ReadReq_misses::total 285289 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 2443 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2925 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2926 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 27 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 73 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 100 # number of SCUpgradeReq misses
@@ -258,104 +258,104 @@ system.l2c.overall_misses::cpu0.data 387219 # nu
system.l2c.overall_misses::cpu1.inst 545 # number of overall misses
system.l2c.overall_misses::cpu1.data 6107 # number of overall misses
system.l2c.overall_misses::total 406830 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst 800348000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 11682390000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst 800540000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data 11682471000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 34833000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 14789000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 12532360000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu0.data 1038000 # number of UpgradeReq miss cycles
+system.l2c.ReadReq_miss_latency::total 12532633000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data 1038500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 229000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 1267000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 1267500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 22500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 115000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 137500 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data 5536684000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data 5536696500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 338210000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 5874894000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst 800348000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data 17219074000 # number of demand (read+write) miss cycles
+system.l2c.ReadExReq_miss_latency::total 5874906500 # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst 800540000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data 17219167500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 34833000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 352999000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 18407254000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst 800348000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data 17219074000 # number of overall miss cycles
+system.l2c.demand_miss_latency::total 18407539500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst 800540000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data 17219167500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 34833000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 352999000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 18407254000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 18407539500 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.inst 915925 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 1045102 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 1045096 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 86915 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 33956 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2081898 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 820435 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 820435 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 2605 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2081892 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 820431 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 820431 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 2606 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 539 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3144 # number of UpgradeReq accesses(hits+misses)
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system.l2c.SCUpgradeReq_accesses::cpu0.data 48 # number of SCUpgradeReq accesses(hits+misses)
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system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51613.825843 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 45167.559686 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 32931.588648 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 32932.289205 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
@@ -492,7 +492,7 @@ system.iocache.tagsinuse 0.572561 # Cy
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 1746701282000 # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle 1746701284000 # Cycle when the warmup percentage was hit.
system.iocache.occ_blocks::tsunami.ide 0.572561 # Average occupied blocks per requestor
system.iocache.occ_percent::tsunami.ide 0.035785 # Average percentage of cache occupancy
system.iocache.occ_percent::total 0.035785 # Average percentage of cache occupancy
@@ -506,12 +506,12 @@ system.iocache.overall_misses::tsunami.ide 41726 #
system.iocache.overall_misses::total 41726 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10674900806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10674900806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10695943804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10695943804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10695943804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10695943804 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10675580676 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10675580676 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10696623674 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10696623674 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10696623674 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10696623674 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -530,17 +530,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256904.620861 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 256904.620861 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 256337.626516 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 256337.626516 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 256337.626516 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 286340 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256920.982769 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 256920.982769 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 256353.920194 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 256353.920194 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 256353.920194 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 256353.920194 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 286338 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27291 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27305 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.492104 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.486651 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -556,12 +556,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726
system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8512910554 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8512910554 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8524904803 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8524904803 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8524904803 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8524904803 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8513588925 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8513588925 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8525583174 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8525583174 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8525583174 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8525583174 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -572,12 +572,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204873.665624 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 204873.665624 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204306.782414 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 204306.782414 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204889.991456 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 204889.991456 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -641,8 +641,8 @@ system.cpu0.num_fp_register_writes 146520 # nu
system.cpu0.num_mem_refs 14722187 # number of memory refs
system.cpu0.num_load_insts 8662865 # Number of load instructions
system.cpu0.num_store_insts 6059322 # Number of store instructions
-system.cpu0.num_idle_cycles 3679287399.643625 # Number of idle cycles
-system.cpu0.num_busy_cycles 228924136.356375 # Number of busy cycles
+system.cpu0.num_idle_cycles 3679287255.686766 # Number of idle cycles
+system.cpu0.num_busy_cycles 228924280.313234 # Number of busy cycles
system.cpu0.not_idle_fraction 0.058575 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.941425 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
@@ -660,11 +660,11 @@ system.cpu0.kern.ipl_good::22 1975 1.36% 50.73% # nu
system.cpu0.kern.ipl_good::30 6 0.00% 50.73% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::31 71376 49.27% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::total 144870 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1898301273000 97.14% 97.14% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::0 1898301427500 97.14% 97.14% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::21 93023500 0.00% 97.15% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 762236500 0.04% 97.19% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 762226000 0.04% 97.19% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::30 5235500 0.00% 97.19% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 54943969500 2.81% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 54943825500 2.81% 100.00% # number of cycles we spent at this ipl
system.cpu0.kern.ipl_ticks::total 1954105738000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.981209 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
@@ -730,8 +730,8 @@ system.cpu0.kern.mode_switch_good::kernel 0.175657 # f
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total 0.298824 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1950347295500 99.82% 99.82% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3454635500 0.18% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel 1950347158000 99.82% 99.82% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 3454773000 0.18% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3897 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
@@ -766,12 +766,12 @@ system.tsunami.ethernet.coalescedTotal nan # av
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
system.cpu0.icache.replacements 915312 # number of replacements
-system.cpu0.icache.tagsinuse 509.170565 # Cycle average of tags in use
+system.cpu0.icache.tagsinuse 509.170564 # Cycle average of tags in use
system.cpu0.icache.total_refs 53154487 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 915824 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 58.040068 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 32594703000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 509.170565 # Average occupied blocks per requestor
+system.cpu0.icache.occ_blocks::cpu0.inst 509.170564 # Average occupied blocks per requestor
system.cpu0.icache.occ_percent::cpu0.inst 0.994474 # Average percentage of cache occupancy
system.cpu0.icache.occ_percent::total 0.994474 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 53154487 # number of ReadReq hits
@@ -786,12 +786,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 915946 #
system.cpu0.icache.demand_misses::total 915946 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 915946 # number of overall misses
system.cpu0.icache.overall_misses::total 915946 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645153500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 12645153500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 12645153500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 12645153500 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 12645153500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 12645153500 # number of overall miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12645308000 # number of ReadReq miss cycles
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+system.cpu0.icache.demand_miss_latency::total 12645308000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 12645308000 # number of overall miss cycles
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 54070433 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 54070433 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 54070433 # number of demand (read+write) accesses
@@ -804,12 +804,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016940
system.cpu0.icache.demand_miss_rate::total 0.016940 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016940 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.016940 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.566595 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.566595 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13805.566595 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.566595 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13805.566595 # average overall miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13805.735273 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 13805.735273 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13805.735273 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13805.735273 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13805.735273 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -824,70 +824,70 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 915946
system.cpu0.icache.demand_mshr_misses::total 915946 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 915946 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 915946 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813261500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813261500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813261500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 10813261500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813261500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 10813261500 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10813416000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 10813416000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10813416000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 10813416000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10813416000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 10813416000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.016940 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016940 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.016940 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.566595 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.566595 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.566595 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11805.735273 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11805.735273 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11805.735273 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.replacements 1337909 # number of replacements
-system.cpu0.dcache.tagsinuse 506.537579 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 13346950 # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs 1338324 # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs 9.972884 # Average number of references to valid blocks.
+system.cpu0.dcache.replacements 1337901 # number of replacements
+system.cpu0.dcache.tagsinuse 506.537580 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 13346958 # Total number of references to valid blocks.
+system.cpu0.dcache.sampled_refs 1338316 # Sample count of references to valid blocks.
+system.cpu0.dcache.avg_refs 9.972950 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 93616000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 506.537579 # Average occupied blocks per requestor
+system.cpu0.dcache.occ_blocks::cpu0.data 506.537580 # Average occupied blocks per requestor
system.cpu0.dcache.occ_percent::cpu0.data 0.989331 # Average percentage of cache occupancy
system.cpu0.dcache.occ_percent::total 0.989331 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data 7419116 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7419116 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 5560491 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5560491 # number of WriteReq hits
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+system.cpu0.dcache.ReadReq_hits::total 7419122 # number of ReadReq hits
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+system.cpu0.dcache.WriteReq_hits::total 5560492 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176356 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 176356 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191669 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 191669 # number of StoreCondReq hits
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-system.cpu0.dcache.demand_hits::total 12979607 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 12979607 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12979607 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 1035921 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1035921 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 291041 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 291041 # number of WriteReq misses
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+system.cpu0.dcache.demand_hits::total 12979614 # number of demand (read+write) hits
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+system.cpu0.dcache.overall_hits::total 12979614 # number of overall hits
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system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16710 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 16710 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 430 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 430 # number of StoreCondReq misses
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-system.cpu0.dcache.demand_misses::total 1326962 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1326962 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1326962 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 22391252000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 22391252000 # number of ReadReq miss cycles
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+system.cpu0.dcache.WriteReq_miss_latency::total 8190691500 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 219165000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 219165000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2509000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 2509000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 30581937500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 30581937500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 30581937500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 30581937500 # number of overall miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 30581958000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 30581958000 # number of demand (read+write) miss cycles
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+system.cpu0.dcache.overall_miss_latency::total 30581958000 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8455037 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 8455037 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851532 # number of WriteReq accesses(hits+misses)
@@ -900,30 +900,30 @@ system.cpu0.dcache.demand_accesses::cpu0.data 14306569
system.cpu0.dcache.demand_accesses::total 14306569 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 14306569 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 14306569 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122521 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.122521 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049738 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.049738 # miss rate for WriteReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122520 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.122520 # miss rate for ReadReq accesses
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+system.cpu0.dcache.WriteReq_miss_rate::total 0.049737 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.086551 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.086551 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002238 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.002238 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092752 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.092752 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092752 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.092752 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.825841 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.825841 # average ReadReq miss latency
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.720441 # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092751 # miss rate for demand accesses
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21614.965031 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 21614.965031 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 28142.837754 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13115.798923 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13115.798923 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5834.883721 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5834.883721 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 23046.581213 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.581213 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 23046.581213 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 23046.718238 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23046.718238 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 23046.718238 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -932,62 +932,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 789805 # number of writebacks
-system.cpu0.dcache.writebacks::total 789805 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035921 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 1035921 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291041 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 291041 # number of WriteReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks 789801 # number of writebacks
+system.cpu0.dcache.writebacks::total 789801 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1035915 # number of ReadReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::total 291040 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16710 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16710 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 430 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 430 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1326962 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185745000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185745000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1649000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1649000 # number of StoreCondReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::total 27928013500 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092162000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3557617500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557617500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122521 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122521 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049738 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049738 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 27928048000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 27928048000 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::total 27928048000 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1465347500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1465347500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2092159000 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3557506500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122520 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.122520 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049737 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.049737 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086551 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086551 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002238 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.002238 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.092752 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092752 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.092752 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.825841 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.825841 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.720441 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.720441 # average WriteReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.092751 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092751 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.092751 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 19614.965031 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 19614.965031 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26142.837754 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26142.837754 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11115.798923 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11115.798923 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3834.883721 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3834.883721 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.581213 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.581213 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21046.718238 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21046.718238 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
@@ -1045,8 +1045,8 @@ system.cpu1.num_fp_register_writes 21862 # nu
system.cpu1.num_mem_refs 1706720 # number of memory refs
system.cpu1.num_load_insts 1053093 # Number of load instructions
system.cpu1.num_store_insts 653627 # Number of store instructions
-system.cpu1.num_idle_cycles 3890042761.998010 # Number of idle cycles
-system.cpu1.num_busy_cycles 19339981.001990 # Number of busy cycles
+system.cpu1.num_idle_cycles 3890042730.998010 # Number of idle cycles
+system.cpu1.num_busy_cycles 19340012.001990 # Number of busy cycles
system.cpu1.not_idle_fraction 0.004947 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.995053 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
@@ -1062,10 +1062,10 @@ system.cpu1.kern.ipl_good::22 1969 9.91% 54.95% # nu
system.cpu1.kern.ipl_good::30 88 0.44% 55.40% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 8863 44.60% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 19871 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1917858613000 98.12% 98.12% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0 1917858601000 98.12% 98.12% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::22 705516000 0.04% 98.15% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::30 59546500 0.00% 98.15% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 36066938000 1.85% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 36066950000 1.85% 100.00% # number of cycles we spent at this ipl
system.cpu1.kern.ipl_ticks::total 1954690613500 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.998884 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
@@ -1138,12 +1138,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 86916 #
system.cpu1.icache.demand_misses::total 86916 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 86916 # number of overall misses
system.cpu1.icache.overall_misses::total 86916 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175951500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 1175951500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 1175951500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 1175951500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 1175951500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 1175951500 # number of overall miss cycles
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1175956500 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 1175956500 # number of ReadReq miss cycles
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+system.cpu1.icache.demand_miss_latency::total 1175956500 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 1175956500 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 1175956500 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5263148 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 5263148 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 5263148 # number of demand (read+write) accesses
@@ -1156,12 +1156,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016514
system.cpu1.icache.demand_miss_rate::total 0.016514 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016514 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.016514 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.747112 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.747112 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13529.747112 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.747112 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13529.747112 # average overall miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13529.804639 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 13529.804639 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 13529.804639 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13529.804639 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 13529.804639 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1176,70 +1176,70 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 86916
system.cpu1.icache.demand_mshr_misses::total 86916 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 86916 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 86916 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 1002119500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1002119500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 1002119500 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.icache.overall_mshr_miss_latency::total 1002119500 # number of overall MSHR miss cycles
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system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.016514 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.016514 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016514 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.016514 # mshr miss rate for overall accesses
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-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11529.747112 # average ReadReq mshr miss latency
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-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.747112 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.747112 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average ReadReq mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11529.804639 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11529.804639 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 52807 # number of replacements
system.cpu1.dcache.tagsinuse 417.673106 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1641018 # Total number of references to valid blocks.
+system.cpu1.dcache.total_refs 1641017 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 53319 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 30.777359 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 30.777340 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1938580812000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.occ_blocks::cpu1.data 417.673106 # Average occupied blocks per requestor
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system.cpu1.dcache.occ_percent::total 0.815768 # Average percentage of cache occupancy
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system.cpu1.dcache.WriteReq_hits::total 616220 # number of WriteReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 10806 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 10806 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11203 # number of StoreCondReq hits
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system.cpu1.dcache.WriteReq_misses::total 20401 # number of WriteReq misses
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system.cpu1.dcache.LoadLockedReq_misses::total 956 # number of LoadLockedReq misses
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system.cpu1.dcache.StoreCondReq_miss_latency::total 3694000 # number of StoreCondReq miss cycles
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system.cpu1.dcache.ReadReq_accesses::cpu1.data 1038246 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1038246 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 636621 # number of WriteReq accesses(hits+misses)
@@ -1252,8 +1252,8 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1674867
system.cpu1.dcache.demand_accesses::total 1674867 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 1674867 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1674867 # number of overall (read+write) accesses
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.035645 # miss rate for ReadReq accesses
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system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032046 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.032046 # miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081279 # miss rate for LoadLockedReq accesses
@@ -1264,18 +1264,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034277
system.cpu1.dcache.demand_miss_rate::total 0.034277 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034277 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.034277 # miss rate for overall accesses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.898941 # average ReadReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11089.435146 # average LoadLockedReq miss latency
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 12529.857602 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 26513.577766 # average WriteReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11087.343096 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7388 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7388 # average StoreCondReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 17499.129056 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.129056 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17499.129056 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17499.059397 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 17499.059397 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17499.059397 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 17499.059397 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1286,38 +1286,38 @@ system.cpu1.dcache.fast_writes 0 # nu
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 30630 # number of writebacks
system.cpu1.dcache.writebacks::total 30630 # number of writebacks
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-system.cpu1.dcache.ReadReq_mshr_misses::total 37008 # number of ReadReq MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_misses::total 37009 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20401 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 20401 # number of WriteReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 956 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 956 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 500 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 500 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 8689500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 389699500 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 500101500 # number of WriteReq MSHR miss cycles
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system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 2694000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 2694000 # number of StoreCondReq MSHR miss cycles
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system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19380000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19380000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 529600000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 529600000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 548980000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 548980000 # number of overall MSHR uncacheable cycles
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035645 # mshr miss rate for ReadReq accesses
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system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032046 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032046 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.081279 # mshr miss rate for LoadLockedReq accesses
@@ -1328,18 +1328,18 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034277
system.cpu1.dcache.demand_mshr_miss_rate::total 0.034277 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034277 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.034277 # mshr miss rate for overall accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.898941 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.455223 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.455223 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9089.435146 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9089.435146 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10529.857602 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10529.857602 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24513.577766 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24513.577766 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9087.343096 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9087.343096 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5388 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5388 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.129056 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.129056 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15499.059397 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15499.059397 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 10a028441..9db64d392 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.913475 # Nu
sim_ticks 1913474690000 # Number of ticks simulated
final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1324010 # Simulator instruction rate (inst/s)
-host_op_rate 1324010 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45134311907 # Simulator tick rate (ticks/s)
-host_mem_usage 328328 # Number of bytes of host memory used
-host_seconds 42.40 # Real time elapsed on the host
+host_inst_rate 960952 # Simulator instruction rate (inst/s)
+host_op_rate 960952 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32757999490 # Simulator tick rate (ticks/s)
+host_mem_usage 329472 # Number of bytes of host memory used
+host_seconds 58.41 # Real time elapsed on the host
sim_insts 56131527 # Number of instructions simulated
sim_ops 56131527 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
@@ -40,7 +40,7 @@ system.physmem.bw_total::tsunami.ide 1386010 # To
system.physmem.bw_total::total 18692227 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 443158 # Total number of read requests seen
system.physmem.writeReqs 115703 # Total number of write requests seen
-system.physmem.cpureqs 560726 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 559001 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 28362112 # Total number of bytes read from memory
system.physmem.bytesWritten 7404992 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 28362112 # bytesRead derated as per pkt->getSize()
@@ -80,7 +80,7 @@ system.physmem.perBankWrReqs::13 7186 # Tr
system.physmem.perBankWrReqs::14 7115 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 7077 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 1735 # Number of times wr buffer was full causing retry
+system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
system.physmem.totGap 1913462790000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@@ -96,26 +96,26 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 115703 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 402452 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4725 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3681 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 2218 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3124 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2960 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2702 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 402453 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4723 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 3684 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2217 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3126 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2958 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2701 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2703 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 2646 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 2585 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 1528 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 1461 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1423 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1368 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1422 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1367 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 1353 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1388 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1604 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1473 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 916 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 777 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1608 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1477 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 912 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
@@ -132,11 +132,11 @@ system.physmem.wrQLenPdf::0 3531 # Wh
system.physmem.wrQLenPdf::1 3690 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 4106 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 4152 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 4652 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5003 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5013 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5015 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 4653 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5005 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5014 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5016 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5031 # What write queue length does an incoming req see
@@ -155,19 +155,19 @@ system.physmem.wrQLenPdf::23 1500 # Wh
system.physmem.wrQLenPdf::24 1341 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 925 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 879 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 379 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
-system.physmem.totQLat 4718928250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 13231418250 # Sum of mem lat for all requests
+system.physmem.wrQLenPdf::27 378 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see
+system.physmem.totQLat 4710239250 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 13222743000 # Sum of mem lat for all requests
system.physmem.totBusLat 2215485000 # Total cycles spent in databus access
-system.physmem.totBankLat 6297005000 # Total cycles spent in bank access
-system.physmem.avgQLat 10649.88 # Average queueing delay per request
-system.physmem.avgBankLat 14211.35 # Average bank access latency per request
+system.physmem.totBankLat 6297018750 # Total cycles spent in bank access
+system.physmem.avgQLat 10630.27 # Average queueing delay per request
+system.physmem.avgBankLat 14211.38 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 29861.22 # Average memory access latency
+system.physmem.avgMemAccLat 29841.64 # Average memory access latency
system.physmem.avgRdBW 14.82 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 3.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 14.82 # Average consumed read bandwidth in MB/s
@@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 #
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10661973806 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10661973806 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10682901804 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10682901804 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10682901804 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10682901804 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10653271428 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10653271428 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10674199426 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10674199426 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10674199426 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10674199426 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -224,17 +224,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256593.516702 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 256593.516702 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 256031.199617 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 256031.199617 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 256031.199617 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 285723 # number of cycles access was blocked
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.083269 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 256384.083269 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 255822.634536 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 255822.634536 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 285520 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27146 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27149 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.525418 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.516778 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8499962078 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8499962078 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8511893327 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8511893327 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8511893327 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8511893327 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491261949 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8491261949 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8503193198 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8503193198 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8503193198 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8503193198 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204562.044619 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 204562.044619 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203999.840072 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203999.840072 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.665311 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.665311 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
@@ -335,8 +335,8 @@ system.cpu.num_fp_register_writes 166418 # nu
system.cpu.num_mem_refs 15461819 # number of memory refs
system.cpu.num_load_insts 9093811 # Number of load instructions
system.cpu.num_store_insts 6368008 # Number of store instructions
-system.cpu.num_idle_cycles 3593003741.998122 # Number of idle cycles
-system.cpu.num_busy_cycles 233945638.001878 # Number of busy cycles
+system.cpu.num_idle_cycles 3593002703.998122 # Number of idle cycles
+system.cpu.num_busy_cycles 233946676.001878 # Number of busy cycles
system.cpu.not_idle_fraction 0.061131 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.938869 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
@@ -352,10 +352,10 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu
system.cpu.kern.ipl_good::22 1933 1.30% 50.69% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73532 49.31% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 149128 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1858610780000 97.13% 97.13% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1858610730000 97.13% 97.13% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 91300500 0.00% 97.14% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 737276500 0.04% 97.18% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 54034599000 2.82% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 54034649000 2.82% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1913473956000 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981749 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
@@ -420,9 +420,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323898 # fr
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392402 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 45394142000 2.37% 2.37% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5131394000 0.27% 2.64% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1862948418000 97.36% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 45394332000 2.37% 2.37% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 5131699000 0.27% 2.64% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1862947923000 97.36% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4175 # number of times the context was actually changed
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
@@ -476,12 +476,12 @@ system.cpu.icache.demand_misses::cpu.inst 928628 # n
system.cpu.icache.demand_misses::total 928628 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 928628 # number of overall misses
system.cpu.icache.overall_misses::total 928628 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 12770278000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 12770278000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141596 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383927 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383927 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.173403 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014312 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279663 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279661 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.173403 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50132.884123 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30740.052728 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31643.569007 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 50144.547028 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30741.223843 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31645.228937 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35601.022455 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35601.022455 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50132.884123 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32200.972792 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32793.635731 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35600.705826 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35600.705826 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50144.547028 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32201.696779 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32794.721257 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -703,47 +703,47 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1389801 # number of replacements
+system.cpu.dcache.replacements 1389808 # number of replacements
system.cpu.dcache.tagsinuse 511.980871 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14037928 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1390313 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 10.096955 # Average number of references to valid blocks.
+system.cpu.dcache.total_refs 14037921 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1390320 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 10.096899 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 93552000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.980871 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7807394 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807394 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data 7807387 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7807387 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 5848285 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5848285 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183004 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183004 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 199228 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199228 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 13655679 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13655679 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13655679 # number of overall hits
-system.cpu.dcache.overall_hits::total 13655679 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1068700 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1068700 # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data 13655672 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13655672 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 13655672 # number of overall hits
+system.cpu.dcache.overall_hits::total 13655672 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1068707 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1068707 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 304387 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304387 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17244 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17244 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1373087 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1373087 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1373087 # number of overall misses
-system.cpu.dcache.overall_misses::total 1373087 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 22867911000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 22867911000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385686000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8385686000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 1373094 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1373094 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1373094 # number of overall misses
+system.cpu.dcache.overall_misses::total 1373094 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 22868320000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 22868320000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8385649000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8385649000 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228869000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 228869000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 31253597000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 31253597000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 31253597000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 31253597000 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 31253969000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 31253969000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 31253969000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 31253969000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 8876094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 8876094 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 6152672 # number of WriteReq accesses(hits+misses)
@@ -756,8 +756,8 @@ system.cpu.dcache.demand_accesses::cpu.data 15028766 #
system.cpu.dcache.demand_accesses::total 15028766 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 15028766 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15028766 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120402 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.120402 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120403 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.120403 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049472 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.049472 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086113 # miss rate for LoadLockedReq accesses
@@ -766,16 +766,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.091364
system.cpu.dcache.demand_miss_rate::total 0.091364 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.091364 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.091364 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21397.876860 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21397.876860 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.422282 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.422282 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21398.119410 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 21398.119410 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27549.300726 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 27549.300726 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13272.384598 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13272.384598 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22761.556260 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.556260 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22761.556260 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22761.711143 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22761.711143 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22761.711143 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -784,36 +784,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 834498 # number of writebacks
-system.cpu.dcache.writebacks::total 834498 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068700 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1068700 # number of ReadReq MSHR misses
+system.cpu.dcache.writebacks::writebacks 834499 # number of writebacks
+system.cpu.dcache.writebacks::total 834499 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1068707 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1068707 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304387 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 304387 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17244 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17244 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1373087 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1373087 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1373087 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1373087 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730511000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730511000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776912000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776912000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data 1373094 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1373094 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1373094 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1373094 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 20730906000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 20730906000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7776875000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7776875000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194381000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194381000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507423000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 28507423000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507423000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28507423000 # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28507781000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 28507781000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28507781000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 28507781000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424236000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424236000 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011665000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011665000 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3435901000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 3435901000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120402 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120402 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120403 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120403 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049472 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049472 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086113 # mshr miss rate for LoadLockedReq accesses
@@ -822,16 +822,16 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091364
system.cpu.dcache.demand_mshr_miss_rate::total 0.091364 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091364 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.091364 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19397.876860 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19397.876860 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.422282 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.422282 # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19398.119410 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19398.119410 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25549.300726 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25549.300726 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11272.384598 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11272.384598 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.556260 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.556260 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20761.711143 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20761.711143 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 38cfd80e2..2f6691c8d 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,13 +4,13 @@ sim_seconds 5.195162 # Nu
sim_ticks 5195162021000 # Number of ticks simulated
final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 926995 # Simulator instruction rate (inst/s)
-host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 37543942770 # Simulator tick rate (ticks/s)
-host_mem_usage 611560 # Number of bytes of host memory used
-host_seconds 138.38 # Real time elapsed on the host
-sim_insts 128273323 # Number of instructions simulated
-sim_ops 247275942 # Number of ops (including micro ops) simulated
+host_inst_rate 697576 # Simulator instruction rate (inst/s)
+host_op_rate 1344736 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28252317760 # Simulator tick rate (ticks/s)
+host_mem_usage 611664 # Number of bytes of host memory used
+host_seconds 183.88 # Real time elapsed on the host
+sim_insts 128273373 # Number of instructions simulated
+sim_ops 247275988 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
@@ -48,16 +48,16 @@ system.physmem.bw_total::cpu.data 1734722 # To
system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 198400 # Total number of read requests seen
system.physmem.writeReqs 126924 # Total number of write requests seen
-system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady
+system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 12697600 # Total number of bytes read from memory
system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
+system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 12233 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis
@@ -88,7 +88,7 @@ system.physmem.perBankWrReqs::13 7628 # Tr
system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 633 # Number of times wr buffer was full causing retry
+system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry
system.physmem.totGap 5195161957500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
@@ -104,27 +104,27 @@ system.physmem.writePktSize::3 0 # Ca
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 126924 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
@@ -136,15 +136,15 @@ system.physmem.rdQLenPdf::28 0 # Wh
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see
@@ -159,23 +159,23 @@ system.physmem.wrQLenPdf::19 5518 # Wh
system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
-system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests
-system.physmem.totBusLat 991710000 # Total cycles spent in databus access
-system.physmem.totBankLat 2804120000 # Total cycles spent in bank access
-system.physmem.avgQLat 20536.88 # Average queueing delay per request
-system.physmem.avgBankLat 14137.80 # Average bank access latency per request
+system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
+system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests
+system.physmem.totBusLat 991715000 # Total cycles spent in databus access
+system.physmem.totBankLat 2804628750 # Total cycles spent in bank access
+system.physmem.avgQLat 20766.54 # Average queueing delay per request
+system.physmem.avgBankLat 14140.30 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 39674.68 # Average memory access latency
+system.physmem.avgMemAccLat 39906.83 # Average memory access latency
system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
@@ -184,8 +184,8 @@ system.physmem.peakBW 12800.00 # Th
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 12.66 # Average write queue length over time
-system.physmem.readRowHits 175586 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94818 # Number of row buffer hits during writes
+system.physmem.readRowHits 175593 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94810 # Number of row buffer hits during writes
system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
system.physmem.avgGap 15969193.66 # Average gap between requests
@@ -206,14 +206,14 @@ system.iocache.demand_misses::pc.south_bridge.ide 47564
system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
system.iocache.overall_misses::total 47564 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732357682 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10732357682 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10870344079 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10870344079 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10870344079 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10870344079 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
@@ -230,19 +230,19 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.559974 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 229716.559974 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 228541.419540 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 228541.419540 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
@@ -256,14 +256,14 @@ system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564
system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301559588 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8301559588 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8395637015 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8395637015 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
@@ -272,14 +272,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.491182 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.491182 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
@@ -296,72 +296,72 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1
system.cpu.numCycles 10390324042 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 128273323 # Number of instructions committed
-system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses
+system.cpu.committedInsts 128273373 # Number of instructions committed
+system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls
-system.cpu.num_int_insts 232011652 # number of integer instructions
+system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls
+system.cpu.num_int_insts 232011695 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read
-system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written
+system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read
+system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 22232130 # number of memory refs
-system.cpu.num_load_insts 13871776 # Number of load instructions
-system.cpu.num_store_insts 8360354 # Number of store instructions
-system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles
-system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles
-system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.942191 # Percentage of idle cycles
+system.cpu.num_mem_refs 22232145 # number of memory refs
+system.cpu.num_load_insts 13871789 # Number of load instructions
+system.cpu.num_store_insts 8360356 # Number of store instructions
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -370,40 +370,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -624,46 +624,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -672,17 +672,17 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses
@@ -775,37 +775,37 @@ system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737
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@@ -837,29 +837,29 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 141743
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