diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-02-12 16:07:43 -0600 |
| commit | 4f8d1a4cef2b23b423ea083078cd933c66c88e2a (patch) | |
| tree | c6d7d7567ead8bc2fe34bbf35604cc10d50dd72c /tests/quick/fs | |
| parent | 542d0ceebca1d24bfb433ce9fe916b0586f8d029 (diff) | |
| download | gem5-4f8d1a4cef2b23b423ea083078cd933c66c88e2a.tar.xz | |
stats: update stats for insts/ops and master id changes
Diffstat (limited to 'tests/quick/fs')
33 files changed, 3140 insertions, 4966 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index bd95bae49..ab088d9ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -71,6 +72,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu0.tracer width=1 +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -85,20 +87,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -121,20 +116,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -180,6 +168,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu1.tracer width=1 +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -194,20 +183,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -230,20 +212,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -327,20 +302,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -359,20 +327,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -398,7 +359,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -468,7 +428,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -550,7 +509,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -567,7 +525,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -584,7 +541,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -601,7 +557,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -618,7 +573,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -635,7 +589,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -652,7 +605,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -669,7 +621,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -686,7 +637,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -703,7 +653,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -720,7 +669,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -737,7 +685,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -754,7 +701,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -771,7 +717,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -788,7 +733,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -805,7 +749,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -822,7 +765,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -839,7 +781,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -856,7 +797,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -872,7 +812,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -937,7 +876,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -948,7 +886,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index dbef4ddb7..78e725520 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 04:22:39 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:36 gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index c3dae4684..a6953794d 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3272042 # Simulator instruction rate (inst/s) -host_tick_rate 96902915749 # Simulator tick rate (ticks/s) -host_mem_usage 296264 # Number of bytes of host memory used -host_seconds 19.30 # Real time elapsed on the host +host_inst_rate 4204751 # Simulator instruction rate (inst/s) +host_op_rate 4204746 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 124525337361 # Simulator tick rate (ticks/s) +host_mem_usage 293604 # Number of bytes of host memory used +host_seconds 15.02 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated +sim_ops 63154034 # Number of ops (including micro ops) simulated system.physmem.bytes_read 72297472 # Number of bytes read from this memory system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory system.physmem.bytes_written 10452352 # Number of bytes written to this memory @@ -25,102 +27,111 @@ system.l2c.total_refs 2341203 # To system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks. system.l2c.avg_refs 2.151871 # Average number of references to valid blocks. system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10019.673951 # Average occupied blocks per context -system.l2c.occ_blocks::1 266.115685 # Average occupied blocks per context -system.l2c.occ_blocks::2 23831.931773 # Average occupied blocks per context -system.l2c.occ_percent::0 0.152888 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.004061 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.363646 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1620505 # number of ReadReq hits -system.l2c.ReadReq_hits::1 137130 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits -system.l2c.Writeback_hits::0 811846 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits system.l2c.Writeback_hits::total 811846 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 134 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 39 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 15 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 9 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 164417 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 14126 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 164417 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14126 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits -system.l2c.demand_hits::0 1784922 # number of demand (read+write) hits -system.l2c.demand_hits::1 151256 # number of demand (read+write) hits -system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 871618 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 913304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 101445 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 49811 # number of demand (read+write) hits system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits -system.l2c.overall_hits::0 1784922 # number of overall hits -system.l2c.overall_hits::1 151256 # number of overall hits -system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::cpu0.inst 871618 # number of overall hits +system.l2c.overall_hits::cpu0.data 913304 # number of overall hits +system.l2c.overall_hits::cpu1.inst 101445 # number of overall hits +system.l2c.overall_hits::cpu1.data 49811 # number of overall hits system.l2c.overall_hits::total 1936178 # number of overall hits -system.l2c.ReadReq_misses::0 956917 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4511 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 13362 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 943555 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2185 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2326 # number of ReadReq misses system.l2c.ReadReq_misses::total 961428 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2441 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 567 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2441 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 567 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 3008 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 65 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 101 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 65 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 101 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 117481 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 9826 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 117481 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9826 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 127307 # number of ReadExReq misses -system.l2c.demand_misses::0 1074398 # number of demand (read+write) misses -system.l2c.demand_misses::1 14337 # number of demand (read+write) misses -system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 13362 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 1061036 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2185 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 12152 # number of demand (read+write) misses system.l2c.demand_misses::total 1088735 # number of demand (read+write) misses -system.l2c.overall_misses::0 1074398 # number of overall misses -system.l2c.overall_misses::1 14337 # number of overall misses -system.l2c.overall_misses::2 0 # number of overall misses +system.l2c.overall_misses::cpu0.inst 13362 # number of overall misses +system.l2c.overall_misses::cpu0.data 1061036 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2185 # number of overall misses +system.l2c.overall_misses::cpu1.data 12152 # number of overall misses system.l2c.overall_misses::total 1088735 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2577422 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 141641 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1692442 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 38011 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2719063 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 811846 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 811846 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 811846 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2575 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 606 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 80 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 110 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 80 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 110 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 190 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 281898 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 23952 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281898 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23952 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 305850 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2859320 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 165593 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1974340 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61963 # number of demand (read+write) accesses system.l2c.demand_accesses::total 3024913 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2859320 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 165593 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1974340 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61963 # number of overall (read+write) accesses system.l2c.overall_accesses::total 3024913 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.371269 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.031848 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.947961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.935644 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.812500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.918182 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.416750 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.410237 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.375753 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.086580 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.375753 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.086580 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency -system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency -system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015099 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.557511 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.021085 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.061193 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947961 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.935644 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.812500 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.918182 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.416750 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.410237 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015099 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.537413 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.021085 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.196117 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015099 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.537413 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.021085 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.196117 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -129,28 +140,8 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 121798 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 no_value # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 no_value # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 121798 # number of writebacks +system.l2c.writebacks::total 121798 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41695 # number of replacements system.iocache.tagsinuse 0.435437 # Cycle average of tags in use @@ -158,50 +149,29 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 41711 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.435437 # Average occupied blocks per context -system.iocache.occ_percent::1 0.027215 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 175 # number of ReadReq misses +system.iocache.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.027215 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41727 # number of demand (read+write) misses +system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses system.iocache.demand_misses::total 41727 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41727 # number of overall misses +system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses system.iocache.overall_misses::total 41727 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 175 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41727 # number of demand (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41727 # number of overall (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -210,26 +180,8 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41520 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -278,7 +230,8 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 3740670933 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 57222076 # Number of instructions executed +system.cpu0.committedInsts 57222076 # Number of instructions committed +system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses system.cpu0.num_func_calls 1399585 # number of times a function call or return occured @@ -422,47 +375,30 @@ system.cpu0.icache.total_refs 56345132 # To system.cpu0.icache.sampled_refs 884916 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 63.672859 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.244754 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.998525 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 56345132 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998525 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 56345132 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 56345132 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits system.cpu0.icache.overall_hits::total 56345132 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 885000 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 885000 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 885000 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses system.cpu0.icache.overall_misses::total 885000 # number of overall misses -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 57230132 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 57230132 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 57230132 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.015464 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.015464 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.015464 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015464 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -471,26 +407,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 95 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 95 # number of writebacks +system.cpu0.icache.writebacks::total 95 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1978962 # number of replacements system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use @@ -498,68 +416,51 @@ system.cpu0.dcache.total_refs 13123502 # To system.cpu0.dcache.sampled_refs 1979474 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 504.827058 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.985990 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7298106 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 504.827058 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.985990 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.985990 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7298106 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7298106 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 5462265 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5462265 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5462265 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 172138 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172138 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 172138 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 186635 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186635 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 186635 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12760371 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 12760371 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12760371 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12760371 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 12760371 # number of overall hits system.cpu0.dcache.overall_hits::total 12760371 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1683563 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 1683563 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 285996 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 285996 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 285996 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 16159 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16159 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16159 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 703 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 703 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 703 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 1969559 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 1969559 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 1969559 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 1969559 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 1969559 # number of overall misses system.cpu0.dcache.overall_misses::total 1969559 # number of overall misses -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8981669 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 188297 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.187444 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.049753 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085817 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.003753 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.133711 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.133711 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187444 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049753 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085817 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.003753 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.133711 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.133711 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -568,26 +469,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 771740 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 771740 # number of writebacks +system.cpu0.dcache.writebacks::total 771740 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -624,7 +507,8 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.numCycles 3740248881 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 5931958 # Number of instructions executed +system.cpu1.committedInsts 5931958 # Number of instructions committed +system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses system.cpu1.num_func_calls 182742 # number of times a function call or return occured @@ -720,47 +604,30 @@ system.cpu1.icache.total_refs 5832136 # To system.cpu1.icache.sampled_refs 103603 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 56.293119 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 427.126317 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.834231 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 5832136 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.834231 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 5832136 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 5832136 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits system.cpu1.icache.overall_hits::total 5832136 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 103630 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 103630 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 103630 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses system.cpu1.icache.overall_misses::total 103630 # number of overall misses -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 5935766 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 5935766 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 5935766 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.017459 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.017459 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.017459 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -769,26 +636,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 15 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 15 # number of writebacks +system.cpu1.icache.writebacks::total 15 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 62338 # number of replacements system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use @@ -796,68 +645,51 @@ system.cpu1.dcache.total_refs 1834544 # To system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.765530 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 707444 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 15613 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 1816759 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 1816759 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 25861 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 732 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 67511 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 67511 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses system.cpu1.dcache.overall_misses::total 67511 # number of overall misses -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.035266 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044784 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.035829 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.035829 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -866,26 +698,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 39996 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks +system.cpu1.dcache.writebacks::total 39996 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index b72ae72cb..435421de9 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -71,6 +72,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -85,20 +87,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -121,20 +116,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -218,20 +206,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -250,20 +231,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -289,7 +263,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -359,7 +332,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -441,7 +413,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -458,7 +429,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -475,7 +445,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -492,7 +461,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -509,7 +477,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -526,7 +493,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -543,7 +509,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -560,7 +525,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -577,7 +541,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -594,7 +557,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -611,7 +573,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -628,7 +589,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -645,7 +605,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -662,7 +621,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -679,7 +637,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -696,7 +653,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -713,7 +669,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -730,7 +685,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -747,7 +701,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -763,7 +716,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -828,7 +780,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -839,7 +790,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index 9b658d14c..484a5fec9 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 04:22:39 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:36 gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index 7f4c99b34..d300de39a 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3300922 # Simulator instruction rate (inst/s) -host_tick_rate 100577077281 # Simulator tick rate (ticks/s) -host_mem_usage 294216 # Number of bytes of host memory used -host_seconds 18.19 # Real time elapsed on the host +host_inst_rate 4111639 # Simulator instruction rate (inst/s) +host_op_rate 4111633 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 125278906724 # Simulator tick rate (ticks/s) +host_mem_usage 291412 # Number of bytes of host memory used +host_seconds 14.60 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated +sim_ops 60038305 # Number of ops (including micro ops) simulated system.physmem.bytes_read 71650816 # Number of bytes read from this memory system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory system.physmem.bytes_written 10156864 # Number of bytes written to this memory @@ -25,67 +27,64 @@ system.l2c.total_refs 2291835 # To system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks. system.l2c.avg_refs 2.126306 # Average number of references to valid blocks. system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context -system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context -system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1699395 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits -system.l2c.Writeback_hits::0 825291 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits system.l2c.Writeback_hits::total 825291 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 185383 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits -system.l2c.demand_hits::0 1884778 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits -system.l2c.overall_hits::0 1884778 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::cpu.inst 905267 # number of overall hits +system.l2c.overall_hits::cpu.data 979511 # number of overall hits system.l2c.overall_hits::total 1884778 # number of overall hits -system.l2c.ReadReq_misses::0 959629 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 12 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 12 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 118859 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 118859 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 118859 # number of ReadExReq misses -system.l2c.demand_misses::0 1078488 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14936 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 1063552 # number of demand (read+write) misses system.l2c.demand_misses::total 1078488 # number of demand (read+write) misses -system.l2c.overall_misses::0 1078488 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::cpu.inst 14936 # number of overall misses +system.l2c.overall_misses::cpu.data 1063552 # number of overall misses system.l2c.overall_misses::total 1078488 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2659024 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1738821 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2659024 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 825291 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 825291 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 825291 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 304242 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2963266 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 2043063 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2963266 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2963266 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 2043063 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2963266 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.360895 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.923077 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.390673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.363952 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.363952 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency -system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 no_value # average overall miss latency -system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.inst 0.016231 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.543295 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.390673 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -94,26 +93,8 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 117189 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 117189 # number of writebacks +system.l2c.writebacks::total 117189 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41686 # number of replacements system.iocache.tagsinuse 1.225570 # Cycle average of tags in use @@ -121,50 +102,29 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 41702 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.225570 # Average occupied blocks per context -system.iocache.occ_percent::1 0.076598 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 174 # number of ReadReq misses +system.iocache.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.076598 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses system.iocache.ReadReq_misses::total 174 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41726 # number of demand (read+write) misses +system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses system.iocache.demand_misses::total 41726 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41726 # number of overall misses +system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses system.iocache.overall_misses::total 41726 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -173,26 +133,8 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41512 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -241,7 +183,8 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 3658664408 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 60038305 # Number of instructions executed +system.cpu.committedInsts 60038305 # Number of instructions committed +system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses system.cpu.num_func_calls 1484182 # number of times a function call or return occured @@ -380,47 +323,30 @@ system.cpu.icache.total_refs 59129922 # To system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.215243 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.998467 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 59129922 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.998467 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits -system.cpu.icache.demand_hits::0 59129922 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 59129922 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits system.cpu.icache.overall_hits::total 59129922 # number of overall hits -system.cpu.icache.ReadReq_misses::0 920221 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses -system.cpu.icache.demand_misses::0 920221 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 920221 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses system.cpu.icache.overall_misses::total 920221 # number of overall misses -system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 60050143 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 60050143 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 60050143 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.015324 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.015324 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.015324 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -429,26 +355,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 108 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 108 # number of writebacks +system.cpu.icache.writebacks::total 108 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2042700 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use @@ -456,65 +364,48 @@ system.cpu.dcache.total_refs 14038433 # To system.cpu.dcache.sampled_refs 2043212 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.997802 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 5848212 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 199282 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 13655994 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 13655994 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits system.cpu.dcache.overall_hits::total 13655994 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 304362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 2026067 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2026067 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses system.cpu.dcache.overall_misses::total 2026067 # number of overall misses -system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.049469 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.129196 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.129196 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,26 +414,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 825183 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks +system.cpu.dcache.writebacks::total 825183 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index 1a4bf8750..110cfac39 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -68,6 +69,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu0.tracer +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -82,20 +84,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -118,20 +113,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -174,6 +162,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu1.tracer +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -188,20 +177,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -224,20 +206,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -321,20 +296,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -353,20 +321,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -392,7 +353,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -462,7 +422,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -544,7 +503,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -561,7 +519,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -578,7 +535,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -595,7 +551,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -612,7 +567,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -629,7 +583,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -646,7 +599,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -663,7 +615,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -680,7 +631,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -697,7 +647,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -714,7 +663,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -731,7 +679,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -748,7 +695,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -765,7 +711,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -782,7 +727,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -799,7 +743,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -816,7 +759,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -833,7 +775,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -850,7 +791,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -866,7 +806,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -931,7 +870,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -942,7 +880,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index 3af3fc1dd..b1f645266 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 04:23:09 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:02 gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 562628000 diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 628ea2e3e..565674386 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.958647 # Nu sim_ticks 1958647095000 # Number of ticks simulated final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1643366 # Simulator instruction rate (inst/s) -host_tick_rate 54228566310 # Simulator tick rate (ticks/s) -host_mem_usage 293036 # Number of bytes of host memory used -host_seconds 36.12 # Real time elapsed on the host +host_inst_rate 1989502 # Simulator instruction rate (inst/s) +host_op_rate 1989500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65650485361 # Simulator tick rate (ticks/s) +host_mem_usage 290388 # Number of bytes of host memory used +host_seconds 29.83 # Real time elapsed on the host sim_insts 59355643 # Number of instructions simulated +sim_ops 59355643 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30050624 # Number of bytes read from this memory system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory system.physmem.bytes_written 10333120 # Number of bytes written to this memory @@ -25,122 +27,153 @@ system.l2c.total_refs 2371449 # To system.l2c.sampled_refs 427769 # Sample count of references to valid blocks. system.l2c.avg_refs 5.543761 # Average number of references to valid blocks. system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10867.929163 # Average occupied blocks per context -system.l2c.occ_blocks::1 199.983935 # Average occupied blocks per context -system.l2c.occ_blocks::2 23419.887612 # Average occupied blocks per context -system.l2c.occ_percent::0 0.165831 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.003052 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.357359 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1659395 # number of ReadReq hits -system.l2c.ReadReq_hits::1 119191 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 7139.593108 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 100.838318 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 99.145617 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.357359 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056890 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.108942 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001539 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.001513 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.526242 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 901389 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 758006 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 86187 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 33004 # number of ReadReq hits system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits -system.l2c.Writeback_hits::0 816294 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 816294 # number of Writeback hits system.l2c.Writeback_hits::total 816294 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 53 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 53 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 19 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 170288 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 12569 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 170288 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 12569 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 182857 # number of ReadExReq hits -system.l2c.demand_hits::0 1829683 # number of demand (read+write) hits -system.l2c.demand_hits::1 131760 # number of demand (read+write) hits -system.l2c.demand_hits::2 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 901389 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 928294 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 86187 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 45573 # number of demand (read+write) hits system.l2c.demand_hits::total 1961443 # number of demand (read+write) hits -system.l2c.overall_hits::0 1829683 # number of overall hits -system.l2c.overall_hits::1 131760 # number of overall hits -system.l2c.overall_hits::2 0 # number of overall hits +system.l2c.overall_hits::cpu0.inst 901389 # number of overall hits +system.l2c.overall_hits::cpu0.data 928294 # number of overall hits +system.l2c.overall_hits::cpu1.inst 86187 # number of overall hits +system.l2c.overall_hits::cpu1.data 45573 # number of overall hits system.l2c.overall_hits::total 1961443 # number of overall hits -system.l2c.ReadReq_misses::0 302827 # number of ReadReq misses -system.l2c.ReadReq_misses::1 1953 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 14371 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 288456 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 815 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1138 # number of ReadReq misses system.l2c.ReadReq_misses::total 304780 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2453 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 495 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2453 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 495 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2948 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 15 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 74 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 15 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 74 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 89 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 117546 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 6196 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 117546 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6196 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 123742 # number of ReadExReq misses -system.l2c.demand_misses::0 420373 # number of demand (read+write) misses -system.l2c.demand_misses::1 8149 # number of demand (read+write) misses -system.l2c.demand_misses::2 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 14371 # number of demand (read+write) misses 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miss cycles -system.l2c.SCUpgradeReq_miss_latency 416000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6434878000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22288518000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22288518000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1962222 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 121144 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu0.inst 747344500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 15004707000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 42364500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 59224000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15853640000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2244000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 780000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 3024000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 104000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 312000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 416000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6112681000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 322197000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6434878000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 747344500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 21117388000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 42364500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 381421000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22288518000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 747344500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 21117388000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 42364500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 381421000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22288518000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 915760 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1046462 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 87002 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 34142 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2083366 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 816294 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816294 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 816294 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2625 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 548 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2625 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 548 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 3173 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 33 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 93 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 33 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 93 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 126 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 287834 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 18765 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 287834 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18765 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 306599 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2250056 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 139909 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 915760 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1334296 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 87002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 52907 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2389965 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2250056 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 139909 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 915760 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1334296 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 87002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 52907 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2389965 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.154329 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.016121 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.934476 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.903285 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.454545 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.795699 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.408381 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.330189 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.186828 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.058245 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.186828 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.058245 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52352.135047 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 8117583.205325 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 1232.776192 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 6109.090909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 27733.333333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 5621.621622 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 54743.487656 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 1038553.582957 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 53020.812469 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 2735123.082587 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 53020.812469 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 2735123.082587 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015693 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.275649 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.033331 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.934476 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.903285 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.454545 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.795699 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.408381 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.330189 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015693 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.304282 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009368 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.138621 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015693 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.304282 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009368 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.138621 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 914.798206 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1575.757576 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6933.333333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4216.216216 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,61 +182,113 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 119935 # number of writebacks -system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 304769 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 2948 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 89 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 123742 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 428511 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 428511 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12195855000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 117981000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 3560000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4949974000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 17145829000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 17145829000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 802314500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1391411500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 2193726000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.155318 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.515758 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq 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accesses -system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.190445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 3.062784 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.190445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 3.062784 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40016.717580 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40020.691995 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40002.375911 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40012.576107 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40012.576107 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 119935 # number of writebacks +system.l2c.writebacks::total 119935 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.inst 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 14371 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 288456 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 804 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1138 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 304769 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2453 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 495 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2948 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 15 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 74 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 89 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 117546 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6196 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123742 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 14371 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 406002 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 804 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7334 # number of demand (read+write) MSHR misses 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+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 98181000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 19800000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 117981000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 600000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 2960000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 3560000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4702129000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 247845000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4949974000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 574888000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 16245364000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 32164000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 293413000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 17145829000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 574888000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 16245364000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 32164000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 293413000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 17145829000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 792100000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 10214500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 802314500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1122200000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 269211500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1391411500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1914300000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 279426000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2193726000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.275649 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.033331 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.934476 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.903285 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.454545 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.795699 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.408381 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.330189 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015693 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.304282 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.138621 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 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# miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115247.114943 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137701.766606 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137608.129320 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137608.129320 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64596068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked @@ -271,38 +339,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6176.122765 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41520 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41726 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 11004998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3560928000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3571932998 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3571932998 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85698.113208 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85604.491157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41520 # number of writebacks +system.iocache.writebacks::total 41520 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41726 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41726 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41726 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11004998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11004998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3560928000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3560928000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3571932998 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3571932998 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3571932998 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3571932998 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -351,7 +413,8 @@ system.cpu0.itb.data_accesses 0 # DT system.cpu0.numCycles 3916023774 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 54072652 # Number of instructions executed +system.cpu0.committedInsts 54072652 # Number of instructions committed +system.cpu0.committedOps 54072652 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 50043234 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 293967 # Number of float alu accesses system.cpu0.num_func_calls 1426863 # number of times a function call or return occured @@ -494,51 +557,39 @@ system.cpu0.icache.total_refs 53165471 # To system.cpu0.icache.sampled_refs 915659 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 58.062522 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 36696092000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 508.800486 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.993751 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 53165471 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 508.800486 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.993751 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.993751 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 53165471 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 53165471 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 53165471 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 53165471 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 53165471 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 53165471 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 53165471 # number of overall hits system.cpu0.icache.overall_hits::total 53165471 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 915781 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 915781 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 915781 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 915781 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 915781 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 915781 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 915781 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 915781 # number of overall misses system.cpu0.icache.overall_misses::total 915781 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 13429132500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 13429132500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 13429132500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 54081252 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13429132500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13429132500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13429132500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13429132500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13429132500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13429132500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 54081252 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 54081252 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 54081252 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 54081252 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 54081252 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 54081252 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 54081252 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 54081252 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.016933 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.016933 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.016933 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14664.130944 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14664.130944 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14664.130944 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016933 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016933 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016933 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -547,119 +598,96 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 55 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 915781 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 915781 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 915781 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 10681093500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 10681093500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 10681093500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.016933 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.016933 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.016933 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11663.370937 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11663.370937 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 55 # number of writebacks +system.cpu0.icache.writebacks::total 55 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915781 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 915781 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 915781 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 915781 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 915781 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 915781 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10681093500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10681093500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10681093500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10681093500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10681093500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10681093500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016933 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1338438 # number of replacements -system.cpu0.dcache.tagsinuse 502.524901 # Cycle average of tags in use +system.cpu0.dcache.tagsinuse 503.524900 # Cycle average of tags in use system.cpu0.dcache.total_refs 13348404 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 1338837 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 9.970149 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 503.524900 # Average occupied blocks per context -system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.983447 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7421006 # number of ReadReq hits +system.cpu0.dcache.warmup_cycle 83958000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 503.524900 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.983447 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.983447 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7421006 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7421006 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 5560133 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5560133 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5560133 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 176505 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 176505 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 176505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 191674 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 191674 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 191674 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12981139 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 12981139 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12981139 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12981139 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 12981139 # number of overall hits system.cpu0.dcache.overall_hits::total 12981139 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 1036101 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 1036101 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 1036101 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 291536 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 291536 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 291536 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 16544 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16544 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 16544 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 410 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 410 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 410 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 1327637 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 1327637 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 1327637 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 1327637 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 1327637 # number of overall misses system.cpu0.dcache.overall_misses::total 1327637 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 26570279500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 9109954000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 234949000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 2973000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 35680233500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 35680233500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8457107 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 26570279500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 26570279500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9109954000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9109954000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 234949000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 234949000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 2973000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 2973000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 35680233500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 35680233500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 35680233500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 35680233500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8457107 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 8457107 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5851669 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5851669 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5851669 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 193049 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 193049 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 193049 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 192084 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192084 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 192084 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 14308776 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 14308776 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 14308776 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 14308776 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.122512 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.049821 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.085698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.002134 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.092785 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.092785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 25644.487844 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 31248.127161 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14201.462766 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 7251.219512 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 26874.991809 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 26874.991809 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -668,54 +696,53 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 786441 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 1036101 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 291536 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 16544 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 410 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 1327637 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 1327637 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 23461938500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 8235346000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 185317000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1743000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 31697284500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 31697284500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 884470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1242107000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 2126577000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049821 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.085698 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.002134 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.092785 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.092785 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 4251.219512 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks +system.cpu0.dcache.writebacks::total 786441 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1036101 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1036101 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 291536 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16544 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16544 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 410 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 410 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1327637 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1327637 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1327637 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1327637 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 23461938500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 23461938500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8235346000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8235346000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 185317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 185317000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 1743000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1743000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 31697284500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 31697284500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 31697284500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 31697284500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 884470000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 884470000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1242107000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1242107000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2126577000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2126577000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.122512 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.049821 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.085698 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.002134 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.092785 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses @@ -752,7 +779,8 @@ system.cpu1.itb.data_accesses 0 # DT system.cpu1.numCycles 3917294190 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 5282991 # Number of instructions executed +system.cpu1.committedInsts 5282991 # Number of instructions committed +system.cpu1.committedOps 5282991 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses system.cpu1.num_func_calls 158031 # number of times a function call or return occured @@ -843,51 +871,39 @@ system.cpu1.icache.total_refs 5199349 # To system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 419.807616 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.819937 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 5199349 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 419.807616 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.819937 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.819937 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 5199349 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 5199349 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 5199349 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 5199349 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 5199349 # number of overall hits system.cpu1.icache.overall_hits::total 5199349 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 87005 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 87005 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 87005 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 87005 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 87005 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 87005 # number of overall misses system.cpu1.icache.overall_misses::total 87005 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 1260607500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 1260607500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 1260607500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 5286354 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 1260607500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 1260607500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 1260607500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 1260607500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 1260607500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 5286354 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 5286354 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 5286354 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 5286354 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.016458 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.016458 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.016458 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14488.908683 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14488.908683 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -896,32 +912,26 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 14 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 87005 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 87005 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 87005 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 999558500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 999558500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 999558500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016458 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.016458 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.016458 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 14 # number of writebacks +system.cpu1.icache.writebacks::total 14 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 87005 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 52960 # number of replacements system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use @@ -929,84 +939,69 @@ system.cpu1.dcache.total_refs 1644934 # To system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 389.521271 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.760784 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 1003161 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 389.521271 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.760784 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.760784 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 1003161 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 1003161 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 616899 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 616899 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 616899 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 11784 # number of LoadLockedReq hits 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of overall hits -system.cpu1.dcache.ReadReq_misses::0 37113 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 37113 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 37113 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 20421 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 20421 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 20421 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 982 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 982 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 982 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 505 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 505 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 505 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 57534 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 57534 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 57534 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 57534 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 57534 # number of overall misses system.cpu1.dcache.overall_misses::total 57534 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 533263000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 556796000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 13079000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 6416000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 1090059000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 1090059000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 1040274 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 533263000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 533263000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 556796000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 556796000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13079000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 13079000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6416000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 6416000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1090059000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1090059000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1090059000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1090059000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040274 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 1040274 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 637320 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 637320 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 637320 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12766 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 12031 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12031 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 1677594 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 1677594 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 1677594 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.035676 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.032042 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.076923 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.041975 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.034296 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.034296 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1015,54 +1010,53 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 29784 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 37113 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 20421 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 982 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 505 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 57534 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 57534 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 421922000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 495533000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10133000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 4901000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 917455000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 917455000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 11413500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 298050500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 309464000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035676 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.032042 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.076923 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.041975 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.034296 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.034296 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9704.950495 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks +system.cpu1.dcache.writebacks::total 29784 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 982 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 982 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 505 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 505 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 57534 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 57534 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 57534 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 57534 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 421922000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 421922000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 495533000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 495533000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 10133000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 10133000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4901000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4901000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 917455000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 917455000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 917455000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 917455000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11413500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11413500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 54195aa23..c8fe39e38 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -68,6 +69,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu.tracer +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -82,20 +84,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -118,20 +113,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -215,20 +203,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -247,20 +228,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -286,7 +260,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -356,7 +329,6 @@ pio=system.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[1] @@ -438,7 +410,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -455,7 +426,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -472,7 +442,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -489,7 +458,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -506,7 +474,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -523,7 +490,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -540,7 +506,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -557,7 +522,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -574,7 +538,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -591,7 +554,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -608,7 +570,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -625,7 +586,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -642,7 +602,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -659,7 +618,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -676,7 +634,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -693,7 +650,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -710,7 +666,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -727,7 +682,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -744,7 +698,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=system.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -760,7 +713,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=system.tsunami system=system pio=system.iobus.port[22] @@ -825,7 +777,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=system.tsunami system=system time=Thu Jan 1 00:00:00 2009 tsunami=system.tsunami @@ -836,7 +787,6 @@ pio=system.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=system.tsunami system=system tsunami=system.tsunami pio=system.iobus.port[2] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index 826f2c28b..e3d6e41ac 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 04:22:43 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:47 gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1915548867000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index ac9598c08..713b264a4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 1.915549 # Nu sim_ticks 1915548867000 # Number of ticks simulated final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1659827 # Simulator instruction rate (inst/s) -host_tick_rate 56637748152 # Simulator tick rate (ticks/s) -host_mem_usage 290988 # Number of bytes of host memory used -host_seconds 33.82 # Real time elapsed on the host +host_inst_rate 1998214 # Simulator instruction rate (inst/s) +host_op_rate 1998212 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68184353129 # Simulator tick rate (ticks/s) +host_mem_usage 288188 # Number of bytes of host memory used +host_seconds 28.09 # Real time elapsed on the host sim_insts 56137087 # Number of instructions simulated +sim_ops 56137087 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29663360 # Number of bytes read from this memory system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory system.physmem.bytes_written 10122368 # Number of bytes written to this memory @@ -25,79 +27,85 @@ system.l2c.total_refs 2311163 # To system.l2c.sampled_refs 421794 # Sample count of references to valid blocks. system.l2c.avg_refs 5.479364 # Average number of references to valid blocks. system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context -system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context -system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1710461 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.inst 913599 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 796862 # number of ReadReq hits system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits -system.l2c.Writeback_hits::0 826671 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 826671 # number of Writeback hits system.l2c.Writeback_hits::total 826671 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 6 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 185878 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 185878 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits -system.l2c.demand_hits::0 1896339 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 913599 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 982740 # number of demand (read+write) hits system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits -system.l2c.overall_hits::0 1896339 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits +system.l2c.overall_hits::cpu.inst 913599 # number of overall hits +system.l2c.overall_hits::cpu.data 982740 # number of overall hits system.l2c.overall_hits::total 1896339 # number of overall hits -system.l2c.ReadReq_misses::0 304138 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14735 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 289403 # number of ReadReq misses system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 7 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 118294 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 118294 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses -system.l2c.demand_misses::0 422432 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14735 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 407697 # number of demand (read+write) misses system.l2c.demand_misses::total 422432 # number of demand (read+write) misses -system.l2c.overall_misses::0 422432 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses +system.l2c.overall_misses::cpu.inst 14735 # number of overall misses +system.l2c.overall_misses::cpu.data 407697 # number of overall misses system.l2c.overall_misses::total 422432 # number of overall misses -system.l2c.ReadReq_miss_latency 15820206500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 248000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6151753000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 21971959500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 21971959500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2014599 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.inst 766261500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 15053945000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15820206500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 248000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 248000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6151753000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6151753000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.inst 766261500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 21205698000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 21971959500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.inst 766261500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 928334 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086265 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 826671 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 826671 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 304172 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2318771 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 928334 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1390437 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2318771 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 928334 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1390437 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.150967 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.538462 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.388905 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.182179 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.182179 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52016.540189 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52003.930884 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52013.009194 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52013.009194 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.inst 0.015873 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.266420 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.538462 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.388905 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.inst 0.015873 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.293215 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.inst 0.015873 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.293215 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52013.377582 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,48 +114,59 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 116650 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 304138 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 118294 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 422432 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 422432 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12170545000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 320000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4732225000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 16902770000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 16902770000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1083819500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1856492500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.150967 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.538462 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.388905 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.182179 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.182179 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40012.996175 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 116650 # number of writebacks +system.l2c.writebacks::total 116650 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.inst 14735 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 289403 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 304138 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 118294 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 118294 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 14735 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 407697 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 422432 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 14735 # 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number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16902770000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 589436000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 16313334000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16902770000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 772673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1083819500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1083819500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 1856492500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1856492500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.266420 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.538462 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.388905 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015873 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.293215 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements system.iocache.tagsinuse 1.340325 # Cycle average of tags in use @@ -155,58 +174,41 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1750545944000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.340325 # Average occupied blocks per context -system.iocache.occ_percent::1 0.083770 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 173 # number of ReadReq misses +system.iocache.occ_blocks::tsunami.ide 1.340325 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.083770 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.083770 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses +system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41725 # number of demand (read+write) misses +system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41725 # number of overall misses +system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19940998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5722300806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5742241804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5742241804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::tsunami.ide 19940998 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 19940998 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 5722300806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 5722300806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 5742241804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5742241804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 5742241804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5742241804 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115265.884393 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137714.208847 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137621.133709 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137621.133709 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 64604060 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked @@ -215,38 +217,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6166.863307 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41512 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10944998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3561447990 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3572392988 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3572392988 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85617.567118 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 41512 # number of writebacks +system.iocache.writebacks::total 41512 # number of writebacks +system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 10944998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 10944998 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 3561447990 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3561447990 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 3572392988 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3572392988 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 3572392988 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3572392988 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -295,7 +291,8 @@ system.cpu.itb.data_accesses 0 # DT system.cpu.numCycles 3831097734 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 56137087 # Number of instructions executed +system.cpu.committedInsts 56137087 # Number of instructions committed +system.cpu.committedOps 56137087 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 52011214 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 324192 # Number of float alu accesses system.cpu.num_func_calls 1482242 # number of times a function call or return occured @@ -434,51 +431,39 @@ system.cpu.icache.total_refs 55220553 # To system.cpu.icache.sampled_refs 928194 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 59.492469 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 36307428000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 508.721464 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.993597 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 55220553 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 508.721464 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.993597 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.993597 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 55220553 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 55220553 # number of ReadReq hits -system.cpu.icache.demand_hits::0 55220553 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 55220553 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 55220553 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 55220553 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 55220553 # number of overall hits system.cpu.icache.overall_hits::total 55220553 # number of overall hits -system.cpu.icache.ReadReq_misses::0 928354 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 928354 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 928354 # number of ReadReq misses -system.cpu.icache.demand_misses::0 928354 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 928354 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 928354 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 928354 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 928354 # number of overall misses system.cpu.icache.overall_misses::total 928354 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13616370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13616370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13616370500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 56148907 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13616370500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13616370500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13616370500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13616370500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13616370500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13616370500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56148907 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56148907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 56148907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 56148907 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 56148907 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 56148907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56148907 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.016534 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.016534 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.016534 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14667.218001 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14667.218001 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016534 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016534 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016534 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -487,32 +472,26 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 85 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 928354 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 928354 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 928354 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10830625500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10830625500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10830625500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016534 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.016534 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.016534 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 85 # number of writebacks +system.cpu.icache.writebacks::total 85 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928354 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928354 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928354 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928354 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928354 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928354 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10830625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10830625500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10830625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10830625500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10830625500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10830625500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016534 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1390115 # number of replacements system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use @@ -520,77 +499,63 @@ system.cpu.dcache.total_refs 14038335 # To system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.094968 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.984023 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999969 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 7807536 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.984023 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999969 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999969 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 7807536 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7807536 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 5848554 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5848554 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 5848554 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 183025 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 183025 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 183025 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 199203 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199203 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199203 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 13656090 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 13656090 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 13656090 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 13656090 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 13656090 # number of overall hits system.cpu.dcache.overall_hits::total 13656090 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1069110 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1069110 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1069110 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 304335 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 17201 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17201 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17201 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 1373445 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1373445 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1373445 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 1373445 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1373445 # number of overall misses system.cpu.dcache.overall_misses::total 1373445 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 27121920500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 9228484000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 245980000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 36350404500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 36350404500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 8876646 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27121920500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27121920500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9228484000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9228484000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245980000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 245980000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36350404500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36350404500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36350404500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36350404500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8876646 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8876646 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6152889 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6152889 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6152889 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 200226 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200226 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 200226 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 199203 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199203 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 199203 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 15029535 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 15029535 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 15029535 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 15029535 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15029535 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15029535 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.120441 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.049462 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085908 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.091383 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.091383 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 26466.589124 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 26466.589124 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120441 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049462 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085908 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091383 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091383 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,48 +564,47 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 826586 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1069110 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 304335 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17201 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1373445 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1373445 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23914545000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8315479000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 194377000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32230024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32230024000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1199607500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2062370500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120441 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.049462 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.085908 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.091383 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.091383 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 826586 # number of writebacks +system.cpu.dcache.writebacks::total 826586 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069110 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069110 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17201 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17201 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1373445 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373445 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373445 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373445 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23914545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23914545000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8315479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8315479000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 194377000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 194377000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32230024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 04178bb32..614929bfc 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -1,18 +1,11 @@ -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -hack: be nice to actually delete the event here +Traceback (most recent call last): + File "<string>", line 1, in <module> + File "/tmp/gem5.ali/src/python/m5/main.py", line 357, in main + exec filecode in scope + File "tests/run.py", line 70, in <module> + execfile(joinpath(tests_root, 'configs', test_filename + '.py')) + File "tests/configs/realview-simple-atomic-dual.py", line 86, in <module> + system.l2c.num_cpus = 2 + File "/tmp/gem5.ali/src/python/m5/SimObject.py", line 725, in __setattr__ + % (self.__class__.__name__, attr) +AttributeError: Class L2 has no parameter num_cpus diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 417579719..d3606030f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,7 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:25:02 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:37:03 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 -info: Using bootloader at address 0x80000000 -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2411694099500 because m5_exit instruction encountered +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 2ca0aa5cb..e69de29bb 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,719 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.411694 # Number of seconds simulated -sim_ticks 2411694099500 # Number of ticks simulated -final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2039542 # Simulator instruction rate (inst/s) -host_tick_rate 61821688958 # Simulator tick rate (ticks/s) -host_mem_usage 378872 # Number of bytes of host memory used -host_seconds 39.01 # Real time elapsed on the host -sim_insts 79563488 # Number of instructions simulated -system.nvmem.bytes_read 68 # Number of bytes read from this memory -system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory -system.nvmem.bytes_written 0 # Number of bytes written to this memory -system.nvmem.num_reads 17 # Number of read requests responded to by this memory -system.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.nvmem.num_other 0 # Number of other requests responded to by this memory -system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s) -system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s) -system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 123270308 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10185232 # Number of bytes written to this memory -system.physmem.num_reads 14146769 # Number of read requests responded to by this memory -system.physmem.num_writes 869038 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 127720 # number of replacements -system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use -system.l2c.total_refs 1498989 # Total number of references to valid blocks. -system.l2c.sampled_refs 156132 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.600780 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context -system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context -system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context -system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits -system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits -system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits -system.l2c.Writeback_hits::0 580461 # number of Writeback hits -system.l2c.Writeback_hits::total 580461 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits -system.l2c.demand_hits::0 771021 # number of demand (read+write) hits -system.l2c.demand_hits::1 537612 # number of demand (read+write) hits -system.l2c.demand_hits::2 12920 # number of demand (read+write) hits -system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits -system.l2c.overall_hits::0 771021 # number of overall hits -system.l2c.overall_hits::1 537612 # number of overall hits -system.l2c.overall_hits::2 12920 # number of overall hits -system.l2c.overall_hits::total 1321553 # number of overall hits -system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses -system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses -system.l2c.ReadReq_misses::2 52 # number of ReadReq misses -system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses -system.l2c.demand_misses::0 118723 # number of demand (read+write) misses -system.l2c.demand_misses::1 64009 # number of demand (read+write) misses -system.l2c.demand_misses::2 52 # number of demand (read+write) misses -system.l2c.demand_misses::total 182784 # number of demand (read+write) misses -system.l2c.overall_misses::0 118723 # number of overall misses -system.l2c.overall_misses::1 64009 # number of overall misses -system.l2c.overall_misses::2 52 # number of overall misses -system.l2c.overall_misses::total 182784 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 111818 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.dtb.inst_hits 0 # ITB inst hits -system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9339288 # DTB read hits -system.cpu0.dtb.read_misses 5153 # DTB read misses -system.cpu0.dtb.write_hits 6907876 # DTB write hits -system.cpu0.dtb.write_misses 1048 # DTB write misses -system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch -system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9344441 # DTB read accesses -system.cpu0.dtb.write_accesses 6908924 # DTB write accesses -system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 16247164 # DTB hits -system.cpu0.dtb.misses 6201 # DTB misses -system.cpu0.dtb.accesses 16253365 # DTB accesses -system.cpu0.itb.inst_hits 34822552 # ITB inst hits -system.cpu0.itb.inst_misses 2978 # ITB inst misses -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB -system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses -system.cpu0.itb.hits 34822552 # DTB hits -system.cpu0.itb.misses 2978 # DTB misses -system.cpu0.itb.accesses 34825530 # DTB accesses -system.cpu0.numCycles 4823340800 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 44975797 # Number of instructions executed -system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses -system.cpu0.num_func_calls 1311755 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39858123 # number of integer instructions -system.cpu0.num_fp_insts 4945 # number of float instructions -system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written -system.cpu0.num_mem_refs 17030946 # number of memory refs -system.cpu0.num_load_insts 9786549 # Number of load instructions -system.cpu0.num_store_insts 7244397 # Number of store instructions -system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles -system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles -system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles -system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed -system.cpu0.icache.replacements 504460 # number of replacements -system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use -system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 34319155 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34319155 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 34319155 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 34319155 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 34319155 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 504973 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 504973 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 504973 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 504973 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 504973 # number of overall misses -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 34824128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 34824128 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 34824128 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 34824128 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.014501 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.014501 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.014501 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 24728 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 380107 # number of replacements -system.cpu0.dcache.tagsinuse 479.716402 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14708286 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 380619 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 479.716402 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.936946 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7803296 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 6534059 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 172314 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 174866 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 174866 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 14337355 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14337355 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 14337355 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 14337355 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 237350 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 237350 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 183580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183580 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9878 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9878 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 7293 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 420930 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 420930 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 420930 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 420930 # number of overall misses -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 8040646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8040646 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 6717639 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6717639 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 182192 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 182159 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 14758285 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14758285 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 14758285 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14758285 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.029519 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.027328 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.054218 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.040036 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.028522 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.028522 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 339627 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dtb.inst_hits 0 # ITB inst hits -system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6258230 # DTB read hits -system.cpu1.dtb.read_misses 2159 # DTB read misses -system.cpu1.dtb.write_hits 4713962 # DTB write hits -system.cpu1.dtb.write_misses 1181 # DTB write misses -system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1498 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 92 # Number of TLB faults due to prefetch -system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6260389 # DTB read accesses -system.cpu1.dtb.write_accesses 4715143 # DTB write accesses -system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10972192 # DTB hits -system.cpu1.dtb.misses 3340 # DTB misses -system.cpu1.dtb.accesses 10975532 # DTB accesses -system.cpu1.itb.inst_hits 27739434 # ITB inst hits -system.cpu1.itb.inst_misses 1388 # ITB inst misses -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1342 # Number of entries that have been flushed from TLB -system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 27740822 # ITB inst accesses -system.cpu1.itb.hits 27739434 # DTB hits -system.cpu1.itb.misses 1388 # DTB misses -system.cpu1.itb.accesses 27740822 # DTB accesses -system.cpu1.numCycles 4822838236 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 34587691 # Number of instructions executed -system.cpu1.num_int_alu_accesses 30998246 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5772 # Number of float alu accesses -system.cpu1.num_func_calls 758024 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3375080 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30998246 # number of integer instructions -system.cpu1.num_fp_insts 5772 # number of float instructions -system.cpu1.num_int_register_reads 156835040 # number of times the integer registers were read -system.cpu1.num_int_register_writes 33469179 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3980 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1792 # number of times the floating registers were written -system.cpu1.num_mem_refs 11415835 # number of memory refs -system.cpu1.num_load_insts 6478994 # Number of load instructions -system.cpu1.num_store_insts 4936841 # Number of store instructions -system.cpu1.num_idle_cycles 4787960178.177661 # Number of idle cycles -system.cpu1.num_busy_cycles 34878057.822339 # Number of busy cycles -system.cpu1.not_idle_fraction 0.007232 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.992768 # Percentage of idle cycles -system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 33011 # number of quiesce instructions executed -system.cpu1.icache.replacements 374406 # number of replacements -system.cpu1.icache.tagsinuse 498.143079 # Cycle average of tags in use -system.cpu1.icache.total_refs 27365572 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 374918 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 72.990819 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69956143000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.143079 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.972936 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 27365572 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 27365572 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 27365572 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 27365572 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 27365572 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 27365572 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 374920 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 374920 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 374920 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 374920 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 374920 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 374920 # number of overall misses -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 27740492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 27740492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 27740492 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 27740492 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 27740492 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 27740492 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.013515 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.013515 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.013515 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 13905 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 247434 # number of replacements -system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 277266 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 277266 # number of overall misses -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 202201 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs no_value # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index 5b5bd9164..5cb72c285 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -93,6 +93,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -107,20 +108,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -152,20 +146,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -217,20 +204,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -249,20 +229,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -288,7 +261,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -330,7 +302,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -340,7 +311,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -410,7 +380,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -422,7 +391,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -432,7 +400,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -461,7 +428,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -471,7 +437,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -481,7 +446,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -494,7 +458,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -508,7 +471,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -519,7 +481,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -538,7 +499,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -548,7 +508,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -557,7 +516,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -569,7 +527,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -579,7 +536,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -589,7 +545,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -599,7 +554,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -609,7 +563,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -623,7 +576,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -637,7 +589,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -660,7 +611,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -670,7 +620,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -680,7 +629,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -690,7 +638,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index e355498ce..31542346f 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:24:55 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:36:22 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index e3050fa31..d895bb120 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.332317 # Nu sim_ticks 2332316587000 # Number of ticks simulated final_tick 2332316587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2072038 # Simulator instruction rate (inst/s) -host_tick_rate 63144661085 # Simulator tick rate (ticks/s) -host_mem_usage 379208 # Number of bytes of host memory used -host_seconds 36.94 # Real time elapsed on the host -sim_insts 76532931 # Number of instructions simulated +host_inst_rate 2011652 # Simulator instruction rate (inst/s) +host_op_rate 2597875 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79169370264 # Simulator tick rate (ticks/s) +host_mem_usage 376316 # Number of bytes of host memory used +host_seconds 29.46 # Real time elapsed on the host +sim_insts 59262876 # Number of instructions simulated +sim_ops 76532931 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 20 # Number of bytes read from this memory system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,72 +36,92 @@ system.l2c.total_refs 1520830 # To system.l2c.sampled_refs 146847 # Sample count of references to valid blocks. system.l2c.avg_refs 10.356562 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10591.091336 # Average occupied blocks per context -system.l2c.occ_blocks::1 13649.297042 # Average occupied blocks per context -system.l2c.occ_percent::0 0.161607 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.208272 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1188216 # number of ReadReq hits -system.l2c.ReadReq_hits::1 10669 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 13639.466210 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 7.864412 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 1.966419 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5246.411267 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5344.680069 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.208122 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000120 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000030 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.080054 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.081553 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.369879 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7522 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3147 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 831710 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 356506 # number of ReadReq hits system.l2c.ReadReq_hits::total 1198885 # number of ReadReq hits -system.l2c.Writeback_hits::0 604613 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 604613 # number of Writeback hits system.l2c.Writeback_hits::total 604613 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 105791 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 105791 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 105791 # number of ReadExReq hits -system.l2c.demand_hits::0 1294007 # number of demand (read+write) hits -system.l2c.demand_hits::1 10669 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 7522 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3147 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 831710 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 462297 # number of demand (read+write) hits system.l2c.demand_hits::total 1304676 # number of demand (read+write) hits -system.l2c.overall_hits::0 1294007 # number of overall hits -system.l2c.overall_hits::1 10669 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 7522 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3147 # number of overall hits +system.l2c.overall_hits::cpu.inst 831710 # number of overall hits +system.l2c.overall_hits::cpu.data 462297 # number of overall hits system.l2c.overall_hits::total 1304676 # number of overall hits -system.l2c.ReadReq_misses::0 31716 # number of ReadReq misses -system.l2c.ReadReq_misses::1 27 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 19 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14294 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 17422 # number of ReadReq misses system.l2c.ReadReq_misses::total 31743 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2911 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 2911 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2911 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 141169 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 141169 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 141169 # number of ReadExReq misses -system.l2c.demand_misses::0 172885 # number of demand (read+write) misses -system.l2c.demand_misses::1 27 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 19 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 8 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14294 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 158591 # number of demand (read+write) misses system.l2c.demand_misses::total 172912 # number of demand (read+write) misses -system.l2c.overall_misses::0 172885 # number of overall misses -system.l2c.overall_misses::1 27 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 8 # number of overall misses +system.l2c.overall_misses::cpu.inst 14294 # number of overall misses +system.l2c.overall_misses::cpu.data 158591 # number of overall misses system.l2c.overall_misses::total 172912 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1219932 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 10696 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.dtb.walker 7541 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3155 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 846004 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 373928 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1230628 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 604613 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 604613 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 604613 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2937 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2937 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2937 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 246960 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 246960 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 246960 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1466892 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 10696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 7541 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3155 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 846004 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 620888 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1477588 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1466892 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 10696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 7541 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3155 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 846004 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 620888 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1477588 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025998 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002524 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028522 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.991147 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.571627 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.117858 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002524 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.120382 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.117858 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002524 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.120382 # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002520 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.002536 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016896 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.046592 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991147 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.571627 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.002520 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.002536 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016896 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.255426 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.002520 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.002536 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016896 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.255426 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -108,26 +130,8 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102531 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 102531 # number of writebacks +system.l2c.writebacks::total 102531 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -180,7 +184,8 @@ system.cpu.itb.accesses 60278360 # DT system.cpu.numCycles 4664556206 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 76532931 # Number of instructions executed +system.cpu.committedInsts 59262876 # Number of instructions committed +system.cpu.committedOps 76532931 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 68161177 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1971944 # number of times a function call or return occured @@ -206,47 +211,30 @@ system.cpu.icache.total_refs 59429083 # To system.cpu.icache.sampled_refs 847566 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 70.117351 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 5705452000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.678552 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.999372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 59429083 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 511.678552 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59429083 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 59429083 # number of ReadReq hits -system.cpu.icache.demand_hits::0 59429083 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 59429083 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 59429083 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 59429083 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 59429083 # number of overall hits system.cpu.icache.overall_hits::total 59429083 # number of overall hits -system.cpu.icache.ReadReq_misses::0 847566 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 847566 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 847566 # number of ReadReq misses -system.cpu.icache.demand_misses::0 847566 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 847566 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 847566 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 847566 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 847566 # number of overall misses system.cpu.icache.overall_misses::total 847566 # number of overall misses -system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 60276649 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::cpu.inst 60276649 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 60276649 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 60276649 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 60276649 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 60276649 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 60276649 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60276649 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60276649 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.014061 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.014061 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.014061 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014061 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014061 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014061 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -255,26 +243,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 44721 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 44721 # number of writebacks +system.cpu.icache.writebacks::total 44721 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 622134 # number of replacements system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use @@ -282,65 +252,48 @@ system.cpu.dcache.total_refs 23580069 # To system.cpu.dcache.sampled_refs 622646 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 37.870747 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.997030 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 13150366 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13150366 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9943631 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 23093997 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 23093997 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 23093997 # number of overall hits system.cpu.dcache.overall_hits::total 23093997 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 614445 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses system.cpu.dcache.overall_misses::total 614445 # number of overall misses -system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13514914 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10193528 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23708442 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23708442 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,26 +302,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 559892 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks +system.cpu.dcache.writebacks::total 559892 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -376,38 +311,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -416,26 +319,6 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 82d6c82a5..73f5e0c76 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -19,7 +19,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.nvmem +memories=system.nvmem system.physmem midr_regval=890224640 num_work_ids=16 physmem=system.physmem @@ -90,6 +90,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu0.tracer +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -104,20 +105,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -149,20 +143,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -214,6 +201,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu1.tracer +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -228,20 +216,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -273,20 +254,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -338,20 +312,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -370,20 +337,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=2 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -409,7 +369,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -451,7 +410,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -461,7 +419,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -531,7 +488,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -543,7 +499,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -553,7 +508,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -582,7 +536,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -592,7 +545,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -602,7 +554,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -615,7 +566,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -629,7 +579,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -640,7 +589,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -659,7 +607,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -669,7 +616,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -678,7 +624,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -690,7 +635,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -700,7 +644,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -710,7 +653,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -720,7 +662,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -730,7 +671,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -744,7 +684,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -758,7 +697,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -781,7 +719,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -791,7 +728,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -801,7 +737,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -811,7 +746,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 2f40c0e53..83064ae1d 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:25:02 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:38:22 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 6f6f084e3..46b5d4b73 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.669611 # Nu sim_ticks 2669611225000 # Number of ticks simulated final_tick 2669611225000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 842154 # Simulator instruction rate (inst/s) -host_tick_rate 28671225175 # Simulator tick rate (ticks/s) -host_mem_usage 380676 # Number of bytes of host memory used -host_seconds 93.11 # Real time elapsed on the host -sim_insts 78413959 # Number of instructions simulated +host_inst_rate 868396 # Simulator instruction rate (inst/s) +host_op_rate 1110924 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37821516206 # Simulator tick rate (ticks/s) +host_mem_usage 377896 # Number of bytes of host memory used +host_seconds 70.58 # Real time elapsed on the host +sim_insts 61295262 # Number of instructions simulated +sim_ops 78413959 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 68 # Number of bytes read from this memory system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,127 +36,233 @@ system.l2c.total_refs 1540412 # To system.l2c.sampled_refs 157158 # Sample count of references to valid blocks. system.l2c.avg_refs 9.801677 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 6351.465954 # Average occupied blocks per context -system.l2c.occ_blocks::1 4614.904109 # Average occupied blocks per context -system.l2c.occ_blocks::2 15206.143377 # Average occupied blocks per context -system.l2c.occ_percent::0 0.096916 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.070418 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.232027 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 562859 # number of ReadReq hits -system.l2c.ReadReq_hits::1 656143 # number of ReadReq hits -system.l2c.ReadReq_hits::2 11798 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 15197.869059 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 8.069070 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.114155 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2680.486069 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3670.979885 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.091092 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.000002 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2441.904066 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2173.000042 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.231901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000123 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.040901 # Average percentage of cache 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-system.l2c.UpgradeReq_miss_latency 56471000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 6300000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7751543000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9564047500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9564047500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 581514 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 672177 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 11848 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1250500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 728500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 402353500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 568569000 # number of ReadReq miss cycles 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system.l2c.Writeback_accesses::total 589400 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 4658 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 5915 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 4658 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5915 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 10573 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 714 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 800 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 714 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 800 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1514 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 139830 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 110078 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 139830 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 110078 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 249908 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 721344 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 782255 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 11848 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 4261 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1516 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 378834 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 342510 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 4193 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1878 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 506630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 275625 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1515447 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 721344 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 782255 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 11848 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4261 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1516 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 378834 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 342510 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 4193 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1878 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 506630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 275625 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1515447 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.032080 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.023854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.004220 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.060154 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.754616 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.883009 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.764706 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.767500 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.696017 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.468068 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.160782 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.086363 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.004220 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.251365 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.160782 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.086363 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.004220 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.251365 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 97159.179845 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 113041.318448 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 36250090 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 36460290.498293 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79646.777773 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 150445.287633 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 82463.614103 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 141567.949022 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 191280950 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 191504981.563124 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 82463.614103 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 141567.949022 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 191280950 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 191504981.563124 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.009235 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.020399 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.053913 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.002130 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.014869 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.051351 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.754616 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.883009 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764706 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.767500 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.696017 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.468068 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.009235 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.020399 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.316052 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.002130 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.014869 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.217778 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.005632 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.009235 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.020399 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.316052 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001908 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.002130 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.014869 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.217778 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52064.376294 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52033.403496 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52267.489712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375.955770 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 7304.694168 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5896.036760 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3047.619048 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7550.488599 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.479142 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52160.818259 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52104.166667 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52035.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52064.376294 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52032.572447 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 52267.489712 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52191.286964 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -163,61 +271,172 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 111955 # number of writebacks -system.l2c.ReadReq_mshr_hits 9 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 9 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 9 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 34730 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 8738 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1160 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148848 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 183578 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 183578 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1395310000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 350593500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 46546000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5965367000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7360677000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7360677000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131926671000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 31372379500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 163299050500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.059723 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.051668 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 2.931296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 3.042688 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.875912 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 1.477261 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.624650 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.450000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 1.064493 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.352205 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.254494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.234678 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 15.494429 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 15.983602 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.254494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.234678 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 15.494429 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 15.983602 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40095.637822 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 111955 # number of writebacks +system.l2c.writebacks::total 111955 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 24 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 7727 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 10919 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 7533 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 8501 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 34730 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 3515 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5223 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8738 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 546 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 614 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1160 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 97324 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 51524 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 148848 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 24 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 7727 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 108243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 8 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 7533 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 60025 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 183578 # number of demand (read+write) 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309600000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 437141000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 320000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 160000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 303331000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 343236000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1395310000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 140869500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 209724000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 350593500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 21887000 # number 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of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 160000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 303331000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2412482000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7360677000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 265520000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 8189961000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3961000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123467229000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131926671000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 30961750000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 410629500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31372379500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 265520000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 39151711000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3961000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 123877858500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163299050500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.053873 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051351 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.754616 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.883009 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764706 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.767500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.696017 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.468068 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average ReadReq mshr miss latency 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average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40161.237785 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.479142 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40160.818259 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -270,7 +489,8 @@ system.cpu0.itb.accesses 35749115 # DT system.cpu0.numCycles 5337805216 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.num_insts 43969024 # Number of instructions executed +system.cpu0.committedInsts 35373502 # Number of instructions committed +system.cpu0.committedOps 43969024 # Number of ops (including micro ops) committed system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses system.cpu0.num_func_calls 977479 # number of times a function call or return occured @@ -296,51 +516,39 @@ system.cpu0.icache.total_refs 35367311 # To system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits +system.cpu0.icache.occ_blocks::cpu0.inst 510.849663 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.997753 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 35367311 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 35367311 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 35367311 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 35367311 # number of overall hits -system.cpu0.icache.overall_hits::1 0 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 35367311 # number of overall hits system.cpu0.icache.overall_hits::total 35367311 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 380583 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 380583 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 380583 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 380583 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::0 380583 # number of overall misses -system.cpu0.icache.overall_misses::1 0 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 380583 # number of overall misses system.cpu0.icache.overall_misses::total 380583 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency 5651439000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency 5651439000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::0 35747894 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5651439000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5651439000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5651439000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5651439000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5651439000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5651439000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 35747894 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::0 35747894 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::0 35747894 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 35747894 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::0 0.010646 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.010646 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010646 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010646 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010646 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.425749 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,34 +557,32 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks 12960 # number of writebacks -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses 380583 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::0 0.010646 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks +system.cpu0.icache.writebacks::total 12960 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 380583 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 380583 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 380583 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 380583 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 380583 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 380583 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4509188500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4509188500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4509188500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4509188500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4509188500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4509188500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 351814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 351814000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 351814000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010646 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 334596 # number of replacements system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use @@ -384,84 +590,69 @@ system.cpu0.dcache.total_refs 12875674 # To system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context -system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 450.118381 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.879137 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 7428609 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5172633 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126778 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127996 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::0 12601242 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 12601242 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits -system.cpu0.dcache.overall_hits::1 0 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 12601242 # number of overall hits system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits -system.cpu0.dcache.ReadReq_misses::0 217330 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 217330 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::0 155538 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 155538 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::0 9456 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9456 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::0 8189 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8189 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::0 372868 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 372868 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::0 372868 # number of overall misses -system.cpu0.dcache.overall_misses::1 0 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 372868 # number of overall misses system.cpu0.dcache.overall_misses::total 372868 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency 6317758500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency 9648444500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency 9648444500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::0 7645939 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3330686000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3330686000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6317758500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6317758500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100249000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100249000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 70240000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 70240000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 9648444500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 9648444500 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 9648444500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 9648444500 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7645939 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::0 5328171 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5328171 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 136234 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 136185 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 12974110 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12974110 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028424 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.029192 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.069410 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.060131 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028739 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028739 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15325.477385 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40618.745901 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,56 +661,56 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 294891 # number of writebacks -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 45691000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks +system.cpu0.dcache.writebacks::total 294891 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 217330 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 155538 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 155538 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9456 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9456 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8184 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8184 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 372868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372868 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 372868 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 372868 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2678673500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2678673500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5851029000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5851029000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 71881000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71881000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 45691000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 45691000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8529702500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8529702500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8529702500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8529702500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 9171180500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9171180500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 40129379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 40129379500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 49300560000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 49300560000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029192 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069410 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.060095 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7601.628596 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5582.966764 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -566,7 +757,8 @@ system.cpu1.itb.accesses 26851434 # DT system.cpu1.numCycles 5339222450 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.num_insts 34444935 # Number of instructions executed +system.cpu1.committedInsts 25921760 # Number of instructions committed +system.cpu1.committedOps 34444935 # Number of ops (including micro ops) committed system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses system.cpu1.num_func_calls 1093852 # number of times a function call or return occured @@ -592,51 +784,39 @@ system.cpu1.icache.total_refs 26339543 # To system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context -system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits +system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 26339543 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::cpu1.inst 26339543 # number of demand (read+write) hits system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 26339543 # number of overall hits -system.cpu1.icache.overall_hits::1 0 # number of overall hits +system.cpu1.icache.overall_hits::cpu1.inst 26339543 # number of overall hits system.cpu1.icache.overall_hits::total 26339543 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 508733 # number of overall misses -system.cpu1.icache.overall_misses::1 0 # number of overall misses +system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses system.cpu1.icache.overall_misses::total 508733 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7436442000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7436442000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7436442000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7436442000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7436442000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7436442000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7436442000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7436442000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848276 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 26848276 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::cpu1.inst 26848276 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 26848276 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 26848276 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.018948 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.018948 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.018948 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.573462 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,34 +825,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 27998 # number of writebacks -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.018948 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks +system.cpu1.icache.writebacks::total 27998 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 508733 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 508733 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 508733 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 508733 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 508733 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 508733 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5908060000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5908060000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5908060000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5908060000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5908060000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5908060000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5250000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5250000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.018948 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 295754 # number of replacements system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use @@ -680,84 +858,69 @@ system.cpu1.dcache.total_refs 11737107 # To system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks. system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 467.166427 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.912434 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6345290 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 5152610 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5152610 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 104795 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104795 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 106403 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 11497900 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 11497900 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 11497900 # number of overall hits -system.cpu1.dcache.overall_hits::1 0 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 11497900 # number of overall hits system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 188245 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 137493 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 137493 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11557 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 9906 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9906 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 325738 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 325738 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 325738 # number of overall misses -system.cpu1.dcache.overall_misses::1 0 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 325738 # number of overall misses system.cpu1.dcache.overall_misses::total 325738 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 2729023500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 4123985000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 131721000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 82493000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 6853008500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 6853008500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 6533535 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2729023500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2729023500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4123985000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4123985000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131721000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 82493000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 82493000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6853008500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6853008500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6853008500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6853008500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 6533535 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 5290103 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290103 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 116352 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 116309 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 116309 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 11823638 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11823638 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11823638 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025991 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.099328 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.085170 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027550 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.189832 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.508004 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -766,54 +929,53 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 253551 # number of writebacks -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks +system.cpu1.dcache.writebacks::total 253551 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11557 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11557 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 9900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164153000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164153000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97050000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5875619500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875619500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5875619500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470526000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470526000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402501000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402501000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.470026 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.508004 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -821,38 +983,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -861,28 +991,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index b4466ea53..49efd7ba0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 boot_loader=/dist/m5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 @@ -90,6 +90,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu.tracer +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -104,20 +105,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -149,20 +143,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -214,20 +201,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -246,20 +226,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -285,7 +258,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -327,7 +299,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -337,7 +308,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -407,7 +377,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -419,7 +388,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -429,7 +397,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -458,7 +425,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -468,7 +434,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -478,7 +443,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -491,7 +455,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -505,7 +468,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -516,7 +478,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -535,7 +496,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -545,7 +505,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -554,7 +513,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -566,7 +524,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -576,7 +533,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -586,7 +542,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -596,7 +551,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -606,7 +560,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -620,7 +573,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -634,7 +586,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -657,7 +608,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -667,7 +617,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -677,7 +626,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -687,7 +635,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 661533caf..af233a80c 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 04:25:02 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:37:03 gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 543720998..833c19821 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 2.591442 # Nu sim_ticks 2591441692000 # Number of ticks simulated final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 852555 # Simulator instruction rate (inst/s) -host_tick_rate 29271571690 # Simulator tick rate (ticks/s) -host_mem_usage 379496 # Number of bytes of host memory used -host_seconds 88.53 # Real time elapsed on the host -sim_insts 75477515 # Number of instructions simulated +host_inst_rate 874833 # Simulator instruction rate (inst/s) +host_op_rate 1117723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38375829651 # Simulator tick rate (ticks/s) +host_mem_usage 376612 # Number of bytes of host memory used +host_seconds 67.53 # Real time elapsed on the host +sim_insts 59075683 # Number of instructions simulated +sim_ops 75477515 # Number of ops (including micro ops) simulated system.nvmem.bytes_read 20 # Number of bytes read from this memory system.nvmem.bytes_inst_read 20 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -34,84 +36,125 @@ system.l2c.total_refs 1535240 # To system.l2c.sampled_refs 146709 # Sample count of references to valid blocks. system.l2c.avg_refs 10.464525 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 10331.534348 # Average occupied blocks per context -system.l2c.occ_blocks::1 14596.842556 # Average occupied blocks per context -system.l2c.occ_percent::0 0.157647 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.222730 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1198360 # number of ReadReq hits -system.l2c.ReadReq_hits::1 12495 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 14588.908220 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 6.963925 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.970411 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 5158.445831 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 5173.088517 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.222609 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000106 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.078712 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.078935 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.380377 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8825 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3670 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 837469 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 360891 # number of ReadReq hits system.l2c.ReadReq_hits::total 1210855 # number of ReadReq hits -system.l2c.Writeback_hits::0 610049 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 610049 # number of Writeback hits system.l2c.Writeback_hits::total 610049 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 26 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 106473 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 106473 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 106473 # number of ReadExReq hits -system.l2c.demand_hits::0 1304833 # number of demand (read+write) hits -system.l2c.demand_hits::1 12495 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 8825 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3670 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 837469 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 467364 # number of demand (read+write) hits system.l2c.demand_hits::total 1317328 # number of demand (read+write) hits -system.l2c.overall_hits::0 1304833 # number of overall hits -system.l2c.overall_hits::1 12495 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 8825 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3670 # number of overall hits +system.l2c.overall_hits::cpu.inst 837469 # number of overall hits +system.l2c.overall_hits::cpu.data 467364 # number of overall hits system.l2c.overall_hits::total 1317328 # number of overall hits -system.l2c.ReadReq_misses::0 31685 # number of ReadReq misses -system.l2c.ReadReq_misses::1 37 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 24 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 14429 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 17256 # number of ReadReq misses system.l2c.ReadReq_misses::total 31722 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 2875 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2875 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 140928 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 140928 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 140928 # number of ReadExReq misses -system.l2c.demand_misses::0 172613 # number of demand (read+write) misses -system.l2c.demand_misses::1 37 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 24 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 14429 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 158184 # number of demand (read+write) misses system.l2c.demand_misses::total 172650 # number of demand (read+write) misses -system.l2c.overall_misses::0 172613 # number of overall misses -system.l2c.overall_misses::1 37 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 24 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu.inst 14429 # number of overall misses +system.l2c.overall_misses::cpu.data 158184 # number of overall misses system.l2c.overall_misses::total 172650 # number of overall misses -system.l2c.ReadReq_miss_latency 1654516000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1040000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7338006500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 8992522500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 8992522500 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1230045 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 12532 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 1250000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 676000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 753120500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 899469500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1654516000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 1040000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1040000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7338006500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7338006500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 1250000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 676000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 753120500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8237476000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8992522500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 1250000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 676000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 753120500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8237476000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8992522500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 8849 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3683 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 851898 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 378147 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1242577 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 610049 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 610049 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 610049 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 2901 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 247401 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 247401 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 247401 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1477446 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 12532 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 8849 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3683 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 851898 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 625548 # number of demand (read+write) accesses system.l2c.demand_accesses::total 1489978 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1477446 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 12532 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 8849 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3683 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 851898 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 625548 # number of overall (read+write) accesses system.l2c.overall_accesses::total 1489978 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025759 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002952 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.028712 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.991038 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.569634 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.116832 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002952 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.119784 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.116832 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002952 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.119784 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52217.642418 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 44716648.648649 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 44768866.291066 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 361.739130 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52069.187812 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52096.438275 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 243041148.648649 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 243093245.086924 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52096.438275 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 243041148.648649 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 243093245.086924 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002712 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003530 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.016937 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.045633 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.569634 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.002712 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.003530 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.016937 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.252873 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.002712 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.003530 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.016937 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.252873 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52083.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52194.919953 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52125.028975 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 361.739130 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52069.187812 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52083.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52194.919953 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52075.279421 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -120,48 +163,87 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 103410 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 31722 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 2875 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140928 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 172650 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 172650 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1273844000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 115156000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5646870000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 6920714000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 6920714000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131817513000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 31206766500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 163024279500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.025789 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.531280 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 2.557069 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.991038 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.569634 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.116857 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 13.776732 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 13.893589 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.116857 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 13.776732 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 13.893589 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40085.224443 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 103410 # number of writebacks +system.l2c.writebacks::total 103410 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 24 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 14429 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 17256 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 31722 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 140928 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140928 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 24 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 14429 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 158184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 172650 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 24 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 14429 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 158184 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 172650 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 962000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 520000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 579966000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 692396000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1273844000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 115156000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 115156000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5646870000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5646870000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 962000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 579966000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6339266000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6920714000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 962000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 520000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 579966000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6339266000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6920714000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 264840000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131552673000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131817513000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31206766500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31206766500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 264840000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162759439500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163024279500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.045633 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569634 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.252873 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.002712 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.016937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.252873 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40194.469471 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40124.942049 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.260870 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.184264 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40194.469471 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.266778 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40194.469471 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.266778 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -214,7 +296,8 @@ system.cpu.itb.accesses 60362193 # DT system.cpu.numCycles 5182883384 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 75477515 # Number of instructions executed +system.cpu.committedInsts 59075683 # Number of instructions committed +system.cpu.committedOps 75477515 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 68255270 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses system.cpu.num_func_calls 1975579 # number of times a function call or return occured @@ -240,51 +323,39 @@ system.cpu.icache.total_refs 59504239 # To system.cpu.icache.sampled_refs 853483 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 69.719302 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18512998000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.943281 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997936 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 59504239 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 510.943281 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997936 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997936 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 59504239 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 59504239 # number of ReadReq hits -system.cpu.icache.demand_hits::0 59504239 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 59504239 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 59504239 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 59504239 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 59504239 # number of overall hits system.cpu.icache.overall_hits::total 59504239 # number of overall hits -system.cpu.icache.ReadReq_misses::0 853483 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 853483 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 853483 # number of ReadReq misses -system.cpu.icache.demand_misses::0 853483 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 853483 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 853483 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 853483 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 853483 # number of overall misses system.cpu.icache.overall_misses::total 853483 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12547128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12547128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12547128000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 60357722 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12547128000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12547128000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12547128000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12547128000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12547128000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12547128000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 60357722 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 60357722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 60357722 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 60357722 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 60357722 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 60357722 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 60357722 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 60357722 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.014140 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.014140 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.014140 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14701.087192 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14701.087192 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14701.087192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014140 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014140 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014140 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14701.087192 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14701.087192 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -293,34 +364,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 45661 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 853483 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 853483 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 853483 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9984295500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9984295500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9984295500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency 350913000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency 350913000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.014140 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.014140 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.014140 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.294518 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 45661 # number of writebacks +system.cpu.icache.writebacks::total 45661 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 853483 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 853483 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 853483 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 853483 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 853483 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 853483 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9984295500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9984295500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9984295500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9984295500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9984295500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9984295500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 350913000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 350913000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 350913000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 350913000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014140 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.294518 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.294518 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 626903 # number of replacements system.cpu.dcache.tagsinuse 511.875592 # Cycle average of tags in use @@ -328,77 +397,63 @@ system.cpu.dcache.total_refs 23615096 # To system.cpu.dcache.sampled_refs 627415 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 37.638718 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 660309000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.875592 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 13170367 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.875592 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13170367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13170367 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 9958094 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9958094 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 9958094 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 236142 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236142 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 236142 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 247592 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247592 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247592 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 23128461 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 23128461 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 23128461 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 23128461 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 23128461 # number of overall hits system.cpu.dcache.overall_hits::total 23128461 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 368563 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 368563 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 368563 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 250302 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250302 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 250302 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 11451 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11451 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 11451 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 618865 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 618865 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 618865 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 618865 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 618865 # number of overall misses system.cpu.dcache.overall_misses::total 618865 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5846897000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 9551170500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 186076500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 15398067500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 15398067500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13538930 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5846897000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5846897000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9551170500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9551170500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 186076500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 186076500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15398067500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15398067500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15398067500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15398067500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13538930 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10208396 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247593 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247592 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 23747326 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23747326 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024519 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046249 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.026060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15864.036813 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,48 +462,47 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 564388 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 564388 # number of writebacks +system.cpu.dcache.writebacks::total 564388 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250302 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250302 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11451 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11451 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 618865 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 618865 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 618865 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 618865 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741074500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741074500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800219500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800219500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151723500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151723500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13541294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13541294000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13541294000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13541294000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146946835000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146946835000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367455500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367455500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187314290500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187314290500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024519 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046249 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12863.674596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35158.406645 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13249.803511 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -456,38 +510,6 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.avg_refs no_value # Average number of references to valid blocks. system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 0 # number of demand (read+write) misses -system.iocache.demand_misses::total 0 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 0 # number of overall misses -system.iocache.overall_misses::total 0 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,28 +518,12 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 0 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1341941439938 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index 91a089b4b..1885ca8f8 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -1,15 +1,15 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus +children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer -boot_cpu_frequency=500 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 e820_table=system.e820_table init_param=0 @@ -50,6 +50,17 @@ oem_id= oem_revision=0 oem_table_id= +[system.apicbridge] +type=Bridge +delay=50000 +nack_delay=4000 +ranges=11529215046068469760:11529215046068473855 +req_size=16 +resp_size=16 +write_ack=false +master=system.membus.port[2] +slave=system.iobus.port[1] + [system.bridge] type=Bridge delay=50000 @@ -89,6 +100,7 @@ simulate_inst_stalls=false system=system tracer=system.cpu.tracer width=1 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -103,20 +115,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -146,20 +151,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -178,20 +176,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -204,7 +195,6 @@ type=X86LocalApic int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 -platform=system.pc system=system int_port=system.membus.port[7] pio=system.membus.port[6] @@ -231,20 +221,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -618,17 +601,6 @@ subtractive_decode=true type=IntrControl sys=system -[system.iobridge] -type=Bridge -delay=50000 -nack_delay=4000 -ranges=11529215046068469760:11529215046068473855 -req_size=16 -resp_size=16 -write_ack=false -master=system.membus.port[2] -slave=system.iobus.port[1] - [system.iobus] type=Bus block_size=64 @@ -638,7 +610,7 @@ header_cycles=1 use_default_range=true width=64 default=system.pc.pciconfig.pio -port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side [system.iocache] type=BaseCache @@ -651,20 +623,13 @@ is_top_level=true latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -683,20 +648,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -714,7 +672,7 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.membus.badaddr_responder] type=IsaFake @@ -722,7 +680,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -745,7 +702,6 @@ fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -786,7 +742,6 @@ fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -803,7 +758,6 @@ fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -820,7 +774,6 @@ fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -837,7 +790,6 @@ fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -854,7 +806,6 @@ fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -894,7 +845,6 @@ children=int_pin int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 -platform=system.pc system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[2] @@ -906,7 +856,6 @@ type=X86IntSourcePin type=I8237 pio_addr=9223372036854775808 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[3] @@ -1091,7 +1040,6 @@ external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 pio_latency=1000 -platform=system.pc system=system int_port=system.iobus.port[13] pio=system.iobus.port[12] @@ -1105,7 +1053,6 @@ keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[7] @@ -1122,7 +1069,6 @@ mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 -platform=system.pc slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[8] @@ -1137,7 +1083,6 @@ mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 -platform=system.pc slave=Null system=system pio=system.iobus.port[9] @@ -1151,7 +1096,6 @@ children=int_pin int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[10] @@ -1163,7 +1107,6 @@ type=PcSpeaker i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[11] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index 23cf47db2..e4d0a5032 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:12:17 -gem5 started Jan 23 2012 04:24:46 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:48 gem5 executing on zizzer -command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 324bf8929..21f7dfc5d 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2850135 # Simulator instruction rate (inst/s) -host_tick_rate 35611898535 # Simulator tick rate (ticks/s) -host_mem_usage 353172 # Number of bytes of host memory used -host_seconds 143.55 # Real time elapsed on the host -sim_insts 409133277 # Number of instructions simulated +host_inst_rate 1772716 # Simulator instruction rate (inst/s) +host_op_rate 3629762 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45353186641 # Simulator tick rate (ticks/s) +host_mem_usage 350348 # Number of bytes of host memory used +host_seconds 112.72 # Real time elapsed on the host +sim_insts 199813913 # Number of instructions simulated +sim_ops 409133277 # Number of ops (including micro ops) simulated system.physmem.bytes_read 15568704 # Number of bytes read from this memory system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory system.physmem.bytes_written 12232896 # Number of bytes written to this memory @@ -25,72 +27,92 @@ system.l2c.total_refs 3332458 # To system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context -system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context -system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits -system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits -system.l2c.Writeback_hits::0 1529403 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits system.l2c.Writeback_hits::total 1529403 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits -system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits -system.l2c.demand_hits::1 9538 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits -system.l2c.overall_hits::0 2211865 # number of overall hits -system.l2c.overall_hits::1 9538 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits +system.l2c.overall_hits::cpu.inst 776101 # number of overall hits +system.l2c.overall_hits::cpu.data 1435764 # number of overall hits system.l2c.overall_hits::total 2221403 # number of overall hits -system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses -system.l2c.ReadReq_misses::1 27 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses -system.l2c.demand_misses::0 200611 # number of demand (read+write) misses -system.l2c.demand_misses::1 27 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses system.l2c.demand_misses::total 200638 # number of demand (read+write) misses -system.l2c.overall_misses::0 200611 # number of overall misses -system.l2c.overall_misses::1 27 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses +system.l2c.overall_misses::cpu.inst 15200 # number of overall misses +system.l2c.overall_misses::cpu.data 185411 # number of overall misses system.l2c.overall_misses::total 200638 # number of overall misses -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -99,26 +121,8 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 144472 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 144472 # number of writebacks +system.l2c.writebacks::total 144472 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47570 # number of replacements system.iocache.tagsinuse 0.042409 # Cycle average of tags in use @@ -126,50 +130,29 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context -system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 905 # number of ReadReq misses +system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses system.iocache.ReadReq_misses::total 905 # number of ReadReq misses -system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47625 # number of demand (read+write) misses +system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses system.iocache.demand_misses::total 47625 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47625 # number of overall misses +system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses system.iocache.overall_misses::total 47625 # number of overall misses -system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 0 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 905 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47625 # number of demand (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47625 # number of overall (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.demand_avg_miss_latency::1 0 # average overall miss latency -system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.iocache.overall_avg_miss_latency::1 0 # average overall miss latency -system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -178,26 +161,8 @@ system.iocache.avg_blocked_cycles::no_mshrs no_value # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46667 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 0 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 46667 # number of writebacks +system.iocache.writebacks::total 46667 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -214,7 +179,8 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10224086531 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 409133277 # Number of instructions executed +system.cpu.committedInsts 199813913 # Number of instructions committed +system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -240,47 +206,30 @@ system.cpu.icache.total_refs 243365777 # To system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.627676 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 243365777 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits -system.cpu.icache.demand_hits::0 243365777 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 243365777 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits system.cpu.icache.overall_hits::total 243365777 # number of overall hits -system.cpu.icache.ReadReq_misses::0 791314 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses -system.cpu.icache.demand_misses::0 791314 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 791314 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses system.cpu.icache.overall_misses::total 791314 # number of overall misses -system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 244157091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 244157091 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 244157091 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.003241 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.003241 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.003241 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -289,26 +238,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 809 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 809 # number of writebacks +system.cpu.icache.writebacks::total 809 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3435 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use @@ -316,51 +247,34 @@ system.cpu.itb_walker_cache.total_refs 7940 # To system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 3.021701 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.188856 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 7947 # number of ReadReq hits +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits -system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits +system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 7949 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 7949 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 4278 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 4278 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 4278 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses -system.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 12225 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 12227 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 12227 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.349939 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.349881 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.349881 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,26 +283,8 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 518 # number of writebacks -system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 7755 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use @@ -396,47 +292,30 @@ system.cpu.dtb_walker_cache.total_refs 12854 # To system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses -system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -445,26 +324,8 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks -system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1621277 # number of replacements system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use @@ -472,54 +333,37 @@ system.cpu.dcache.total_refs 20142220 # To system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 20139962 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits system.cpu.dcache.overall_hits::total 20139962 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 1624057 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses system.cpu.dcache.overall_misses::total 1624057 # number of overall misses -system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -528,26 +372,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1525559 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses -system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks +system.cpu.dcache.writebacks::total 1525559 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index e3a339662..baa9c805b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -1,15 +1,15 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 [system] type=LinuxX86System -children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus +children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus acpi_description_table_pointer=system.acpi_description_table_pointer -boot_cpu_frequency=500 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 e820_table=system.e820_table init_param=0 @@ -50,6 +50,17 @@ oem_id= oem_revision=0 oem_table_id= +[system.apicbridge] +type=Bridge +delay=50000 +nack_delay=4000 +ranges=11529215046068469760:11529215046068473855 +req_size=16 +resp_size=16 +write_ack=false +master=system.membus.port[2] +slave=system.iobus.port[1] + [system.bridge] type=Bridge delay=50000 @@ -86,6 +97,7 @@ profile=0 progress_interval=0 system=system tracer=system.cpu.tracer +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -100,20 +112,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -143,20 +148,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -175,20 +173,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=32768 subblock_size=0 +system=system tgts_per_mshr=8 trace_addr=0 two_queue=false @@ -201,7 +192,6 @@ type=X86LocalApic int_latency=1000 pio_addr=2305843009213693952 pio_latency=1000 -platform=system.pc system=system int_port=system.membus.port[7] pio=system.membus.port[6] @@ -228,20 +218,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -615,17 +598,6 @@ subtractive_decode=true type=IntrControl sys=system -[system.iobridge] -type=Bridge -delay=50000 -nack_delay=4000 -ranges=11529215046068469760:11529215046068473855 -req_size=16 -resp_size=16 -write_ack=false -master=system.membus.port[2] -slave=system.iobus.port[1] - [system.iobus] type=Bus block_size=64 @@ -635,7 +607,7 @@ header_cycles=1 use_default_range=true width=64 default=system.pc.pciconfig.pio -port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side +port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side [system.iocache] type=BaseCache @@ -648,20 +620,13 @@ is_top_level=false latency=50000 max_miss_count=0 mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=1024 subblock_size=0 +system=system tgts_per_mshr=12 trace_addr=0 two_queue=false @@ -680,20 +645,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=4194304 subblock_size=0 +system=system tgts_per_mshr=16 trace_addr=0 two_queue=false @@ -711,7 +669,7 @@ header_cycles=1 use_default_range=false width=64 default=system.membus.badaddr_responder.pio -port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port +port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.membus.badaddr_responder] type=IsaFake @@ -719,7 +677,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -742,7 +699,6 @@ fake_mem=false pio_addr=9223372036854779128 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -783,7 +739,6 @@ fake_mem=false pio_addr=9223372036854776568 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -800,7 +755,6 @@ fake_mem=false pio_addr=9223372036854776808 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -817,7 +771,6 @@ fake_mem=false pio_addr=9223372036854776552 pio_latency=1000 pio_size=8 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -834,7 +787,6 @@ fake_mem=false pio_addr=9223372036854776818 pio_latency=1000 pio_size=2 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -851,7 +803,6 @@ fake_mem=false pio_addr=9223372036854775936 pio_latency=1000 pio_size=1 -platform=system.pc ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -891,7 +842,6 @@ children=int_pin int_pin=system.pc.south_bridge.cmos.int_pin pio_addr=9223372036854775920 pio_latency=1000 -platform=system.pc system=system time=Sun Jan 1 00:00:00 2012 pio=system.iobus.port[2] @@ -903,7 +853,6 @@ type=X86IntSourcePin type=I8237 pio_addr=9223372036854775808 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[3] @@ -1088,7 +1037,6 @@ external_int_pic=system.pc.south_bridge.pic1 int_latency=1000 pio_addr=4273995776 pio_latency=1000 -platform=system.pc system=system int_port=system.iobus.port[13] pio=system.iobus.port[12] @@ -1102,7 +1050,6 @@ keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin pio_addr=0 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[7] @@ -1119,7 +1066,6 @@ mode=I8259Master output=system.pc.south_bridge.pic1.output pio_addr=9223372036854775840 pio_latency=1000 -platform=system.pc slave=system.pc.south_bridge.pic2 system=system pio=system.iobus.port[8] @@ -1134,7 +1080,6 @@ mode=I8259Slave output=system.pc.south_bridge.pic2.output pio_addr=9223372036854775968 pio_latency=1000 -platform=system.pc slave=Null system=system pio=system.iobus.port[9] @@ -1148,7 +1093,6 @@ children=int_pin int_pin=system.pc.south_bridge.pit.int_pin pio_addr=9223372036854775872 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[10] @@ -1160,7 +1104,6 @@ type=PcSpeaker i8254=system.pc.south_bridge.pit pio_addr=9223372036854775905 pio_latency=1000 -platform=system.pc system=system pio=system.iobus.port[11] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 5dde537a2..9ff593dd3 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,13 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:12:17 -gem5 started Jan 23 2012 04:24:49 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:06:52 gem5 executing on zizzer -command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second - 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5195470393000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index c4a248e5e..6ded30fe7 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 5.195470 # Nu sim_ticks 5195470393000 # Number of ticks simulated final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1681123 # Simulator instruction rate (inst/s) -host_tick_rate 32940960656 # Simulator tick rate (ticks/s) -host_mem_usage 349824 # Number of bytes of host memory used -host_seconds 157.72 # Real time elapsed on the host -sim_insts 265147881 # Number of instructions simulated +host_inst_rate 1225094 # Simulator instruction rate (inst/s) +host_op_rate 2351489 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46076516791 # Simulator tick rate (ticks/s) +host_mem_usage 346880 # Number of bytes of host memory used +host_seconds 112.76 # Real time elapsed on the host +sim_insts 138138472 # Number of instructions simulated +sim_ops 265147881 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13764096 # Number of bytes read from this memory system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory system.physmem.bytes_written 10427072 # Number of bytes written to this memory @@ -25,84 +27,125 @@ system.l2c.total_refs 3363370 # To system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context -system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context -system.l2c.occ_percent::0 0.120711 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.358261 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 2047882 # number of ReadReq hits -system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits +system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits -system.l2c.Writeback_hits::0 1534567 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits system.l2c.Writeback_hits::total 1534567 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 192958 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits -system.l2c.demand_hits::0 2240840 # number of demand (read+write) hits -system.l2c.demand_hits::1 9561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits -system.l2c.overall_hits::0 2240840 # number of overall hits -system.l2c.overall_hits::1 9561 # number of overall hits +system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits +system.l2c.overall_hits::cpu.inst 773419 # number of overall hits +system.l2c.overall_hits::cpu.data 1467421 # number of overall hits system.l2c.overall_hits::total 2250401 # number of overall hits -system.l2c.ReadReq_misses::0 50807 # number of ReadReq misses -system.l2c.ReadReq_misses::1 23 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 1369 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 120168 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses -system.l2c.demand_misses::0 170975 # number of demand (read+write) misses -system.l2c.demand_misses::1 23 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses system.l2c.demand_misses::total 170998 # number of demand (read+write) misses -system.l2c.overall_misses::0 170975 # number of overall misses -system.l2c.overall_misses::1 23 # number of overall misses +system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu.inst 15226 # number of overall misses +system.l2c.overall_misses::cpu.data 155749 # number of overall misses system.l2c.overall_misses::total 170998 # number of overall misses -system.l2c.ReadReq_miss_latency 2656122500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 33778000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6249324500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 8905447000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2098689 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 9584 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 676000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 520000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 791868000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 1863058500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2656122500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 33778000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 33778000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6249324500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6249324500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 676000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 791868000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 8112383000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8905447000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 676000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 520000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 791868000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 8112383000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8905447000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 6541 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3043 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 788645 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1310044 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1534567 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 1689 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 1689 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 313126 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 313126 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2411815 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 9584 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.dtb.walker 6541 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3043 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 788645 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2411815 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 9584 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 6541 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3043 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 788645 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.002400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026609 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.810539 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.383769 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.070891 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.070891 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52278.672230 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 115483586.956522 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 115535865.628752 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52004.897310 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52086.252376 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 387193347.826087 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 387245434.078463 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52086.252376 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 387193347.826087 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 387245434.078463 # average overall miss latency +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -111,48 +154,83 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 116255 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 50830 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 120168 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 2046144000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4807305000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 6853449000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1218050000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.024220 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 5.303631 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 5.327851 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.383769 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.l2c.writebacks::writebacks 116255 # number of writebacks +system.l2c.writebacks::total 116255 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 50830 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 1369 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1369 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 120168 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 120168 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 15226 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 155749 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 170998 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.inst 15226 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 155749 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 170998 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 520000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 609142000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 1436082000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2046144000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55109000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 55109000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4807305000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4807305000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 520000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 609142000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6243387000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6853449000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 520000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 609142000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6243387000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6853449000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56051785000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 56051785000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1218050000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1218050000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269835000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 57269835000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 47510 # number of replacements system.iocache.tagsinuse 0.120586 # Cycle average of tags in use @@ -160,58 +238,41 @@ system.iocache.total_refs 0 # To system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 0.120586 # Average occupied blocks per context -system.iocache.occ_percent::1 0.007537 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 844 # number of ReadReq misses +system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses system.iocache.ReadReq_misses::total 844 # number of ReadReq misses -system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses +system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 47564 # number of demand (read+write) misses +system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses system.iocache.demand_misses::total 47564 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 47564 # number of overall misses +system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses system.iocache.overall_misses::total 47564 # number of overall misses -system.iocache.ReadReq_miss_latency 106575932 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 6391379160 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 6497955092 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 6497955092 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 844 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 106575932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 106575932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391379160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6391379160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 6497955092 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 6497955092 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 6497955092 # number of overall miss cycles +system.iocache.overall_miss_latency::total 6497955092 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 47564 # number of demand (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 47564 # number of overall (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 126274.800948 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 136801.779966 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 136614.983853 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 136614.983853 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked @@ -220,38 +281,32 @@ system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 46668 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 844 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 47564 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 47564 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 62666978 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3961676998 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 4024343976 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 4024343976 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62666978 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 62666978 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3961676998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 3961676998 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4024343976 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -268,7 +323,8 @@ system.pc.south_bridge.ide.disks1.dma_write_txs 1 system.cpu.numCycles 10390940786 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 265147881 # Number of instructions executed +system.cpu.committedInsts 138138472 # Number of instructions committed +system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -294,51 +350,39 @@ system.cpu.icache.total_refs 158433932 # To system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 510.361283 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.996799 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 158433932 # number of ReadReq hits +system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits -system.cpu.icache.demand_hits::0 158433932 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 158433932 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits +system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits system.cpu.icache.overall_hits::total 158433932 # number of overall hits -system.cpu.icache.ReadReq_misses::0 788658 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses -system.cpu.icache.demand_misses::0 788658 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 788658 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses +system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses system.cpu.icache.overall_misses::total 788658 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 11681762500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 11681762500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 11681762500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 159222590 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 159222590 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 159222590 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.004953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.004953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.004953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14812.203135 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14812.203135 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -347,32 +391,26 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 805 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 788658 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 788658 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 788658 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9314744000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9314744000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9314744000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.004953 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.004953 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.004953 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.writebacks::writebacks 805 # number of writebacks +system.cpu.icache.writebacks::total 805 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3754 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use @@ -380,55 +418,43 @@ system.cpu.itb_walker_cache.total_refs 7549 # To system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::1 3.070606 # Average occupied blocks per context -system.cpu.itb_walker_cache.occ_percent::1 0.191913 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::1 7619 # number of ReadReq hits +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits -system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits +system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::1 7621 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::1 7621 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::1 4602 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::1 4602 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::1 4602 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency 50817000 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency 50817000 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency 50817000 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::1 12221 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) +system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::1 12223 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::1 12223 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.376565 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::1 0.376503 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::1 0.376503 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -437,32 +463,26 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks 826 # number of writebacks -system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.itb_walker_cache.ReadReq_mshr_misses 4602 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses 4602 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses 4602 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 37011000 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency 37011000 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency 37011000 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.376565 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.376503 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.376503 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 8042.372881 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dtb_walker_cache.replacements 7704 # number of replacements system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use @@ -470,51 +490,39 @@ system.cpu.dtb_walker_cache.total_refs 13051 # To system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::1 5.052403 # Average occupied blocks per context -system.cpu.dtb_walker_cache.occ_percent::1 0.315775 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::1 13051 # number of ReadReq hits +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::1 13051 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::1 13051 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::1 8896 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::1 8896 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::1 8896 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency 103895500 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency 103895500 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency 103895500 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::1 21947 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses) system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::1 21947 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::1 21947 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.405340 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::1 0.405340 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::1 0.405340 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -523,32 +531,26 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks 2985 # number of writebacks -system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dtb_walker_cache.ReadReq_mshr_misses 8896 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses 8896 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses 8896 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 77207000 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency 77207000 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency 77207000 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.405340 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.405340 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.405340 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 8678.844424 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 1623424 # number of replacements system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use @@ -556,62 +558,49 @@ system.cpu.dcache.total_refs 20011404 # To system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.997312 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 11977182 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 8032009 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits -system.cpu.dcache.demand_hits::0 20009191 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 20009191 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits +system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits system.cpu.dcache.overall_hits::total 20009191 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1310824 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 315344 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315344 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses -system.cpu.dcache.demand_misses::0 1626168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::cpu.data 1626168 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 1626168 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses +system.cpu.dcache.overall_misses::cpu.data 1626168 # number of overall misses system.cpu.dcache.overall_misses::total 1626168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 19851809000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 9514837000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 29366646000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 29366646000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19851809000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19851809000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9514837000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9514837000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29366646000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29366646000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29366646000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29366646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13288006 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 8347353 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8347353 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 21635359 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 21635359 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 21635359 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.098647 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.037778 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::0 0.075163 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.075163 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 18058.802043 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 18058.802043 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,42 +609,41 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 1529951 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1310824 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 315344 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1626168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1626168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 15919294500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8568794500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 24488089000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 24488089000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 77305053000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.075163 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.075163 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks +system.cpu.dcache.writebacks::total 1529951 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index 4bff39dc1..7a0c1d8ae 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -64,6 +64,7 @@ simulate_inst_stalls=false system=drivesys tracer=drivesys.cpu.tracer width=1 +workload= dcache_port=drivesys.membus.port[4] icache_port=drivesys.membus.port[3] @@ -165,7 +166,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -225,7 +225,6 @@ pio=drivesys.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=drivesys.tsunami system=drivesys tsunami=drivesys.tsunami pio=drivesys.iobus.port[1] @@ -308,7 +307,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -325,7 +323,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -342,7 +339,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -359,7 +355,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -376,7 +371,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -393,7 +387,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -410,7 +403,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -427,7 +419,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -444,7 +435,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -461,7 +451,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -478,7 +467,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -495,7 +483,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -512,7 +499,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -529,7 +515,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -546,7 +531,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -563,7 +547,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -580,7 +563,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -597,7 +579,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -614,7 +595,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=drivesys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -630,7 +610,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=drivesys.tsunami system=drivesys pio=drivesys.iobus.port[22] @@ -695,7 +674,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=drivesys.tsunami system=drivesys time=Thu Jan 1 00:00:00 2009 tsunami=drivesys.tsunami @@ -706,7 +684,6 @@ pio=drivesys.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=drivesys.tsunami system=drivesys tsunami=drivesys.tsunami pio=drivesys.iobus.port[2] @@ -746,6 +723,7 @@ int1=drivesys.tsunami.ethernet.interface [root] type=Root children=drivesys etherdump etherlink testsys +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -816,6 +794,7 @@ simulate_inst_stalls=false system=testsys tracer=testsys.cpu.tracer width=1 +workload= dcache_port=testsys.membus.port[4] icache_port=testsys.membus.port[3] @@ -917,7 +896,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -977,7 +955,6 @@ pio=testsys.iobus.port[25] type=TsunamiCChip pio_addr=8803072344064 pio_latency=1000 -platform=testsys.tsunami system=testsys tsunami=testsys.tsunami pio=testsys.iobus.port[1] @@ -1060,7 +1037,6 @@ fake_mem=false pio_addr=8796093677568 pio_latency=1000 pio_size=393216 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1077,7 +1053,6 @@ fake_mem=false pio_addr=8804615848432 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1094,7 +1069,6 @@ fake_mem=false pio_addr=8804615848304 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1111,7 +1085,6 @@ fake_mem=false pio_addr=8804615848569 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1128,7 +1101,6 @@ fake_mem=false pio_addr=8804615848451 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1145,7 +1117,6 @@ fake_mem=false pio_addr=8804615848515 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1162,7 +1133,6 @@ fake_mem=false pio_addr=8804615848579 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1179,7 +1149,6 @@ fake_mem=false pio_addr=8804615848643 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1196,7 +1165,6 @@ fake_mem=false pio_addr=8804615848707 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1213,7 +1181,6 @@ fake_mem=false pio_addr=8804615848771 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1230,7 +1197,6 @@ fake_mem=false pio_addr=8804615848835 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1247,7 +1213,6 @@ fake_mem=false pio_addr=8804615848899 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1264,7 +1229,6 @@ fake_mem=false pio_addr=8804615850617 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1281,7 +1245,6 @@ fake_mem=false pio_addr=8804615848891 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1298,7 +1261,6 @@ fake_mem=false pio_addr=8804615848816 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1315,7 +1277,6 @@ fake_mem=false pio_addr=8804615848696 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1332,7 +1293,6 @@ fake_mem=false pio_addr=8804615848936 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1349,7 +1309,6 @@ fake_mem=false pio_addr=8804615848680 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1366,7 +1325,6 @@ fake_mem=false pio_addr=8804615848944 pio_latency=1000 pio_size=8 -platform=testsys.tsunami ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1382,7 +1340,6 @@ type=BadDevice devicename=FrameBuffer pio_addr=8804615848912 pio_latency=1000 -platform=testsys.tsunami system=testsys pio=testsys.iobus.port[22] @@ -1447,7 +1404,6 @@ type=TsunamiIO frequency=976562500 pio_addr=8804615847936 pio_latency=1000 -platform=testsys.tsunami system=testsys time=Thu Jan 1 00:00:00 2009 tsunami=testsys.tsunami @@ -1458,7 +1414,6 @@ pio=testsys.iobus.port[23] type=TsunamiPChip pio_addr=8802535473152 pio_latency=1000 -platform=testsys.tsunami system=testsys tsunami=testsys.tsunami pio=testsys.iobus.port[2] diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index d1174531e..ca565fefc 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -1,13 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:53:29 -gem5 started Jan 23 2012 04:23:10 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:10:02 gem5 executing on zizzer -command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second - 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 - 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: kernel located at: /dist/m5/system/binaries/vmlinux info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index c3a385a95..4f6f5ddfe 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.200001 # Nu sim_ticks 200000789468 # Number of ticks simulated final_tick 4300236018046 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201516796 # Simulator instruction rate (inst/s) -host_tick_rate 147427543497 # Simulator tick rate (ticks/s) -host_mem_usage 479620 # Number of bytes of host memory used -host_seconds 1.36 # Real time elapsed on the host +host_inst_rate 238054601 # Simulator instruction rate (inst/s) +host_op_rate 238047910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 174152914765 # Simulator tick rate (ticks/s) +host_mem_usage 476544 # Number of bytes of host memory used +host_seconds 1.15 # Real time elapsed on the host sim_insts 273374833 # Number of instructions simulated +sim_ops 273374833 # Number of ops (including micro ops) simulated testsys.physmem.bytes_read 19104208 # Number of bytes read from this memory testsys.physmem.bytes_inst_read 14257548 # Number of instructions bytes read from this memory testsys.physmem.bytes_written 3887982 # Number of bytes written to this memory @@ -66,7 +68,8 @@ testsys.cpu.itb.data_accesses 0 # DT testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.num_insts 3560411 # Number of instructions executed +testsys.cpu.committedInsts 3560411 # Number of instructions committed +testsys.cpu.committedOps 3560411 # Number of ops (including micro ops) committed testsys.cpu.num_int_alu_accesses 3348322 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses testsys.cpu.num_func_calls 107994 # number of times a function call or return occured @@ -258,7 +261,8 @@ drivesys.cpu.itb.data_accesses 0 # DT drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.num_insts 1958129 # Number of instructions executed +drivesys.cpu.committedInsts 1958129 # Number of instructions committed +drivesys.cpu.committedOps 1958129 # Number of ops (including micro ops) committed drivesys.cpu.num_int_alu_accesses 1889973 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 1278 # Number of float alu accesses drivesys.cpu.num_func_calls 121650 # number of times a function call or return occured @@ -391,11 +395,13 @@ sim_seconds 0.000001 # Nu sim_ticks 785978 # Number of ticks simulated final_tick 4300236804024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 864513825905 # Simulator instruction rate (inst/s) -host_tick_rate 2363296319 # Simulator tick rate (ticks/s) -host_mem_usage 479620 # Number of bytes of host memory used +host_inst_rate 826237832724 # Simulator instruction rate (inst/s) +host_op_rate 785322914063 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2155916043 # Simulator tick rate (ticks/s) +host_mem_usage 476544 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host sim_insts 273374833 # Number of instructions simulated +sim_ops 273374833 # Number of ops (including micro ops) simulated testsys.physmem.bytes_read 0 # Number of bytes read from this memory testsys.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory testsys.physmem.bytes_written 0 # Number of bytes written to this memory @@ -449,7 +455,8 @@ testsys.cpu.itb.data_accesses 0 # DT testsys.cpu.numCycles 0 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.num_insts 0 # Number of instructions executed +testsys.cpu.committedInsts 0 # Number of instructions committed +testsys.cpu.committedOps 0 # Number of ops (including micro ops) committed testsys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses testsys.cpu.num_func_calls 0 # number of times a function call or return occured @@ -568,7 +575,8 @@ drivesys.cpu.itb.data_accesses 0 # DT drivesys.cpu.numCycles 0 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.num_insts 0 # Number of instructions executed +drivesys.cpu.committedInsts 0 # Number of instructions committed +drivesys.cpu.committedOps 0 # Number of ops (including micro ops) committed drivesys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses drivesys.cpu.num_func_calls 0 # number of times a function call or return occured |