summaryrefslogtreecommitdiff
path: root/tests/quick/fs
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2013-03-26 14:47:03 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2013-03-26 14:47:03 -0400
commita84d026538c592d06cc6db7fff4967f4e78447ac (patch)
treebb4552a895923a36efcf0669500c18264e849462 /tests/quick/fs
parent87089175ccdbec433668765b32b608fe266b7ebf (diff)
downloadgem5-a84d026538c592d06cc6db7fff4967f4e78447ac.tar.xz
stats: Update stats for cache retry event check
This patch updates the stats for the affected stats. All the changes are minimal (in the <0.01% range).
Diffstat (limited to 'tests/quick/fs')
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt58
-rw-r--r--tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt58
-rw-r--r--tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt58
3 files changed, 87 insertions, 87 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
index 91c2fb18d..af1133d44 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.954691 # Nu
sim_ticks 1954691371500 # Number of ticks simulated
final_tick 1954691371500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 888978 # Simulator instruction rate (inst/s)
-host_op_rate 888978 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29292473013 # Simulator tick rate (ticks/s)
-host_mem_usage 331536 # Number of bytes of host memory used
-host_seconds 66.73 # Real time elapsed on the host
+host_inst_rate 1268205 # Simulator instruction rate (inst/s)
+host_op_rate 1268205 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41788272650 # Simulator tick rate (ticks/s)
+host_mem_usage 331540 # Number of bytes of host memory used
+host_seconds 46.78 # Real time elapsed on the host
sim_insts 59321614 # Number of instructions simulated
sim_ops 59321614 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 829376 # Number of bytes read from this memory
@@ -506,12 +506,12 @@ system.iocache.overall_misses::tsunami.ide 41726 #
system.iocache.overall_misses::total 41726 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21042998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21042998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10675580676 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10675580676 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10696623674 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10696623674 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10696623674 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10696623674 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10675582674 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10675582674 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10696625672 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10696625672 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10696625672 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10696625672 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -530,12 +530,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120936.770115 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120936.770115 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256920.982769 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 256920.982769 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 256353.920194 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 256353.920194 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 256353.920194 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 256353.920194 # average overall miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256921.030853 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 256921.030853 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 256353.968077 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 256353.968077 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 256353.968077 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 256353.968077 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 286338 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27305 # number of cycles access was blocked
@@ -556,12 +556,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41726
system.iocache.overall_mshr_misses::total 41726 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11994249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11994249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8513588925 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8513588925 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8525583174 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8525583174 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8525583174 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8525583174 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8513590923 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8513590923 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8525585172 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8525585172 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8525585172 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8525585172 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -572,12 +572,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68932.465517 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68932.465517 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204889.991456 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 204889.991456 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204323.040167 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 204323.040167 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204890.039541 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 204890.039541 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 204323.088051 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 204323.088051 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 204323.088051 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 204323.088051 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
index 9db64d392..0c66e643a 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 1.913475 # Nu
sim_ticks 1913474690000 # Number of ticks simulated
final_tick 1913474690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 960952 # Simulator instruction rate (inst/s)
-host_op_rate 960952 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32757999490 # Simulator tick rate (ticks/s)
-host_mem_usage 329472 # Number of bytes of host memory used
-host_seconds 58.41 # Real time elapsed on the host
+host_inst_rate 985591 # Simulator instruction rate (inst/s)
+host_op_rate 985591 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33597920761 # Simulator tick rate (ticks/s)
+host_mem_usage 329492 # Number of bytes of host memory used
+host_seconds 56.95 # Real time elapsed on the host
sim_insts 56131527 # Number of instructions simulated
sim_ops 56131527 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
@@ -200,12 +200,12 @@ system.iocache.overall_misses::tsunami.ide 41725 #
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 20927998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 20927998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10653271428 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10653271428 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10674199426 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10674199426 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10674199426 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10674199426 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide 10653273426 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10653273426 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide 10674201424 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10674201424 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide 10674201424 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10674201424 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
@@ -224,12 +224,12 @@ system.iocache.overall_miss_rate::tsunami.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120971.086705 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 120971.086705 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.083269 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 256384.083269 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 255822.634536 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 255822.634536 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 255822.634536 # average overall miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256384.131353 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 256384.131353 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 255822.682421 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 255822.682421 # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 255822.682421 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 255822.682421 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 285520 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 27149 # number of cycles access was blocked
@@ -250,12 +250,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41725
system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11931249 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 11931249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491261949 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8491261949 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8503193198 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8503193198 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8503193198 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8503193198 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8491263947 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8491263947 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide 8503195196 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8503195196 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide 8503195196 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8503195196 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
@@ -266,12 +266,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68966.757225 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68966.757225 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.665311 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.665311 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.328892 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203791.328892 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 204352.713395 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 204352.713395 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203791.376777 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 203791.376777 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203791.376777 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203791.376777 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
index 2f6691c8d..064236544 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 5.195162 # Nu
sim_ticks 5195162021000 # Number of ticks simulated
final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 697576 # Simulator instruction rate (inst/s)
-host_op_rate 1344736 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 28252317760 # Simulator tick rate (ticks/s)
-host_mem_usage 611664 # Number of bytes of host memory used
-host_seconds 183.88 # Real time elapsed on the host
+host_inst_rate 434432 # Simulator instruction rate (inst/s)
+host_op_rate 837466 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17594801878 # Simulator tick rate (ticks/s)
+host_mem_usage 611684 # Number of bytes of host memory used
+host_seconds 295.27 # Real time elapsed on the host
sim_insts 128273373 # Number of instructions simulated
sim_ops 247275988 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
@@ -208,12 +208,12 @@ system.iocache.overall_misses::pc.south_bridge.ide 47564
system.iocache.overall_misses::total 47564 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732357682 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10732357682 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 10870344079 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10870344079 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 10870344079 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10870344079 # number of overall miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732360679 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 10732360679 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 10870347076 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 10870347076 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 10870347076 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 10870347076 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
@@ -232,12 +232,12 @@ system.iocache.overall_miss_rate::pc.south_bridge.ide 1
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.559974 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 229716.559974 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 228541.419540 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.419540 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 228541.419540 # average overall miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.624122 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 229716.624122 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 228541.482550 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 228541.482550 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked
@@ -258,12 +258,12 @@ system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564
system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301559588 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8301559588 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8395637015 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395637015 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8395637015 # number of overall MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301562585 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 8301562585 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 8395640012 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 8395640012 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
@@ -274,12 +274,12 @@ system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.491182 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.491182 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.425679 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 176512.425679 # average overall mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.555330 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.555330 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).